CN114501779B

CN114501779B - Substrate, packaging structure, board-level architecture and manufacturing method of substrate

Info

Publication number: CN114501779B
Application number: CN202111644558.XA
Authority: CN
Inventors: 于超伟; 谢振霖; 高峰
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-12-29
Filing date: 2021-12-29
Publication date: 2024-06-14
Anticipated expiration: 2041-12-29
Also published as: CN114501779A; WO2023124883A1

Abstract

The embodiment of the application provides a substrate, a packaging structure, a board-level architecture and a manufacturing method of the substrate, wherein the substrate comprises the following components: the fan-in structure comprises a fan-out structure and at least one group of fan-in structures, wherein each group of fan-in structures is internally provided with a fan-in via hole, the fan-out structure is internally provided with a fan-out via hole corresponding to the fan-in via hole, and the fan-in via hole is communicated with the fan-out via hole; and each group of the fan-in structures and the fan-out structures are connected through a sintering process in a stacking manner. The substrate in the embodiment of the application can improve the strength of the substrate, reduce the warping of the substrate, and further improve the connection reliability between the substrate and the circuit board as well as between the substrate and the electronic components, thereby improving the overall reliability of the substrate.

Description

Substrate, packaging structure, board-level architecture and manufacturing method of substrate

Technical Field

The embodiment of the application relates to the technical field of integrated circuit packaging, in particular to a substrate, a packaging structure, a board-level architecture and a manufacturing method of the substrate.

Background

With the continuous development of science and technology, high-speed system architecture puts higher and higher demands on high-speed performance of signal transmission.

Currently, electrical connection is achieved between a substrate and a circuit board (Printed circuit board, PCB) or electronic component in a board level architecture by solder ball bonding. In the soldering process, the solder balls are required to be heated, and the substrate and the circuit board or the electronic component are heated in the heating process, but the substrate and the circuit board or the electronic component are warped due to unbalanced temperatures of upper and lower parts of the substrate and the circuit board or the electronic component. In addition, warpage occurs under the action of self gravity for larger substrates and circuit boards or electronic components.

However, after the soldering is completed, the substrate and the circuit board or the electronic component may return to the original shape with a decrease in temperature, resulting in a soldering stress on the solder joint, which may increase the risk of solder cracking between the substrate and the circuit board or the electronic component.

Disclosure of Invention

The embodiment of the application provides a substrate, a packaging structure, a board-level framework and a manufacturing method of the substrate, which can improve the strength of the substrate, reduce the warpage of the substrate, and further improve the connection reliability between the substrate and a circuit board as well as between the substrate and an electronic component, so that the overall reliability of the substrate can be improved.

In a first aspect, an embodiment of the present application provides a substrate, including at least: the fan-in structure comprises a fan-out structure and at least one group of fan-in structures, wherein each group of fan-in structures is internally provided with a fan-in via hole, the fan-out structure is internally provided with a fan-out via hole corresponding to the fan-in via hole, and the fan-in via hole is communicated with the fan-out via hole; and each group of the fan-in structures and the fan-out structures are connected through a sintering process in a stacking manner.

According to the substrate provided by the embodiment of the application, the electrical conduction of the substrate can be realized by arranging the fan-in via hole and the fan-out via hole and conducting the fan-in via hole and the fan-out via hole so as to be electrically connected with the electronic component and the circuit board; through link to each other through the technology range upon range of sintering between fan-in structure and the fan-out structure at least a set of fan-in structure, form one deck compact structure through the sintering between fan-in structure and the fan-out structure like this, make the inner structure of base plate more compact like this, the intensity of base plate has been increased, the sintering technology can make fan-in structure and fan-out structure fixed connection under high temperature pressfitting in addition, and sintering temperature often is higher than welding temperature, so make base plate and circuit board or electronic components be difficult for taking place the warpage when welding like this, thereby avoided the risk of solder joint fracture between base plate and the circuit board. Thereby increasing the reliability of the connection between the substrate and the circuit board and reducing the reliability risk of solder ball solder cracking between the substrate and the circuit board. Therefore, the embodiment of the application can improve the strength of the substrate, thereby reducing the warping of the substrate and improving the overall reliability of the substrate. In addition, when the fan-in structure and the fan-out structure are connected through the sintering process, the strength of the substrate is ensured due to the compact structure formed between the fan-in structure and the fan-out structure, so that the overall thickness of the substrate can be greatly reduced, the difficulty of opening holes in the fan-in structure and the fan-out structure is reduced, and therefore the fan-in structure with high density can be realized, and the fan-out density of the fan-out structure is improved.

In one possible implementation manner, a semi-fixed layer is arranged between each group of the fan-in structures and the fan-out structures, and a sintering layer corresponding to each fan-in via hole and each fan-out via hole is arranged in the semi-fixed layer; the sintering layer is respectively connected with the fan-in via hole and the fan-out via hole through a sintering process, and the fan-in via hole is communicated with the fan-out via hole through the sintering layer.

According to the substrate, the semi-fixed layer is arranged, so that the sintering layer can be conveniently arranged in the semi-fixed layer, and the semi-fixed layer can isolate, protect and pre-fix the fan-in structure and the fan-out structure in the sintering process. In addition, through setting up the semi-fixed layer, because semi-fixed layer material is softer, conveniently punches, can be convenient like this with sintered layer setting in the semi-fixed layer, on the one hand reduce the processing degree of difficulty of base plate, on the other hand can conveniently switch on between fan-in structure and the fan-out structure. In addition, the sintering layer can realize the conduction of the fan-in via hole and the fan-out via hole, thus, the conductive material layer is added between the fan-in structure and the fan-out structure, and the conductive material is often inorganic material, so that after the sintering is finished, a compact inorganic structure is added between the fan-in structure and the fan-out structure in the substrate, the strength of the substrate is improved, and the warping phenomenon of the substrate in the welding process is reduced.

In one possible implementation manner, a first fan-in conducting layer which is in graphical design is arranged on one surface of the fan-in structure facing the semi-fixed layer, and the first fan-in conducting layer is electrically connected with the fan-in via hole; a first fan-out conducting layer which is in graphical design is arranged on one surface of the fan-out structure facing the semi-fixed layer, and the first fan-out conducting layer is electrically connected with the fan-out via hole; the sintering layer is located between the first fan-in conducting layer and the first fan-out conducting layer, and is connected with the first fan-in conducting layer and the first fan-out conducting layer through sintering respectively so as to conduct the fan-in via holes and the fan-out via holes.

According to the substrate provided by the embodiment of the application, the first fan-in conducting layer and the first fan-out conducting layer are arranged, and the sintering layer is respectively connected with the first fan-in conducting layer and the first fan-out conducting layer in a sintering manner, so that the first fan-in conducting layer and the first fan-out conducting layer are stably and fixedly connected, the strength of the first fan-in conducting layer and the first fan-out conducting layer is improved, and the fan-in via hole and the fan-out via hole can be conveniently conducted.

In one possible implementation, each set of the fan-in structures includes: the fan-in wiring layer is internally provided with the fan-in via hole and a second fan-in conductive layer electrically connected with the fan-in via hole.

In the embodiment of the application, the fan-in wiring layer is arranged to provide a setting space for the through holes, so that the density of the through holes in the substrate is improved, and the transmission speed of the substrate is improved.

In one possible implementation, the fan-in wiring layer includes at least one fan-in dielectric layer, each of the fan-in dielectric layers including a fan-in dielectric layer, the fan-in via disposed within the fan-in dielectric layer, and the second fan-in conductive layer disposed on the dielectric layer.

Thus, the fan-out structure and the fan-out structure can be conducted by arranging at least one fan-out dielectric layer, and the substrate and the electronic component can be electrically connected by arranging the second fan-in conductive layer.

In one possible implementation, the fan-in dielectric layer is a plurality of layers, and a distance between two adjacent second fan-in conductive layers in the topmost of the plurality of layers of fan-in dielectric layers is 130um or less.

In addition, through dividing the fan-in structure into a plurality of fan-in dielectric layers, the number of the through holes in the single fan-in dielectric layer can be reduced, on one hand, the setting difficulty of the through holes can be reduced, on the other hand, the high-density integration of the substrate can be realized, because the smaller the distance between the two second fan-in conductive layers is, the more the fan-in of the substrate is, the more upper modules (such as chips and the like) can be connected with the substrate, so that the high-density integration is realized, and the requirements of a high-speed transmission system are met.

In one possible implementation, the fan-in dielectric layer is an insulating layer made of silicon oxide, polyimide, or polypropylene.

Compared with the substrate in the prior art, which adopts ABF resin as a dominant material, the substrate in the embodiment of the application has small signal difference, is beneficial to improving the signal integrity (also called SI performance) of the substrate and is beneficial to realizing high-density integration of the substrate by arranging the fan-in dielectric layer as the insulating layer made of silicon oxide, polyimide or polypropylene. In addition, the insulating layer of silicon oxide, polyimide or polypropylene has better strength, which is beneficial to improving the strength of the substrate, thereby reducing the warping of the substrate.

In one possible implementation, each set of the fan-in structures further includes: the fan-in carrier plate is arranged in a lamination mode with the fan-in wiring layer, the fan-in through holes are formed in the fan-in carrier plate, and the fan-in through holes in the fan-in carrier plate are communicated with the fan-in through holes in the fan-in wiring layer.

Support can be provided for the fan-in wiring layer through setting up the fan-in carrier plate to increase the intensity of fan-in structure, when being in the same place fan-in structure and fan-out structure link together, conveniently fix like this. And the fan-in carrier plate can reduce the risk of breaking the fan-in structure. The strength of the whole substrate can be enhanced by arranging the fan-in carrier plate, so that the warping can be reduced. In addition, through setting up the fan-in via hole on the fan-in carrier plate, can guarantee that fan-out via hole and fan-in via hole switch on, and then improve the SI performance of base plate.

In one possible implementation, the fan-in carrier plate is located between the fan-in wiring layer and the fan-out structure, and the fan-in carrier plate and the fan-out structure are connected by a sintering process.

Therefore, the fan-in structure and the fan-out structure can be connected stably by sintering the fan-in structure and the fan-out structure, and the stability of the substrate is improved.

In one possible implementation, a distance between two adjacent fan-in vias in the fan-in carrier plate is greater than or equal to 300um and less than or equal to 500um.

Because too dense through holes on the fan-in carrier plate can reduce the strength of the fan-in carrier plate and can improve the punching difficulty, the self strength of the fan-in carrier plate can be ensured and the processing difficulty of the fan-in carrier plate can be reduced by setting the spacing between the through holes on the fan-in carrier plate to be more than or equal to 300um and less than or equal to 500um in the embodiment of the application.

In one possible implementation, the fan-in wiring layer is located between the fan-in carrier plate and the fan-out structure, and the fan-in wiring layer is sintered and connected with the fan-out structure; and the second fan-in conducting layer is arranged on one surface of the fan-in carrier plate, which is opposite to the fan-in wiring layer.

Through setting up the fan-in wiring layer between fan-in carrier plate and fan-out structure to be equipped with the second fan-in conducting layer on the fan-in carrier plate one side of fan-in wiring layer dorsad, can conveniently realize the electricity with between fan-in carrier plate and the fan-out structure and connect, so that fan-out structure and fan-in structure switch on.

In one possible implementation manner, a distance between two adjacent second fan-in conductive layers on the fan-in carrier plate is less than or equal to 130um.

Through the interval design of two adjacent second fan-in conducting layers less than or equal to 130um, can improve the density of fan-in conducting layer like this to be favorable to improving the fan-in density on the base plate, be favorable to the high transmission of base plate.

In one possible implementation, the coefficient of thermal expansion of the fan-in carrier plate is less than 5ppm, and the modulus of elasticity of the fan-in carrier plate is greater than or equal to 100Gpa.

According to the substrate in the embodiment of the application, the thermal expansion coefficient of the fan-in carrier plate is smaller than 5ppm, the elastic modulus is larger than or equal to 100Gpa, the strength of the fan-in carrier plate meeting the index is high, and the strength of the whole substrate is correspondingly improved due to the high strength of the fan-in carrier plate, so that the warping of the whole substrate can be reduced, and the connection stability between the substrate and the circuit board or the electronic component is ensured during use.

In one possible implementation, the fan-in carrier plate is an inorganic plate made of inorganic material.

The fan-in carrier plate is designed to be an inorganic plate, and the inorganic plate is small in thermal expansion coefficient and large in elastic modulus, so that the strength requirement of the fan-in carrier plate can be met, and the warping problem of the substrate can be reduced. In addition, the inorganic board can be made thinner than the organic board in the prior art, so that the thickness of the substrate can be reduced while the strength of the substrate is increased. The inorganic carrier plate has compact internal structure relative to the organic carrier plate, has larger strength and is not easy to deform, so that the warping problem can be improved, and the problem of supplying the large-size carrier plate is solved.

In one possible implementation, the inorganic plate is a glass plate or a ceramic plate.

Through setting up inorganic board into glass board or ceramic plate, because glass board and ceramic plate are more common, and the low price, consequently can be with the manufacturing cost of first base plate, in addition, glass board and ceramic plate surface smoothness are cleared up easily, can reduce the impurity of fan-in carrier plate surface like this, so can reduce the washing cost to the fan-in carrier plate at the production base plate, and then practice thrift the manufacturing cost of base plate to can improve production efficiency.

In one possible implementation, the fan-in structures are multiple groups, and multiple groups of the fan-in structures are spaced apart and arranged on the fan-out structure in parallel.

Thus, by arranging a plurality of groups of fan-in structures, the fan-in density on the substrate can be increased so as to meet the requirements of a high-speed transmission system. In addition, through setting up multiunit fan-in structure, can also connect a plurality of electronic components (can be the chip) at the fan-in end, the FC-BGA base plate in the prior art is used for single chip encapsulation, and the base plate in the embodiment of the application has the advantage of many scene application.

In one possible implementation, the fan-out structure includes at least: at least one fan-out wiring layer, wherein each fan-out wiring layer is internally provided with a fan-out via hole and a second fan-out conductive layer electrically connected with the fan-out via hole; the fan-out wiring layer is sintered and connected with the fan-in structure.

In the embodiment of the application, the fan-out wiring layer is arranged on the fan-out structure, so that a space is provided for the fan-out via hole; the fan-in structure is electrically connected with the fan-out through hole by arranging a second fan-out conducting layer in the fan-out through hole; the fan-out wiring layer and the fan-in structure are sintered and connected, so that the fan-in structure and the fan-out structure are fixedly connected, the rigidity of the substrate is improved, and the warping of the substrate can be reduced.

In one possible implementation, the fan-out structure further includes: the fan-out carrier plate and the fan-out wiring layer are arranged in a stacked mode; the number of the fan-out wiring layers is two, and the fan-out carrier plate is positioned between the two fan-out wiring layers; the fan-out carrier plate is internally provided with the fan-out via hole, and the fan-out via hole in the fan-out carrier plate is communicated with the fan-out via hole in the fan-out wiring layer.

In the embodiment of the application, the fan-out carrier plate is arranged to provide support for the fan-out wiring layer, so that the strength of the fan-out structure is increased, and the fan-out structure and the fan-in structure are conveniently fixed when being connected together. And setting up fan-out carrier plate can reduce the cracked risk of fan-out structure. The strength of the whole substrate can be enhanced by arranging the fan-out carrier plate, so that the warping can be reduced. Through set up fan out via hole on fan-out carrier plate, can guarantee fan out via hole and fan-in via hole and switch on, and then improve the SI performance of base plate. In addition, through setting up fan-out carrier plate and adding the fan-in carrier plate of fan-in structure, can make the base plate have two carrier plate structures, can further improve the intensity of base plate like this, and then reduce the warpage.

In one possible implementation, each of the fan-out wiring layers includes at least one fan-out dielectric layer, each of the fan-out dielectric layers including a fan-out dielectric layer, the fan-out via disposed within the fan-out dielectric layer, and the second fan-out conductive layer disposed on the fan-out dielectric layer and electrically connected with the fan-out via.

Thus, the fan-out structure and the fan-out structure can be made conductive by providing at least one fan-out dielectric layer. The second fan-out conductive layer is arranged to facilitate electrical connection with the circuit board.

In one possible implementation, each of the fan-out wiring layers includes a plurality of the fan-out dielectric layers, the plurality of the fan-out dielectric layers being stacked.

Through setting up multilayer fan-out dielectric layer, can improve the fan-out density in the base plate, in addition, through establishing fan-out structure separately in a plurality of fan-out dielectric layers, can reduce the via hole quantity in the single fan-out dielectric layer, can reduce the setting degree of difficulty of via hole on the one hand, on the other hand can realize the high density integration of base plate.

In one possible implementation, a plurality of discrete devices are disposed within the fan-out structure, the plurality of discrete devices being horizontally spaced apart within the fan-out structure.

By providing a plurality of discrete devices within the fan-out structure, the power integrity performance (PI performance) of the substrate may be improved.

In one possible implementation, the discrete device is a capacitor or an inductor. In a second aspect, embodiments of the present application provide a substrate, which may include: a fan-out structure and at least one set of fan-in structures; each group of the fan-in structures comprises a fan-in wiring layer and a fan-in wiring layer, the fan-in wiring layer and the fan-in carrier plate are both arranged in a lamination manner with the fan-out structure, and the fan-in carrier plate is positioned between the fan-in wiring layer and the fan-out structure or the fan-in wiring layer is positioned between the fan-in carrier plate and the fan-out structure; and the thermal expansion coefficient of the fan-in carrier plate is smaller than 5ppm, and the elastic modulus of the fan-in carrier plate is larger than or equal to 100Gpa.

The substrate in the embodiment of the application can provide support for the fan-in wiring layer by arranging the fan-in carrier plate, so that the strength of the fan-in structure is increased, and the fan-in structure and the fan-out structure are conveniently fixed when being connected together. And the fan-in carrier plate can reduce the risk of breaking the fan-in structure. The strength of the whole substrate can be enhanced by arranging the fan-in carrier plate, so that the warping can be reduced. In addition, through setting up the fan-in via hole on the fan-in carrier plate, can guarantee that fan-out via hole and fan-in via hole switch on, and then improve the SI performance of base plate.

In one possible implementation, the fan-out structure includes: and the fan-out wiring layer is connected with the fan-in carrier plate or connected with the fan-in wiring layer.

Through setting up fan-out wiring layer, can conveniently switch on fan-out structure and fan-in structure.

In one possible implementation, the fan-out wiring layer is connected with the fan-in carrier plate or the fan-in wiring layer through a sintering process; or the fan-out wiring layer is connected with the fan-in carrier plate or the fan-in wiring layer through a welding process; or one surface of the fan-in carrier plate forms the fan-out wiring layer in a semiconductor deposition mode.

According to the embodiment of the application, the fan-in wiring layer and the fan-in carrier plate or the fan-in wiring layer are fixedly connected in a sintering, welding or semiconductor deposition mode, so that the connection stability of the fan-in structure and the fan-out structure can be improved, and the strength of the substrate is further improved. In addition, the sintering process can also reduce warpage of the substrate.

In one possible implementation, the fan-in carrier plate is located between the fan-in wiring layer and the fan-out structure; a semi-fixed layer is arranged between the fan-in carrier plate and the fan-out wiring layer, and a sintering layer corresponding to the through holes in the fan-in carrier plate and the through holes in the fan-out wiring layer is arranged in the semi-fixed layer; the sintering layer is respectively connected with the through holes in the fan-in carrier plate and the through holes in the fan-out wiring layer through a sintering process, and the through holes in the fan-in carrier plate are communicated with the through holes in the fan-out wiring layer through the sintering layer.

According to the substrate, the semi-fixed layer is arranged, so that the sintering layer can be conveniently arranged in the semi-fixed layer, and the semi-fixed layer can isolate and protect the fan-in structure and the fan-out structure in the sintering process. In addition, through setting up the semi-fixed layer, because semi-fixed layer material is softer, conveniently punches, can be convenient like this with sintered layer setting in the semi-fixed layer, on the one hand reduce the processing degree of difficulty of base plate, on the other hand can conveniently switch on between fan-in structure and the fan-out structure. In one possible implementation, the fan-in carrier plate is located between the fan-in wiring layer and the fan-out structure; and solder balls are arranged between the fan-in carrier plate and the fan-out wiring layer, and the through holes in the fan-in carrier plate and the through holes in the fan-out wiring layer are communicated through the corresponding solder balls.

In one possible implementation, the fan-out structure further includes: the fan-out wiring layers are respectively arranged on two sides of the fan-out carrier plate in a stacked mode; one fan-out wiring layer is connected with the fan-in carrier plate or the fan-in wiring layer, and the two fan-out wiring layers are conducted through holes arranged on the fan-out carrier plate.

In the embodiment of the application, the fan-out carrier plate is arranged to provide support for the fan-out wiring layer, so that the strength of the fan-out structure is increased, and the fan-out structure and the fan-in structure are conveniently fixed when being connected together. And setting up fan-out carrier plate can reduce the cracked risk of fan-out structure. The strength of the whole substrate can be enhanced by arranging the fan-out carrier plate, so that the warping can be reduced. Through set up fan out via hole on fan-out carrier plate, can guarantee fan out via hole and fan-in via hole and switch on, and then improve the SI performance of base plate. In addition, through setting up fan-out carrier plate and adding the fan-in carrier plate of fan-in structure, can make the base plate have two carrier plate structures, can further improve the intensity of base plate like this, and then reduce the warpage. In one possible implementation, a patterned upper conductive layer is disposed on one side of the fan-in carrier plate; a patterned lower conductive layer is arranged on the other surface of the fan-in carrier plate; a via hole is arranged in the fan-in carrier plate and is used for conducting the upper conductive layer and the lower conductive layer; and fan-in through holes are formed in the fan-in wiring layer, fan-out through holes are formed in the fan-out structure, and the fan-in through holes are communicated with the fan-out through holes in the fan-in carrier plate, the upper conducting layer and the lower conducting layer. In one possible implementation, the fan-in wiring layer includes at least one fan-in dielectric layer, each of the fan-in dielectric layers including a fan-in dielectric layer, the fan-in via disposed within the fan-in dielectric layer, and a fan-in conductive layer disposed on the dielectric layer and electrically connected to the fan-in via.

Thus, the fan-out structure and the fan-out structure can be conducted by arranging at least one fan-out dielectric layer, and the substrate and the electronic component can be electrically connected by arranging the second fan-in conductive layer. In one possible implementation, each of the fan-out routing layers in the fan-out structure includes at least one fan-out dielectric layer, each of the fan-out dielectric layers including a fan-out dielectric layer, the fan-out via disposed within the fan-out dielectric layer, and a fan-out conductive layer disposed on the fan-out dielectric layer and electrically connected with the fan-out via.

In one possible implementation, when the fan-in carrier board is located between the fan-in wiring layer and the fan-out structure, a distance between two adjacent fan-in conductive layers in the topmost fan-in dielectric layer in the fan-in wiring layer is less than or equal to 130um.

Therefore, the fan-in density in the substrate can be improved by setting the interval between two adjacent fan-in conducting layers in the fan-in medium layer at the topmost end of the fan-in wiring layer to be less than or equal to 130um, and the high-density integration of the substrate is facilitated so as to meet the requirements of a high-speed transmission system.

In one possible implementation, the fan-in dielectric layer in the fan-in wiring layer and the fan-out dielectric layer in the fan-out wiring layer are both insulating layers made of silicon oxide, polyimide or polypropylene.

Compared with the substrate in the prior art, which adopts ABF resin as a dominant material, the substrate in the embodiment of the application has small signal difference, is beneficial to improving the signal integrity (also called SI performance) of the substrate and is beneficial to realizing high-density integration of the substrate by arranging the fan-in dielectric layer as the insulating layer made of silicon oxide, polyimide or polypropylene. In addition, the insulating layer of silicon oxide, polyimide or polypropylene has better strength, which is beneficial to improving the strength of the substrate, thereby reducing the warping of the substrate. In one possible implementation, the fan-in structures are multiple groups, and multiple groups of the fan-in structures are arranged on the fan-out structure at intervals.

In one possible implementation manner, a plurality of discrete devices are disposed in the fan-out structure, and the plurality of discrete devices are horizontally spaced in the fan-out wiring layer.

In one possible implementation, the discrete device is a capacitor or an inductor.

In one possible implementation, the fan-out carrier is an inorganic board or the fan-out carrier is an organic board.

In a third aspect, an embodiment of the present application provides an encapsulation structure, where the encapsulation structure includes at least one electronic component, and the substrate described above, where the electronic component is disposed on a fan-in structure of the substrate, and the electronic component is electrically connected to a fan-in via hole in the fan-in structure.

According to the packaging structure provided by the embodiment of the application, the strength of the whole packaging structure can be improved by arranging the substrate, so that the warping of the substrate can be reduced. And through setting up at least one electronic components (can be the chip), the FC-BGA base plate in contrast to prior art is used for single chip encapsulation, the base plate in the embodiment of the application has the advantage of many scene application.

In a fourth aspect, an embodiment of the present application provides a board-level architecture, where the board-level architecture includes a circuit board, at least one electronic component, and the substrate described above, where the substrate is located between the circuit board and the electronic component, and the electronic component is connected to a fan-in structure in the substrate, and the circuit board is connected to a fan-out structure in the substrate.

According to the board-level framework provided by the embodiment of the application, the strength of the whole board-level framework can be improved by arranging the substrate, and the connection stability between the substrate and the circuit board is higher because the substrate has small warpage. In addition, the size of the board-level framework can be large, and a plurality of electronic components can be connected, so that the multi-application-scene capability of the board-level framework is improved.

In one possible implementation manner, the electronic components are multiple, the fan-in structures in the substrate are a group, and the multiple electronic components are arranged on the fan-in structures at intervals.

The multi-scene applicability of the board-level architecture can be improved by arranging a set of fan-in structures and arranging a plurality of electronic components on the set of fan-in structures.

In one possible implementation manner, the number of the electronic components is multiple, the number of the fan-in structures in the substrate is multiple, and one or more electronic components are arranged on each fan-in structure.

By arranging a plurality of groups of fan-in structures, the manufacture of a large-size board-level framework can be realized. In addition, the fan-in density of the board level framework can be improved by arranging a plurality of groups of fan-in structures, so that the board level framework is beneficial to high-speed transmission, and the board level framework is suitable for application of high-density circuits.

In one possible implementation, the fan-out structure is connected with the circuit board through a sintering process; or the fan-out structure is connected with the circuit board through welding.

Through passing through sintering or welding fan-out structure and circuit board, can be with base plate and circuit board stable connection, and then improve the connection stability of board level framework.

In a fifth aspect, an embodiment of the present application provides a method for manufacturing a substrate, where the method includes: providing a fan-out structure and at least one set of fan-in structures, wherein each set of fan-in structures comprises a carrier plate and a fan-in wiring layer formed on the carrier plate; the fan-out structure is connected with the fan-in structure in a stacked mode, and the fan-in wiring layer is located between the carrier plate and the fan-out structure; and removing the carrier plate to form the substrate.

According to the embodiment of the application, the carrier plate is arranged firstly, so that the fan-in wiring layer can be conveniently arranged on the carrier plate, and the carrier plate can provide support for the fan-in wiring layer, thereby facilitating processing and being beneficial to realizing high-density integration of the fan-in structure. In addition, for some substrates with smaller sizes, the warping of the substrate is smaller, so the strength requirement on the substrate is lower, the carrier plate is removed after the fan-in wiring layer is arranged, the weight of the substrate can be reduced on the premise of ensuring high-density integration of the substrate, the substrate is lighter, and the production cost of the substrate can be reduced. In addition, the carrier plate is removed, and through holes are not required to be arranged on the carrier plate, so that the processing difficulty of the substrate can be reduced.

In a sixth aspect, an embodiment of the present application provides a method for manufacturing a substrate, where the method includes: providing a fan-out structure and at least one set of fan-in structures, wherein each set of fan-in structures comprises a fan-in carrier plate and a fan-in wiring layer arranged on the fan-in carrier plate; a patterned semi-cured layer is arranged on one surface of the fan-out structure, and a sintering layer is arranged in the semi-cured layer; and pressing and sintering at least one group of fan-in structures and the fan-out structures provided with the semi-solidified layers and the sintering layers, wherein the semi-solidified layers and the sintering layers are positioned between the fan-in carrier plates and the fan-out structures, so that the fan-in carrier plates are connected with the fan-out structures in a sintering manner, and fan-in through holes in the fan-in structures are communicated with the fan-out through holes in the fan-out structures through the sintering layers.

Thus, by sintering the fan-out structure and at least one set of fan-in structures, integration of a large-sized substrate can be achieved. The fan-in structure and the fan-out structure are connected in a sintering mode, so that the fan-out structure and the fan-in structure are stable, the strength of the substrate is improved, and the warping of the substrate is reduced. By arranging the semi-cured structure between the fan-in carrier plate and the fan-out structure, the requirement on sintering equipment can be reduced, and the fan-in structure and the fan-out structure can be sintered together by only a common high-temperature pressing machine (the highest temperature is about 220 ℃).

In a seventh aspect, an embodiment of the present application provides a method for manufacturing a substrate, where the method includes: providing a fan-out structure and at least one set of fan-in structures, wherein each set of fan-in structures comprises a fan-in carrier plate and a fan-in wiring layer arranged on the fan-in carrier plate; a patterned semi-cured layer is arranged on one surface of the fan-out structure, and a sintering layer is arranged in the semi-cured layer; at least one group of fan-in structures and the fan-out structures formed with the semi-solidified layers and the sintering layers are pressed and sintered, the semi-solidified layers and the sintering layers are positioned between the fan-in wiring layers and the fan-out structures, so that the fan-in wiring layers are connected with the fan-out structures in a sintering mode, and fan-in through holes in the fan-in structures are communicated with the fan-out through holes in the fan-out structures through the sintering layers.

Thus, by sintering the fan-out structure and at least one set of fan-in structures, integration of a large-sized substrate can be achieved. The fan-in structure and the fan-out structure are connected in a sintering mode, so that the fan-out structure and the fan-in structure are stable, the strength of the substrate is improved, and the warping of the substrate is reduced. Through setting up half solidification between fan-in wiring layer and fan-out structure, can make fan-in carrier plate and electronic components be connected when using like this, it is convenient to connect.

Drawings

FIG. 1 is a schematic diagram of a substrate according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a substrate according to an embodiment of the present application;

FIG. 3 is a schematic diagram of a substrate according to an embodiment of the present application;

Fig. 4 is a schematic structural diagram of a fan-in carrier of a substrate according to an embodiment of the present application;

FIG. 5 is a schematic diagram of a substrate according to an embodiment of the present application;

FIG. 6 is a schematic structural diagram of a substrate according to an embodiment of the present application;

FIG. 7 is a schematic diagram of a substrate according to an embodiment of the application;

FIG. 8 is a schematic diagram of a substrate according to an embodiment of the present application;

FIG. 9 is a schematic diagram of a substrate according to an embodiment of the present application;

FIG. 10 is a schematic diagram of a substrate according to an embodiment of the present application;

FIG. 11 is a schematic diagram of a substrate according to an embodiment of the application;

FIG. 12 is a schematic view of a substrate according to an embodiment of the present application;

FIG. 13 is a schematic view of a substrate according to an embodiment of the present application;

FIG. 14 is a schematic view of a substrate according to an embodiment of the present application;

FIG. 15 is a schematic view of a substrate according to an embodiment of the present application;

FIG. 16 is a schematic view of a substrate according to an embodiment of the present application;

FIG. 17 is a schematic diagram of a substrate according to an embodiment of the present application;

FIG. 18 is a schematic diagram of a substrate according to an embodiment of the present application;

fig. 19 is a schematic structural diagram of a package structure according to an embodiment of the application;

FIG. 20 is a schematic diagram of a package structure according to an embodiment of the present application;

FIG. 21 is a schematic diagram of a board-level architecture according to an embodiment of the present application;

FIG. 22 is a schematic diagram of a board-level architecture according to an embodiment of the present application;

FIG. 23 is a schematic diagram of a board-level architecture according to an embodiment of the present application;

FIG. 24 is a schematic diagram of a board-level architecture according to an embodiment of the present application;

FIG. 25A is a schematic diagram of an exploded structure of a board level architecture according to an embodiment of the present application;

FIG. 25B is a schematic diagram of the board-level architecture of FIG. 25A;

FIG. 26A is a schematic diagram of an exploded structure of a board level architecture according to an embodiment of the present application;

FIG. 26B is a schematic diagram of the board-level architecture of FIG. 26A;

FIG. 27A is a schematic diagram of an exploded structure of a board level architecture according to an embodiment of the present application;

FIG. 27B is a schematic diagram of the board-level architecture of FIG. 27A;

FIG. 28A is an exploded view of a board level architecture according to an embodiment of the present application;

FIG. 28B is a schematic diagram of the board level architecture of FIG. 28A;

FIG. 29 is a flowchart illustrating a method for fabricating a substrate according to an embodiment of the present application;

Fig. 30 is a flow chart illustrating a method for fabricating a fan-in structure in a method for fabricating a substrate according to an embodiment of the present application;

Fig. 31 is a schematic structural diagram of a fan-in carrier in a method for manufacturing a substrate according to an embodiment of the application;

Fig. 32 is a schematic structural diagram of an insulating dielectric layer disposed on a fan-in carrier in a method for manufacturing a substrate according to an embodiment of the present application;

FIG. 33 is a schematic diagram of a structure of a metal layer disposed on an insulating dielectric layer in a method for fabricating a substrate according to an embodiment of the present application;

fig. 34 is a schematic structural diagram of a method for manufacturing a substrate according to an embodiment of the present application, in which a fan-in conductive layer is formed on a metal layer;

FIG. 35 is a schematic view of a fan-in structure in a method for fabricating a substrate according to an embodiment of the present application;

Fig. 36 is a flowchart illustrating a method for fabricating a fan-out structure in a method for fabricating a substrate according to an embodiment of the present application;

Fig. 37 is a schematic structural diagram of a fan-out carrier in a method for manufacturing a substrate according to an embodiment of the application;

FIG. 38 is a schematic view of a substrate manufacturing method according to an embodiment of the present application, in which two sides of a carrier plate are provided with a build-up layer;

fig. 39 is a schematic structural diagram of a fan-out structure in a method for manufacturing a substrate according to an embodiment of the application;

fig. 40 is a schematic structural diagram of a semi-cured layer disposed on a fan-out structure in a method for manufacturing a substrate according to an embodiment of the present application;

FIG. 41 is a schematic diagram of a structure of a semi-cured layer and a sintered layer disposed on a fan-out structure in a method for fabricating a substrate according to an embodiment of the present application;

FIG. 42 is a schematic diagram illustrating sintering and fixing a fan-in structure and a fan-out structure in a method for manufacturing a substrate according to an embodiment of the present application;

FIG. 43 is a flowchart illustrating a method for fabricating a substrate according to an embodiment of the application;

FIG. 44 is a flow chart of a method for fabricating a fan-in structure in a method for fabricating a substrate according to an embodiment of the application;

FIG. 45 is a schematic view of a structure of a fan-in carrier in a method for fabricating a substrate according to an embodiment of the present application;

fig. 46 is a schematic structural diagram of an insulating dielectric layer disposed on a fan-in carrier in a method for manufacturing a substrate according to an embodiment of the present application;

FIG. 47 is a schematic diagram of a structure of a metal layer disposed on an insulating dielectric layer in a method for fabricating a substrate according to an embodiment of the present application;

FIG. 48 is a schematic diagram illustrating a structure of a fan-in conductive layer formed on a metal layer in a method for fabricating a substrate according to an embodiment of the present application;

FIG. 49 is a schematic view of a fan-in structure in a method for fabricating a substrate according to an embodiment of the present application;

fig. 50 is a flowchart illustrating a method for manufacturing a substrate according to an embodiment of the application.

Reference numerals illustrate:

100. 200-a substrate; 110-fan-in configuration; 120. 220-fan-out structure; 130. 260-semi-fixed layer;

140. 240-discrete devices; 150. 270-a protective film; 160-through holes;

111. 210-fan-in wiring layer; 111a, 211-fan-in dielectric layer; 1111. 1121, 2111—fan-in via;

1112-a second fan-in conductive layer;

1113. 2113-fan-in dielectric layer; 112. 230-fan-in carrier plate; 231-vias; 232-an upper conductive layer; 233-a lower conductive layer;

1115. 2112-fanin conductive layer;

121. 221-a fan-out wiring layer; 121a, 221 a-fan-out dielectric layer; 1211. 1221, 2211, 2221-fan-out vias;

1222-a second fan-out conductive layer; 1213. 2213-a fanout dielectric layer; 1116. 2212-a fan-out conductive layer;

122. 222-fan-out carrier plate;

131. 261-sintering layer; 132-a first fan-in conductive layer; 133-a first fan-out conductive layer;

250. 1011, 1021, 2021-solder balls; 300-packaging structure; 101. 201-an electronic component; 102. 202-a circuit board;

1000-board level architecture; 1114. 2114-metal layer.

Detailed Description

The terminology used in the description of the embodiments of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application, as will be described in detail with reference to the accompanying drawings.

The circuit board is the provider of electrical connections for the electronic components. The chip is the most core part for the electronic equipment, and has the functions of logic processing and controlling the normal operation of the whole machine. In an electronic device, a chip and a substrate form a package structure, which is fixed on a printed circuit board to form a board level architecture that can control the conduction between the chip and an external circuit board within the package structure.

The Flip Chip Ball grid array (Flip Chip-Ball GRID ARRAY, FC-BGA) is a high-density semiconductor package substrate capable of realizing high-speed and multi-functions of Large-scale integrated circuit (LSI) chips, and has become a package form frequently used in the fields of high-end devices and high-density packages.

The FC-BGA substrate comprises a core plate arranged in the middle of the substrate and high-density wiring layers symmetrically stacked on two sides of the core plate, wherein the high-density wiring layers are arranged in the ABF material. During packaging, the FC-BGA substrate, the PCB and the chip are fixedly connected in a high-temperature welding mode, in the welding process, warpage is easy to generate due to the influences of the structure of the FC-BGA substrate and welding conditions, the larger the size of the substrate is, the larger the warpage generated is, and the risk of welding spot cracking reliability caused by warpage is extremely high.

It should be noted that ABF (Ajinomoto Buildup Film), ABF resin is a material mainly used by intel corporation for producing higher-order carrier boards such as flip chip packaging process, and is suitable for high-pin-count and high-transmission IC packages due to the fact that the carrier boards can be manufactured into thinner circuits. ABF material was uniquely manufactured by japan flavor company (Ajinomoto), and the manufacturer first began to use monosodium glutamate, food flavoring as an industry, and subsequently started the development of FC-BGA substrates along with Intel margins, resulting in ABF being essentially a standard material for CPU FC-BGA products.

In the prior art, in order to improve the warping problem, the core plate is generally thickened, but the thickening of the core plate can cause the thickness of the whole substrate to be increased, so that the lightweight development of the substrate is not facilitated; in addition, the thickening of the core plate also causes difficult punching, is influenced by the processing capability of the through holes, can cause the reduction of the layout density of the through holes, and is not beneficial to high-density integration; in addition, the FC-BGA substrate is affected by the through holes of the middle core plate, and in order to prevent signals from passing through the through holes of the middle core plate, the high-density wiring layers are arranged on one side, close to the chip, of the upper part of the core plate, but the FC-BGA substrate is manufactured by adopting a symmetrical layer adding process on two sides of the core plate, so that the wiring layers on one side, close to the PCB, of the core plate are wasted to a certain extent.

Or the integrated fan-out system technology (TSMC InFo SOW) technology of the platform is adopted to realize the core-free and PCB-free structure. However, the method cannot rely on the main form of the existing packaging structure, has harsh production conditions and high production cost.

Based on the above, the embodiment of the application provides a substrate, which is provided with a fan-in carrier plate on a fan-in structure so as to improve the strength of the substrate and further reduce the warping of the substrate. Compared with the prior art, the fan-in carrier plate is increased, the strength of the fan-in carrier plate is larger, the thickness of the fan-in carrier plate is smaller, the thickness of the substrate can be reduced while the strength of the substrate is increased, and the warping is reduced, so that the risk of cracking reliability of welding spots can be reduced.

In addition, the embodiment of the application also provides a substrate, which is fixedly connected with the fan-in structure and the fan-out structure in a sintering mode. Therefore, compared with the prior art, the high-temperature welding process is canceled, so that the warping generated in the welding process can be reduced, and the risk of cracking reliability of welding spots is further reduced.

By way of illustration, microscopic definition of sintering: the process of causing particles to bond, strength and densification and recrystallization is known as sintering, in which molecules (or atoms) in the solid state are attracted to each other and undergo migration by heating to obtain sufficient energy from the particles.

Sintering is defined macroscopically by the fact that at high temperatures (not higher than the melting point), the ceramic green solid particles bond with each other, the grains grow up, the voids (pores) and grain boundaries gradually decrease, the total volume of the material is contracted by mass transfer, the density increases, and finally a compact polycrystalline sintered body with a certain microstructure is formed, which phenomenon is called sintering.

Fan in: refers to the number of upper modules that directly call the module. The fan-in size indicates that the multiplexing of the module is high.

Fanning: the number of lower modules directly called by the module is referred to. The large fan-out represents a high complexity of the module, requiring control and coordination of the excessive number of subordinate modules.

The specific structure of the substrate, the package structure formed by using the substrate, the board level structure using the package structure and the manufacturing method of the substrate are described in detail below with reference to the accompanying drawings.

Scene one

Referring to fig. 1 and 2, an embodiment of the present application provides a substrate 100, where the substrate 100 may at least include: a fan-out structure 120, a set of fan-in structures 110, and a semi-cured layer 130, wherein the semi-cured layer 130 is disposed between the fan-in structures 110 and the fan-out structure 120. The fan-in structure 110 is internally provided with a fan-in via hole 1111, the fan-out structure 120 is internally provided with a fan-out via hole 1211 corresponding to the fan-in via hole 1111, and the semi-fixed layer 130 is internally provided with a sintering layer 131 corresponding to both the fan-in via hole 1111 and the fan-out via hole 1211; the fan-in via 1111 is in communication with the fan-out via 1211 through the sintered layer 131. The fan-in structure 110 and the fan-out structure 120 are stacked and connected through a sintering process, and the sintering layer 131 is connected with the fan-in via 1111 and the fan-out via 1211 through a sintering process, respectively.

It should be noted that, in the embodiment of the present application, the number of the fan-in structures 110 may be one, two, three or more, for example, in fig. 2, the number of the fan-in structures 110 is two, two groups of the fan-in structures 110 are spaced apart, and both groups of the fan-in structures 110 are sintered with the fan-out structure 120.

Thus, by providing multiple sets of fan-in structures 110, the fan-in density on the substrate 100 can be increased to accommodate the requirements of high speed transport systems. In addition, by providing multiple groups of fan-in structures 110, multiple electronic components (which may be chips) may be connected at the fan-in end, and compared to the FC-BGA substrate 100 in the prior art, which is used for packaging a single chip, the substrate 100 in the embodiment of the present application has the advantage of multi-scenario application.

The fan-in structure 110 and the fan-out structure 120 may be fixedly connected by laminating at least one set of the fan-in structure 110 and the fan-out structure 120 by a sintering process. In this way, compared with the prior art, the high-temperature welding process is omitted, so that the warping problem of the substrate 100 during welding can be eliminated, the problem that stress exists in welding spots due to the warping of the substrate 100 during welding by adopting solder balls (can be tin balls) between the substrate 100 and a circuit board in the prior art is avoided, and the risk of cracking of the welding spots between the substrate 100 and the circuit board is reduced.

In addition, the sintering process can enable a layer of compact structure to be formed between the fan-in structure 110 and the fan-out structure 120 of the substrate 100, so that the internal structure of the substrate is more compact, and the strength of the substrate 100 can be improved.

Therefore, the embodiment of the application can improve the strength of the substrate 100, thereby reducing the warpage of the substrate 100 and improving the overall reliability of the substrate 100. In addition, when the fan-in structure 110 and the fan-out structure 120 are connected through the sintering process, the strength of the substrate 100 is ensured due to the compact structure formed between the fan-in structure 110 and the fan-out structure 120, so that the overall thickness of the substrate 100 can be greatly reduced, the difficulty of opening holes in the fan-in structure 110 and the fan-out structure 120 is reduced, and thus, the fan-in of high density on the fan-in structure 110 can be realized and the fan-out density of the fan-out structure 120 can be improved.

The substrate 100 provided in the embodiment of the present application may further include: a first fan-in conductive layer 132 and a first fan-out conductive layer 133 in a patterned design. Wherein the first fan-in conductive layer 132 is disposed on a surface of the fan-in structure 110 facing the semi-fixed layer 130, and the first fan-in conductive layer 132 is electrically connected to the fan-in via 1111; the first fan-out conductive layer 133 is disposed on a surface of the fan-out structure 120 facing the semi-fixed layer 130, and the first fan-out conductive layer 133 is electrically connected to the fan-out via 1211; the sintering layer 131 is located between the first fan-in conductive layer 132 and the first fan-out conductive layer 133, and the sintering layer 131 is connected with the first fan-in conductive layer 132 and the first fan-out conductive layer 133 through sintering, respectively, to conduct the fan-in via 1111 and the fan-out via 1211.

The fan-in via 1111 and the fan-out via 1211 are conducted by providing the first fan-in conductive layer 132 and the first fan-out conductive layer 133, and sintering the sintered layer 131 with the first fan-in conductive layer 132 and the first fan-out conductive layer 133, respectively.

As shown in fig. 1 and 2, the fan-in structure 110 in the embodiment of the present application may at least include: a fan-in wiring layer 111, wherein a fan-in via 1111 is disposed in the fan-in wiring layer 111, a first fan-in conductive layer 132 is disposed on a surface of the fan-in wiring layer 111 near the semi-fixed layer 130, and the first fan-in conductive layer 132 is electrically connected to the fan-in via 1111; a second fan-in conductive layer 1112 is provided on a side of the fan-in wiring layer 111 remote from the semi-cured layer 130, and the second fan-in conductive layer 1112 is electrically connected to the fan-in via 1111.

As shown in fig. 1 and 2, the fan-in wiring layer 111 may include three fan-in dielectric layers 111a, but the number of the fan-in dielectric layers 111a may be one, two, four, etc., and the number is not limited. Each of the fan-in dielectric layers 111a may include: a fan-in dielectric layer 1113, a fan-in via 1111 disposed within the fan-in dielectric layer 1113, and a second fan-in conductive layer 1112 disposed on the dielectric layer. The fan-in dielectric layer 1113 is an insulating layer made of silicon oxide, polyimide or polypropylene.

Compared with the substrate 100 in the prior art, which adopts ABF resin as the dominant material, the substrate 100 in the embodiment of the application has smaller signal difference loss by arranging the fan-in dielectric layer 1113 as an insulating layer made of silicon oxide, polyimide or polypropylene, which is beneficial to improving the signal integrity (also called SI performance) of the substrate 100 and realizing high-density integration of the substrate 100. In addition, the insulating layer of silicon oxide, polyimide or polypropylene has better strength, which is advantageous in improving the strength of the substrate 100, thereby reducing warpage of the substrate 100.

Wherein, the interval L1 between two adjacent second fan-in conductive layers 1112 in the topmost fan-in dielectric layer 111a of the plurality of fan-in dielectric layers 111a may be 130um or less. Illustratively, the spacing between adjacent two second fan-in conductive layers 1112 in the topmost fan-in dielectric layer 111a is a suitable value of 120um, 110um, 100um, or 90 um. Additionally, in some embodiments, the spacing between two adjacent second fan-in conductive layers 1112 in the topmost fan-in dielectric layer 111a may also be greater than 130um, for example, for some cases where the substrate 100 does not require high density integration, the spacing between two adjacent second fan-in conductive layers 1112 in the topmost fan-in dielectric layer 111a may be greater than 130um, such as: 150um, 200um, etc.

It should be noted that, the numerical values and the numerical ranges related to the embodiments of the present application are approximate values, and may have a certain range of errors under the influence of the manufacturing process, and those errors may be considered to be negligible by those skilled in the art.

It should be appreciated that when the fan-in dielectric layer 111a is one layer, the fan-in dielectric layer 111a is both the fan-in wiring layer 111 and the fan-in structure 110.

In this way, by providing the multiple fan-in dielectric layers 111a, the fan-in density in the substrate 100 can be improved, in addition, by dividing the fan-in via holes 1111 into multiple fan-in dielectric layers 111a, the number of the fan-in via holes 1111 in a single fan-in dielectric layer 111a can be reduced, on one hand, the difficulty in setting the via holes can be reduced, on the other hand, high-density integration of the substrate 100 can be realized, because the smaller the distance between the two second fan-in conductive layers 1112 is, more superior modules (such as chips) can be connected to the substrate 100, thereby realizing high-density integration so as to adapt to the requirements of a high-speed transmission system. The fan-out structure 120 in the embodiment of the present application may at least include: a fan-out wiring layer 121, a fan-out via 1211 disposed in the fan-out wiring layer 121, a first fan-out conductive layer 133 disposed on a side of the fan-out wiring layer 121 adjacent to the semi-fixed layer 130, the first fan-out conductive layer 133 electrically connected to the fan-out via 1211; a second fan-out conductive layer 1222 is disposed on a side of the fan-out wiring layer 121 remote from the semi-fixed layer 130, and the second fan-out conductive layer 1222 is electrically connected to the fan-out via 1211. Wherein the fan-out wiring layer 121 is sinter-connected to the fan-in structure 110.

The fan-out wiring layer 121 may include three fan-out dielectric layers 121a, but the number of the fan-out dielectric layers 121a may be one, two, four, etc., and the number is not limited. Each fan-out dielectric layer 121a includes: a fan-out dielectric layer 1213, a fan-out via 1211 disposed within the fan-out dielectric layer 1213, and a second fan-out conductive layer 1222 disposed over the dielectric layer.

It should be appreciated that when the fan-out dielectric layer 121a is one layer, the fan-out dielectric layer 121a is both the fan-out wiring layer 121 and the fan-out structure 120.

By providing the multi-layered fan-out dielectric layer 121a, the density of fan-out in the substrate 100 can be increased, and in addition, by disposing the fan-out vias 1211 separately in the plurality of fan-out dielectric layers 121a, the number of fan-out vias 1211 in a single fan-out dielectric layer 121a can be reduced, on the one hand, the difficulty of punching can be reduced, and on the other hand, high density integration of the substrate 100 can be achieved; the strength of the fan-out structure 120 may also be increased, thereby increasing the strength of the substrate 100 to reduce warpage of the substrate 100; in addition, the substrate 100 may be electrically connected to the circuit board.

Note that, the first fan-in conductive layer 132 and the first fan-out conductive layer 133 are used to conduct the fan-in via 1111 and the fan-out via 1211, and the second fan-in conductive layer 1112 is used to conduct the fan-in via 1111 between the different fan-in dielectric layers 111a, or to conduct the fan-in via 1111 of the electronic component and the fan-in structure 110. The second fan-out conductive layer 1222 is used to conduct the fan-out vias 1211 between the different fan-out dielectric layers 121a or to conduct the fan-out vias 1211 of the circuit board and the fan-out structure 120.

As shown in fig. 3, in an embodiment of the present application, each set of fan-in structures 110 may further include: the fan-in carrier plate 112, the fan-in carrier plate 112 and the fan-in wiring layer 111 are stacked, a fan-in via hole 1111 is formed in the fan-in carrier plate 112, and the fan-in via hole 1111 in the fan-in carrier plate 112 is communicated with the fan-in via hole 1111 in the fan-in wiring layer 111; the fan-in carrier 112 is located between the fan-in wiring layer 111 and the fan-out structure 120, and a semi-fixed layer 130 is disposed between the fan-in carrier 112 and the fan-out structure 120, wherein a sintering layer is disposed in the semi-fixed layer 130, and the sintering layer 131 conducts the fan-in via 1111 and the fan-out via 1211. The first fan-in conductive layer 132 is disposed on a surface of the fan-in carrier 112 facing the semi-fixed layer 130, and the first fan-in conductive layer 132 is disposed on a surface of the fan-in wiring layer 111 facing away from the semi-fixed layer 130.

As shown in fig. 4, in the embodiment of the present application, a distance L2 between two adjacent fan-in vias 1121 in the fan-in carrier 112 is greater than or equal to 300um and less than or equal to 500um. Because too dense vias on the fan-in carrier plate 112 may reduce the strength of the fan-in carrier plate 112 and increase the punching difficulty, in the embodiment of the application, the distance between the vias on the fan-in carrier plate 112 is set to be 300um or more and 500um or less, so that the strength of the fan-in carrier plate 112 can be ensured, and the processing difficulty of the fan-in carrier plate 112 can be reduced.

It should be noted that, the fan-in carrier 112 may be disposed on a side of the fan-in structure 110 facing the semi-fixed layer 130 (shown in fig. 3), and in some embodiments, may also be disposed on a side of the fan-in structure 110 facing away from the semi-fixed layer 130, as shown in fig. 5, where the fan-in wiring layer 111 is located between the fan-in carrier 112 and the fan-out structure 120, and the fan-in wiring layer 111 is sintered and connected with the fan-out structure 120; the first fan-in conductive layer 132 is disposed on a surface of the fan-in wiring layer 111 facing the semi-fixed layer 130, and the second fan-in conductive layer 1112 is disposed on a surface of the fan-in carrier 112 facing away from the fan-in wiring layer 111. The distance L1 between two adjacent second fan-in conductive layers 1112 on the fan-in carrier 112 is less than or equal to 130um. By providing the fan-in carrier 112 on the side facing away from the semi-cured layer 130, i.e. the side to which the electronic components (e.g. chips) are connected, the connection of the electronic components (e.g. chips) is facilitated because the surface of the fan-in carrier 112 is relatively flat and the structure of the fan-in carrier 112 is relatively hard.

In addition, in the embodiment of the present application, the thermal expansion coefficient of the fan-in carrier plate 112 is less than 5ppm, and the elastic modulus of the fan-in carrier plate 112 is greater than or equal to 100Gpa.

The thermal expansion coefficient and the elastic modulus of the material may determine the strength of the material, and in general, the material having a low thermal expansion coefficient and a large elastic modulus has a high strength. In the embodiment of the application, the thermal expansion coefficient of the fan-in carrier plate 112 is smaller than 5ppm, and the elastic modulus is larger than or equal to 100Gpa, so that the strength of the fan-in carrier plate 112 is ensured to be larger, and the strength of the whole substrate 100 is correspondingly improved due to the larger strength of the fan-in carrier plate 112, so that the warping of the whole substrate 100 can be reduced, and the connection stability between the substrate 100 and a circuit board or an electronic component is ensured when the electronic component is used.

In an embodiment of the present application, the fan-in carrier plate 112 may be an inorganic plate made of an inorganic material. The inorganic board has a small thermal expansion coefficient and a large elastic modulus, and thus can satisfy the strength requirement of the fan-in carrier 112, so that the warpage problem of the substrate 100 can be reduced. In addition, the core board of the FC-BGA substrate 100 of the prior art is typically an organic board, and the inorganic board can be made thinner than the organic board, so that the thickness of the substrate 100 can be reduced while the strength of the substrate 100 is increased. And moreover, the inorganic carrier plate is compact in internal structure relative to the organic carrier plate, has higher strength and is not easy to deform, so that the warping problem can be improved, and the problem of supplying the large-size carrier plate is solved. Of course, in some embodiments, the fan-in carrier 112 may be an organic board, so long as the thermal expansion coefficient is less than 5ppm, and the elastic modulus is greater than or equal to 100Gpa, which is not limited in the embodiments of the present application.

In one possible implementation, the inorganic plate may be a glass plate or a ceramic plate. By setting the inorganic board as a glass plate or a ceramic plate, since the glass plate and the ceramic plate are relatively common and are inexpensive, the production cost of the first substrate 100 can be reduced, and in addition, the surfaces of the glass plate and the ceramic plate are smooth and easy to clean, so that the impurities on the surface of the fan-in carrier plate 112 can be reduced, the cleaning cost of the fan-in carrier plate 112 can be reduced in the process of producing the substrate 100, the production cost of the substrate 100 can be further saved, and the production efficiency can be improved. However, the material of the inorganic plate is not limited to the glass plate and the ceramic plate, and may be any other material. Of course, the inorganic board may be a board made of other materials, which is not limited in the embodiment of the present application.

As shown in fig. 6, in an embodiment of the present application, the fan-out structure 120 may further include: the fan-out carrier plate 122, the fan-out carrier plate 122 and the fan-out wiring layer 121 are stacked; and the number of the fan-out wiring layers 121 is two, and the fan-out carrier plate 122 is positioned between the two fan-out wiring layers 121; the fan-out carrier 122 is provided with a fan-out via 1221, and the fan-out via 1221 in the fan-out carrier 122 is conducted with the fan-out via 1211 in the fan-out wiring layer 121.

In addition, the fan-in structure 110 and the fan-out structure 120 are stacked, wherein in fig. 6, the fan-in structure 110 is the fan-in wiring layer 111, a semi-fixed layer 130 is arranged between the fan-in wiring layer 111 and one fan-out wiring layer 121, a sintering layer 131 is arranged in the semi-fixed layer 130, the sintering layer 131 conducts the fan-in via 1111 and the fan-out via 1211, and the fan-in wiring layer 111 and the fan-out wiring layer 121 are fixedly connected through sintering.

It should be noted that, in the embodiment of the present application, the fan-out carrier plate 122 may provide support for the fan-out wiring layer 121, so as to increase the strength of the fan-out structure 120, and thus facilitate fixing when the fan-out structure 120 and the fan-in structure 110 are connected together. And providing the fan-out carrier plate 122 may reduce the risk of breaking the fan-out structure 120. The strength of the entire substrate 100 can be enhanced by providing the fan-out carrier 122, so that warpage can be reduced. In addition, by providing the fanout via 1221 on the fanout carrier 122, the fanout via 1211 and the fanin via 1111 can be ensured to be conductive, thereby improving the signal integrity (also referred to as SI performance) of the substrate 100.

It should be noted that the fan-out structure 120 with the fan-out carrier 122 in fig. 6 may be connected to different forms of the fan-in structure 110, so as to form different structures of the substrate 100. In fig. 6, the fan-out structure 120 with the fan-out carrier 122 and the fan-in structure 110 with only the fan-in wiring layer 111 are connected to form the substrate 100, so that the substrate 100 has a carrier, the structural strength is high, and the warpage of the substrate 100 can be reduced; as shown in fig. 7, the fanout structure 120 with the fanout carrier 122 in fig. 6 and the fanin structure 110 with the fanin carrier 112 and the fanin wiring layer 111 are connected to form the substrate 100, and the fanin carrier 112 is close to the semi-fixed layer 130, so that the substrate 100 has two carriers, the structural strength is further increased, and the warpage of the substrate 100 can be further reduced; as shown in fig. 8, the fan-in carrier board 112 of the fan-in structure 110 in fig. 7 may also be disposed on a surface facing away from the semi-fixed layer 130, so that the fan-in carrier board 112 is located on the top layer of the substrate 100, and the fan-in carrier board 112 may be directly connected with an electronic component (such as a chip), which is convenient and fast.

In the embodiment where the fan-in structure 110 includes only the fan-in wiring layer 111, the fan-in wiring layer 111 may be deposited onto one of the fan-in carrier boards 112 when the fan-in structure 110 is manufactured, then after the fan-in wiring layer 111 is disposed, a surface of the fan-in wiring layer 111 facing away from the fan-in carrier board 112 is fixedly connected (sintered or welded) to the fan-out structure 120, and then the fan-in carrier board 112 is removed. Since the fan-in carrier plate 112 is supported when the fan-in structure 110 and the fan-out structure 120 are connected, the strength of the fan-in structure 110 is large, and thus no large warpage occurs regardless of whether the fixed connection is achieved by welding or sintering. Subsequent removal of the fan-in carrier 112 may also reduce the thickness of the substrate 100.

As shown in fig. 9, in an embodiment of the present application, the fan-out structure 120 may further include a plurality of discrete devices 140, and the plurality of discrete devices 140 are horizontally spaced apart within the fan-out structure 120. By providing a plurality of discrete devices 140 within the fan-out structure 120, the power integrity performance (PI performance) of the substrate 100 may be improved. The substrate 100 in the embodiment of the present application can achieve a surface copper thickness greater than or equal to 30um (i.e. equivalent to the conductivity of copper with a thickness of 30 um) to provide a large current supply channel.

It should be noted that the number and types of the discrete devices 140 do not limit the scope of the technical solution of the present application, in addition, in this embodiment, the discrete devices 140 are disposed in the fan-out structure 120, and in some embodiments, the discrete devices 140 may also be disposed in the fan-in structure 110, so long as the technical solution in which the discrete devices 140 are disposed belongs to the scope of the technical solution of the present application, and the specific disposition positions of the discrete devices 140 may be specifically set according to specific requirements, which is not described herein.

In one possible implementation, the discrete device 140 may be one or more of a capacitor or an inductor.

Scene two

As shown in fig. 10, an embodiment of the present application provides a substrate 200, where the substrate 200 may include: a fan-out structure 220 and a set of fan-in structures; each set of fan-in structures includes a fan-in carrier 230 and a fan-in wiring layer 210, the fan-in wiring layer 210 and the fan-in carrier 230 are stacked with the fan-out structure 220, and the fan-in carrier 230 is located between the fan-in wiring layer 210 and the fan-out structure 220. Wherein, the thermal expansion coefficient of the fan-in carrier plate 230 is less than 5ppm, and the elastic modulus of the fan-in carrier plate 230 is greater than or equal to 100Gpa. In the embodiment of the present application, the fan-in carrier plate 230 is disposed on the fan-in structure to provide support for the fan-in wiring layer 210, so as to increase the strength of the fan-in structure, and further reduce the risk of breakage of the fan-in structure; the strength of the entire substrate 200 can be enhanced by providing the fan-in carrier 230, so that warpage can be reduced. The thermal expansion coefficient and the elastic modulus of the material may determine the strength of the material, and in general, a material having a low thermal expansion coefficient and a large elastic modulus has a high strength.

In the embodiment of the present application, by setting the thermal expansion coefficient of the fan-in carrier 230 to be less than 5ppm and the elastic modulus to be greater than or equal to 100Gpa, the strength of the fan-in carrier 230 can be ensured to be greater, and since the strength of the fan-in carrier 230 is greater, the strength of the whole substrate 200 can be correspondingly improved, so that the warpage of the whole substrate 200 can be reduced, and the connection stability between the substrate 200 and the circuit board or the electronic component can be ensured when in use.

It should be noted that, in this embodiment, the number of fan-in structures may be one, two, three or more, and two adjacent fan-in structures may be disposed at intervals. For example, in fig. 11, the number of fan-in structures is two, and the two groups of fan-in structures are arranged at intervals. Thus, by providing multiple sets of fan-in structures, the fan-in density on the substrate 200 can be increased to accommodate the requirements of high speed transport systems. In addition, by setting a plurality of groups of fan-in structures, a plurality of electronic components (which may be chips) can be connected at the fan-in end, and compared with the FC-BGA substrate 200 in the prior art, which is used for packaging a single chip, the substrate 200 in the embodiment of the present application has the advantage of multi-scenario application.

As shown in fig. 10 and 11, a patterned upper conductive layer 232 is disposed on one side of the fan-in carrier 230; a patterned lower conductive layer 233 is arranged on the other surface of the fan-in carrier plate 230; a via hole 231 is arranged in the fan-in carrier 230, and the via hole 231 is used for conducting the upper conductive layer 232 and the lower conductive layer 233; fan-in via 2111 is formed in fan-in wiring layer 210, fan-out via 2211 is formed in fan-out structure 220, and fan-in via 2111 is connected to fan-out via 2211 through via 231, upper conductive layer 232, and lower conductive layer 233 in fan-in carrier 230. SI performance of the substrate 200 may be improved by turning on the fan-in via 2111 and the fan-out via 2211.

In the embodiment of the present application, the fan-in wiring layer 210 may include three fan-in dielectric layers 211, and of course, the number of the fan-in dielectric layers 211 may be one, two, four, etc., and the number is not limited. Each of the fan-in dielectric layers 211 includes: the fan-in dielectric layer 2113, the fan-in via 2111 provided within the fan-in dielectric layer 2113, and the fan-in conductive layer 2112 provided on the dielectric layer and electrically connected to the fan-in via 2111. The fan-in dielectric layer 2113 may be an insulating layer made of silicon oxide, polyimide, or polypropylene.

Compared with the substrate 200 in the prior art, which uses ABF resin as the dominant material, the substrate 200 in the embodiment of the application has smaller signal difference loss by setting the fan-in dielectric layer 2113 as an insulating layer made of silicon oxide, polyimide or polypropylene, which is beneficial to improving the signal integrity (also called SI performance) of the substrate 200 and realizing high density integration of the substrate 200. In addition, the insulating layer of silicon oxide, polyimide or polypropylene has better strength, which is advantageous in improving the strength of the substrate 200, thereby reducing warpage of the substrate 200.

As shown in fig. 10 and 11, the fan-out structure 220 may include: at least one fan-out routing layer 221, wherein the fan-out routing layer 221 may be connected to the fan-in carrier 230, i.e. the fan-in carrier 230 is located near a side of the fan-out structure 220 (as shown in fig. 10), or the fan-out routing layer 221 is connected to the fan-in routing layer 210, i.e. the fan-in carrier 230 is located at a side facing away from the fan-out structure 220, i.e. the fan-in carrier 230 is located at a top end of the substrate 200 (as shown in fig. 12).

Also, the fan-out wiring layer 221 may include three fan-out dielectric layers 211a, but the number of the fan-out dielectric layers 211a may be one, two, four, etc., and the number is not limited. Each fan-out dielectric layer 211a includes: the fan-out dielectric layer 2213, the fan-out via 2211 disposed within the fan-out dielectric layer 2213, and the fan-out conductive layer 2212 disposed on the fan-out dielectric layer 2213 and electrically connected to the fan-out via 2211. The fan-out dielectric layer 2213 may also be an insulating layer made of silicon oxide, polyimide or polypropylene, so that the signal integrity of the substrate 200 may be improved, and in some embodiments, the fan-out dielectric layer 2213 may also be an insulating layer made of other materials, and the material of the corresponding fan-out dielectric layer 2213 is not specifically limited herein.

When the fan-in carrier 230 is located between the fan-in wiring layer 210 and the fan-out structure 220, a spacing L3 between two adjacent fan-in conductive layers 2112 located in the topmost fan-in dielectric layer 2113 in the fan-in wiring layer 210 is 130um or less. In this way, by setting the interval between two adjacent fan-in conductive layers 2112 in the fan-in dielectric layer 2113 at the topmost end of the fan-in wiring layer 210 to be less than or equal to 130um, the fan-in density in the substrate 200 can be increased, which is beneficial to high-density integration of the substrate 200 so as to adapt to the requirement of a high-speed transmission system.

Note that, in the substrate 200 structures in fig. 10, 11 and 12, the fan-out structure 220 is the fan-out wiring layer 221.

As shown in fig. 13, the fan-out structure 220 may further include: a fan-out carrier 222, the fan-out carrier 222 being stacked with the fan-out wiring layer 221; and the number of the fan-out wiring layers 221 is two, and the fan-out carrier plate 222 is positioned between the two fan-out wiring layers 221; the fan-out carrier 222 is provided with a fan-out via 2221, and the fan-out via 2221 in the fan-out carrier 222 is conducted with the fan-out via 2211 in the fan-out wiring layer 221.

In this embodiment, the fan-out structure 220 and the fan-in structure are stacked, and the fan-in carrier 230 is fixedly connected to one of the fan-out wiring layers 221. However, in other embodiments, the fan-in routing layer 210 and one of the fan-out routing layers 221 may also be fixedly connected.

In one possible implementation, the fan-in carrier plate 230 may be an inorganic plate made of inorganic material. The inorganic board has a small thermal expansion coefficient and a large elastic modulus, and thus can meet the strength requirement of the fan-in carrier 230, thereby reducing the warpage problem of the substrate 200. In addition, the core board of the FC-BGA in the prior art is typically an organic board, and the inorganic board can be made thinner than the organic board, so that the thickness of the substrate 200 can be reduced while the strength of the substrate 200 is increased. And moreover, the inorganic carrier plate is compact in internal structure relative to the organic carrier plate, has higher strength and is not easy to deform, so that the warping problem can be improved, and the problem of supplying the large-size carrier plate is solved.

In one possible implementation, the inorganic plate may be a glass plate or a ceramic plate. By setting the inorganic board as a glass plate or a ceramic plate, since the glass plate and the ceramic plate are relatively common and are inexpensive, the production cost of the first substrate 200 can be reduced, and in addition, the surfaces of the glass plate and the ceramic plate are smooth and easy to clean, so that the impurities on the surface of the fan-in carrier plate 230 can be reduced, the cleaning cost of the fan-in carrier plate 230 can be reduced in the process of producing the substrate 200, the production cost of the substrate 200 can be further saved, and the production efficiency can be improved. However, the material of the inorganic plate is not limited to the glass plate and the ceramic plate, and may be any other material. Of course, the inorganic board may be a board made of other materials, which is not limited in the embodiment of the present application.

In the embodiment of the present application, the fan-in structure and the fan-out structure 220 may be fixedly connected by sintering, where, as shown in fig. 14, for the substrate 200 in which the fan-in carrier 230 is disposed near one side of the fan-out structure 220, a semi-fixed layer 260 may be disposed between the fan-in carrier 230 and one fan-out wiring layer 221, a sintering layer 261 is disposed in the semi-fixed layer 260, the sintering layer 261 conducts the fan-in via 2111 and the fan-out via 2211, the fan-in carrier 230 is fixedly connected by sintering with the fan-out wiring layer 221, and the via 231 in the fan-in carrier 230 and the fan-out via 2211 in the fan-out wiring layer 221 are conducted by the sintering layer 261.

As shown in fig. 15, for the substrate 200 in which the fan-in carrier 230 is disposed on a side facing away from the fan-out structure 220, a semi-fixed layer 260 is disposed between the fan-in wiring layer 210 and the fan-out wiring layer 221, a sintering layer 261 is disposed in the semi-fixed layer 260, the sintering layer 261 conducts the fan-in via 2111 and the fan-out via 2211, the fan-in wiring layer 210 and the fan-out wiring layer 221 are fixedly connected by sintering, and the fan-in via 2111 in the fan-in wiring layer 210 and the fan-out via 2211 in the fan-out wiring layer 221 are conducted by the sintering layer 261.

It should be noted that, fig. 14 and fig. 15 only illustrate two different substrate 200 structures for fixedly connecting the fan-in structure and the fan-out structure 220 by sintering, and the other substrate 200 structures for fixedly connecting the fan-in structure and the fan-out structure 220 by sintering may refer to the description of the substrate structures in fig. 14 and fig. 15, which are not illustrated here.

In the embodiment of the present application, the fan-in structure and the fan-out structure 220 may be fixedly connected by welding, where the fan-in carrier 230 is disposed on the substrate 200 near one side of the fan-out structure 220, that is, the fan-in carrier 230 is disposed between the fan-in wiring layer 210 and the fan-out structure 220; as shown in fig. 16, solder balls 250 are disposed between the fan-in carrier 230 and the fan-out wiring layer 221, and the via holes in the fan-in carrier 230 and the via holes in the fan-out wiring layer 221 are conducted through the corresponding solder balls 250. As shown in fig. 17 and 18, for the substrate 200 in which the fan-in carrier 230 is disposed on a side facing away from the fan-out structure 220, solder balls 250 are disposed between the fan-in wiring layer 210 and the fan-out wiring layer 221, and the fan-in via 2111 in the fan-in wiring layer 210 and the fan-out via 2211 in the fan-out wiring layer 221 are conducted through the solder balls 250.

It should be noted that, fig. 16, 17 and 18 only illustrate two different substrate 200 structures for fixedly connecting the fan-in structure and the fan-out structure 220 by welding, and reference may be made to the description of the substrate structures in fig. 16, 17 and 18 for other substrate 200 structures for fixedly connecting the fan-in structure and the fan-out structure 220 by welding, which are not illustrated here.

Note that, in the embodiment of the present application, the solder balls 250 may be solder balls, or may be solder balls 250 made of other materials, which is not particularly limited in the embodiment.

In addition, in the embodiment of the present application, the fan-out wiring layer 221 may also be formed by a semiconductor deposition method on one side of the fan-in carrier 230 (see fig. 10 and 11). Thus, the fan-out wiring layer 221 is directly formed on one surface of the fan-in carrier plate 230 in a semiconductor deposition manner, so that the fan-out carrier plate 222 can be saved, the process steps for fixedly connecting the fan-in structure and the fan-out structure 220 are reduced, the process flow is shortened, and the production cost is saved.

With continued reference to fig. 16, the fan-out structure 220 may also include a plurality of discrete devices 240, the plurality of discrete devices 240 being horizontally spaced apart within the fan-out structure 220. By providing a plurality of discrete devices 240 within the fan-out structure 220, the power integrity performance (PI performance) of the substrate 200 may be improved. The substrate 200 in the embodiment of the present application can achieve a surface copper thickness greater than or equal to 30um (i.e. equivalent to the conductivity of copper with a thickness of 30 um) to provide a large current supply channel.

It should be noted that the number and types of the discrete devices 240 do not limit the scope of the technical solution of the present application, in addition, in this embodiment, the discrete devices 240 are disposed in the fan-out structure 220, and in some embodiments, the discrete devices 240 may also be disposed in the fan-in structure, so long as the technical solution in which the discrete devices 240 are disposed belongs to the scope of the technical solution of the present application, and the specific disposition positions of the discrete devices 240 may be specifically set according to specific requirements, which is not described herein.

In one possible implementation, the discrete device 240 may be one or more of a capacitor or an inductor.

In one possible implementation, the fan-out carrier 222 is an inorganic board, or the fan-out carrier 222 is an organic board. When the fan-out carrier 222 is an inorganic board, the strength of the substrate 200 is greater, and thus warpage is smaller, and when the fan-out carrier 222 is an organic board, the strength of the substrate 200 with two carriers is greater and warpage is smaller than that of the FC-BGA substrate 200 with only one core board in the prior art.

According to the substrate 200 in the embodiment of the application, the strength of the substrate 200 can be enhanced by arranging the fan-in carrier plate 230, so that the warping of the substrate 200 is reduced; the fan-in carrier 230 is made of a material having a thermal expansion coefficient of less than 5ppm and an elastic modulus of greater than or equal to 100Gpa, so that the strength of the fan-in carrier 230 can be ensured and the thickness of the substrate 200 can be reduced; in addition, in the embodiment of the application, by arranging the fan-in carrier plate 230, in the process of increasing the layer of the fan-in structure, the density of the fan-in via holes 2111 is conveniently increased, so that the substrate 200 realizes high-density integration, the substrate 200 can be directly connected with electronic components (such as chips) without an adapter plate, and the application range of the substrate 200 is improved; in addition, the fan-in structure and the fan-out structure 220 in the substrate 200 in the embodiment of the present application may be used as an integrated structure, and may also be applied to a certain scene as an individual; the substrate 200 in the embodiment of the application can realize the surface copper thickness greater than or equal to 30um (namely, the conductivity equivalent to 30um thick copper) so as to provide a large-current power supply channel; the substrate 200 in the embodiment of the present application may be directly connected to an electronic component, and illustratively: and welding the chip and the resistor, the capacitor and the like.

Scene three

In an embodiment of the present application, as shown in fig. 19, the package structure 300 includes an electronic component 101 and a substrate 100 in one embodiment of a first scenario, where the electronic component 101 may be fixedly connected to a fan-in structure 110 of the substrate 100 by soldering with a solder ball 1011.

Referring to fig. 19 and 20, the package structure 300 may include at least an electronic component 101 and the substrate 100 in any of the foregoing embodiments, where the electronic component 101 is disposed on the fan-in structure 110 of the substrate 100 and is electrically connected to the fan-in structure 110, and the number of the electronic components 101 is at least one, specifically may be one, two or more, and is not limited.

As shown in fig. 20, in the embodiment of the present application, the package structure 300 includes an electronic component 201 and the substrate 200 in one embodiment of the second scenario, where the electronic component 201 may be fixedly connected to the fan-in structure of the substrate 200 by soldering with the solder balls 1011.

As shown in fig. 20, the package structure 300 may at least include an electronic component 201 and a substrate 200 in any of the foregoing embodiments, where the electronic component 201 is disposed on a fan-in structure of the substrate 200 and is electrically connected to the fan-in structure, and the number of the electronic components 201 is at least one, specifically, may be one, two or more, and is not limited.

It should be understood that, in the embodiment of the present application, the package structure 300 is actually that at least one electronic component 101 or electronic component 201 is disposed on the substrate 100 or the substrate 200 in the embodiment, and the specific structure of the package structure 300 is not listed in the embodiment because the substrate in the embodiment has a large number of structures.

It should be noted that, the electronic component 101 and the electronic component 201 may be one or more of a chip, a resistor, a capacitor, or an inductor, which is not limited in the embodiment of the present application. In addition, the number of electronic components may be one, two, three or more, which is not limited in the embodiment of the present application.

The package structure 300 according to the embodiment of the present application, by providing the substrate in the above embodiment, can improve the strength of the entire package structure 300 and can reduce the warpage of the substrate. And by providing at least one electronic component (which may be a chip), the package structure 300 in the embodiment of the present application has advantages of multi-scenario application, compared to the FC-BGA substrate of the prior art, which is used for single chip package. In addition, since the substrate has a high fan-in density, it can be directly connected to the electronic component without an interposer, and thus the package structure 300 can be assembled more conveniently.

Scene four

An embodiment of the present application provides a board-level architecture 1000, as shown in fig. 21, where the board-level architecture 1000 may at least include a circuit board, an electronic component, and a substrate in any of the foregoing embodiments, where the substrate is located between the circuit board and the electronic component, and the electronic component is connected to a fan-in structure in the substrate, and the circuit board is connected to the fan-out structure in the substrate.

As shown in fig. 21, the fan-in structure 110 and the fan-out structure 120 in the substrate 100 are fixedly connected by sintering, the fan-in structures 110 in the substrate 100 are a group, and one electronic component 101 is disposed on the fan-in structure 110 of the substrate 100; a solder ball 1011 is provided between the electronic component 101 and the substrate 100, so that the electronic component 101 and the substrate 100 are connected by solder connection of the solder ball 1011; solder balls 1021 are also provided between the substrate 100 and the circuit board 102 so that the substrate 100 and the circuit board 102 are connected by solder ball 1021.

As shown in fig. 22, the fan-in structure and the fan-out structure 220 in the substrate 200 are fixedly connected by means of solder balls 250, a plurality of discrete devices 240 are arranged in the fan-out structure 220, the fan-in structures in the substrate 200 are in a group, and one electronic component 201 is arranged on the fan-in structure of the substrate 200; a solder ball 1011 is arranged between the electronic component 201 and the substrate 200, so that the electronic component 201 and the substrate 200 are connected by solder connection of the solder ball 1011; solder balls 2011 are disposed between the substrate 200 and the circuit board 202, so that the substrate 200 and the circuit board 202 are connected by solder ball 2011.

In the present embodiment, the number of electronic components 101 is one. Of course, in other embodiments, as shown in fig. 23, the fan-in structures 110 in the substrate 100 are in a group, two electronic components 101 are arranged on the fan-in structures 110 at intervals, and a power supply 103 is further arranged on the substrate 100, wherein the power supply 103 is arranged on the fan-in structures 110, and the power supply 103 is electrically connected with the fan-in structures 110, wherein the power supply 103 can be used for supplying power to the substrate 100. In addition, the electronic component 101 and the substrate 100 in the present embodiment are directly soldered via solder balls 1011, and the substrate 100 and the circuit board 102 are connected via solder balls 1021.

It should be noted that, the electronic components 101 on the substrate 100 include, but are not limited to, two, but of course, three, four or more electronic components 101 may be disposed on the fan-in structure 110 at intervals, and the number of the electronic components 101 is not limited in the embodiment of the present application. In addition, the power supply 103 may be disposed on the fan-in structure 110 or on the fan-out structure 120, and the position of the power supply 103 is not limited in the embodiment of the present application. In addition, by providing a plurality of electronic components 101 in this way, the multi-scene adaptation capability of the board-level architecture 1000 can be improved.

As shown in fig. 24, in the embodiment of the present application, two sets of fan-in structures 110 are provided in the substrate 100, two electronic components 101 are provided, a plurality of discrete devices 140 are provided in the fan-out structure 120, and one electronic component 101 is provided on each set of fan-in structures 110.

It should be noted that, in the present embodiment, the number of the fan-in structures 110 is two, and in some embodiments, the number of the fan-in structures 110 may be three, four or more, and the number of the fan-in structures 110 is not limited in the embodiment of the present application. In this embodiment, the number of the electronic components 101 is two, and in some embodiments, the number of the electronic components 101 may be three, four or more, which is not limited in this embodiment. One electronic component 101 may be disposed on each set of fan-in structures 110, or two, three, or more electronic components 101 may be disposed, which is not limited in this embodiment of the present application. In addition, the same number of electronic components 101 may be disposed on different fan-in structures 110, and different numbers of electronic components 101 may be disposed, which is not limited in the embodiment of the present application.

By providing multiple sets of fan-in structures 110, fabrication of a large-sized board level architecture 1000 may be achieved. In addition, the provision of multiple sets of fan-in structures 110 may increase the fan-in density of the board level architecture 1000, thereby facilitating high-speed transmission of the board level architecture 1000 to accommodate high-density circuit applications.

In the board-level architecture 1000 in the embodiment of the present application, the fan-in structure 110 of the substrate 100 and the electronic component 101 may be fixedly connected by welding; the fan-out structures 120 of the substrate 100 and the circuit board 102 may be connected by soldering or by a sintering process.

In the process of manufacturing the board level structure 1000, as shown in fig. 21, 22 and 23, the substrate 100 may be manufactured first, and then the electronic component 101 and the circuit board 102 may be soldered onto the fan-in structure 110 and the fan-out structure 120 by solder balls 1021, respectively.

Or as shown in fig. 25A and 25B, the electronic component 101 may be first connected to the fan-in structure 110, so that the fan-in structure 110 and the electronic component 101 form a whole; the fan-out structure 120 is connected to the circuit board 102 by a sintering process such that the fan-out structure 120 and the circuit board 102 form a single body. The fan-in structure 110 with the electronic component 101 and the fan-out structure 120 with the circuit board 102 are then connected by a sintering process. In this embodiment, the fan-in structures 110 are divided into two groups, and each group of fan-in structures 110 is provided with one electronic component 101, and the fan-out structure 120 is provided with a plurality of discrete devices 140.

It should be noted that in some embodiments, different fan-in structures 110 with electronic components 101 and different fan-in structures 110 with circuit boards 102 may be connected, so as to obtain different board level architectures 1000, so as to adapt to different application scenarios.

Alternatively, as shown in fig. 26A and 26B, the fan-out structure 120 of the substrate 100 and the circuit board 102 may be connected by a sintering process, and then the electronic component 101 may be connected to the fan-in structure 110 of the substrate 100. In an embodiment of the present application, a plurality of discrete devices 140 are disposed in the fan-out structure 120 of the substrate 100.

Or as shown in fig. 27A and 27B, the board level structure 1000 includes two sets of fan-in structures 110 and one fan-out structure 120, and each fan-in structure 110 is provided with one electronic component 101, and when the board level structure 1000 is assembled, the substrate 100 and the electronic component 101 may be first connected into a whole, and then fixedly connected with the circuit board 102 by welding with the solder balls 1021.

Or as shown in fig. 28A and 28B, the board level structure 1000 includes two sets of fan-in structures (the fan-in structures include a fan-in wiring layer 210 and a fan-in carrier plate 230) and one fan-out structure 220, and one electronic component 201 is disposed on each fan-in structure, when the board level structure 1000 is assembled, the circuit board 202 and the fan-out structure 220 may be fixedly connected by welding with a solder ball 2021, and the fan-in structure and the electronic component 201 are connected, then a part of the fan-in structure with the electronic component 201 and the fan-out structure 220 with the circuit board 202 are connected by welding with a solder ball 250, and a part of the fan-in structure with the electronic component 201 and the fan-out structure 220 with the circuit board 202 are fixedly connected by sintering.

It should be noted that, the connection manner between the fan-in structure and the fan-out structure in the board level architecture may be the same or different, which is not specifically limited in the embodiment of the present application.

In addition, there are many combination types for the board-level architecture in the embodiment of the present application, which will not be described in detail herein.

The board-level framework in the embodiment of the application can improve the strength of the whole board-level framework by arranging the substrate in the embodiment, and the connection stability between the substrate and the circuit board is higher because the substrate has small warpage.

Scene five

On the basis of the above embodiment, referring to fig. 29, an embodiment of the present application further provides a method for manufacturing a substrate, where the method for manufacturing a substrate at least may include:

S101: providing a fan-out structure and at least one set of fan-in structures, each set of fan-in structures comprising a carrier plate and a fan-in wiring layer formed on the carrier plate;

s102: the fan-out structure is connected with the fan-in structure in a stacked manner, and the fan-in wiring layer is positioned between the carrier plate and the fan-out structure;

s103: and removing the carrier plate to form the substrate.

The following describes an example of a method for manufacturing one substrate in the first scenario.

Specifically, as shown in fig. 30, in the embodiment of the present application, the manufacturing process flow of the fan-in structure in step S101 at least includes: step S1011: providing a fan-in carrier plate 112, and arranging a protective film 150 on one surface of the fan-in carrier plate 112, and arranging a patterned fan-in conducting layer 1115 (shown in fig. 31) on the other surface of the fan-in carrier plate 112;

s1012: adding layers on the other side of the fan-in carrier plate 112;

s1013: step S1012 is repeated until the number of layers is increased to the desired level (fig. 35 shows a fan-in structure obtained by adding layers three times).

Wherein, S1012: the process flow of adding layers on the other side of the fan-in carrier 112 at least includes:

S1012a: coating liquid photosensitive build-up material or pressing photosensitive build-up material on the other surface of the fan-in carrier 112, baking, exposing, developing, and leaking out the place needing the fan-in via 1111, thus forming an insulating medium layer (i.e. the fan-in medium layer 1113) of the fan-in structure, and obtaining the structure shown in fig. 32;

S1012b: a seed layer is manufactured in the fan-in via hole 1111 and on the insulating medium layer by adopting a method of sputtering metals such as Ti/Cu or electroless copper plating, and the thickness of the seed layer is about 5-10um; then filling the fan-in via 1111 by a hole filling electroplating method, and forming an electroplated metal layer 1114 on the surface of the insulating dielectric layer to obtain a structure shown in fig. 33;

S1012c: a liquid photosensitive resist layer is coated on the metal layer, or the photosensitive resist layer is attached, and then the photosensitive resist layer is sequentially exposed, developed, etched and removed, and finally a patterned fan-in conductive layer 1115 (shown in fig. 34) is formed. It should be noted that after step S1012b, different layers may be connected; each layer is added, namely one layer of fan-in dielectric layer is added; the area covered by the photoresist layer is not corroded, that is, the area covered by the photoresist layer is the area where the fan-in via is finally formed.

In addition, it should be noted that the fanin conductive layer 1115 may be a first fanin conductive layer, a second fanin conductive layer in the first scenario, or an upper conductive layer, a lower conductive layer, and a fanin conductive layer in the second scenario. The metal layer 1114 in step S1012b may be made of copper, or other metal materials.

As shown in fig. 36, in the embodiment of the present application, the manufacturing process flow of the fan-out structure in step S101 at least includes:

S1014: providing a fan-out carrier plate 122 (which may be an organic plate or an inorganic plate), forming an X-type fan-out via hole 1221 on the fan-out carrier plate 122 by laser drilling, then manufacturing a seed layer in the X-type (other shapes are also possible) fan-out via hole 1221 and on both sides of the fan-out carrier plate 122 by a chemical copper deposition method, filling the X-type fan-out via hole 1221 by a hole filling electroplating method, forming a electroplated metal layer on both sides of the fan-out carrier plate 122 respectively, and finally forming a structure as shown in fig. 37 by processes such as film pasting, exposure, development, etching and the like;

S1015: adding layers to the fan-out carrier 122;

S1016: repeating step S1015, two layers may be added each time step S1015 is repeated, until the number of layers is increased to a desired level (e.g., a structure with three layers added on both sides as shown in fig. 39).

Specifically, in step S1015, when the fan-out carrier 122 is added, the layers may be added synchronously. Firstly, insulating dielectric layers (namely fan-out dielectric layers 1213) are respectively arranged on two sides of the fan-out carrier plate 122, and then fan-out vias 1211 are formed on the insulating dielectric layers (namely the fan-out dielectric layers 1213) through laser drilling; secondly, filling metal in the fanout via 1211 by electroless copper plating and electroplating via filling, and forming a metal layer on the surface of the insulating dielectric layer (namely the fanout dielectric layer 1213); finally, a photosensitive resist layer is disposed on the surface of the metal layer, then the photosensitive resist layer is exposed, developed, etched, and removed, and finally a patterned fan-out conductive layer 1116 is formed on the insulating dielectric layer (i.e., the fan-out dielectric layer 1213), so that a build-up (build-up of the fan-out dielectric layer and build-up of the patterned fan-out conductive layer, as shown in fig. 38) is completed. In an embodiment of the present application, the step of stacking the fan-out structure and the fan-in structure in step S102 may include the following steps:

S1021, providing a fan-in structure and a fan-out structure, then arranging a semi-fixed layer and a protective film 150 on one surface of the fan-out structure, and then arranging a through hole 160 communicated with a fan-out via hole on the semi-fixed layer and the protective film to obtain a structure shown in FIG. 40;

S1022, printing a conductive medium in the through holes by adopting a screen printing or steel screen printing mode and the like, then pre-baking, evaporating a solvent so that a sintered layer 131 can be formed in the through holes, and then removing the protective film 150 to form a structure shown in FIG. 41;

S1023, arranging one surface of the fan-in structure, which is opposite to the fan-in carrier plate, and the semi-fixed layer by layer, and fixedly connecting the fan-in structure and the fan-out structure in a sintering mode to obtain a structure shown in fig. 42; the through holes on the semi-fixed layer can conduct the fan-in through holes and the fan-out through holes.

In the embodiment of the present application, by the above-mentioned method for manufacturing the substrate, the distance L1 (see fig. 35) between the fan-in conductive layers at the top end of the fan-in structure may be less than or equal to 130um, which may be more than or equal to 130um in some embodiments; the spacing L3 (see fig. 39) between the two fan-out conductive layers at the bottom end of the fan-out structure is between 650-1000um, although it may be in a range other than 650-1000um in some embodiments; the spacing between fan-out vias on the fan-out carrier (as shown in fig. 37) L4 may be between 300-500mm, although it may be in a range other than 300-500mm in some embodiments.

In the embodiment of the present application, the specific operation method for preparing the fan-in structure and the fan-out structure in each step is not specifically limited, and in some embodiments, the fan-in structure and the fan-out structure in the embodiment of the present application may also be obtained by other methods, which are not described here.

It should be noted that the method for manufacturing the substrate in the embodiment of the present application is applicable to the substrates in the first and second scenes.

A sixth point of view of the scene is shown,

On the basis of the above embodiment, referring to fig. 43, an embodiment of the present application further provides a method for manufacturing a substrate, where the method for manufacturing a substrate at least may include:

S201: providing a fan-out structure and at least one group of fan-in structures, wherein each group of fan-in structures comprises a fan-in carrier plate and a fan-in wiring layer arranged on the fan-in carrier plate;

s202: a patterned semi-cured layer is arranged on one surface of the fan-out structure, and a sintering layer is arranged in the semi-cured layer;

S203: and pressing and sintering at least one group of fan-in structures and the fan-out structure provided with the semi-solidified layer and the sintering layer, wherein the semi-solidified layer and the sintering layer are positioned between the fan-in carrier plate and the fan-out structure so as to enable the fan-in carrier plate to be sintered and connected with the fan-out structure, and fan-in through holes in the fan-in structure are communicated with fan-out through holes in the fan-out structure through the sintering layer.

The following describes an example of a method for producing one substrate in the second scenario.

Specifically, in the embodiment of the present application, as shown in fig. 44, the manufacturing process flow of the fan-in structure in step S201 at least includes:

Step S2011: providing a fan-in carrier plate 230, arranging a protective film 270 on one surface of the fan-in carrier plate 230, arranging through holes 231 at intervals in the fan-in carrier plate 230, wherein the through holes 231 can be provided with conductive materials, and a patterned fan-in conductive layer 2115 is arranged on the other surface of the fan-in carrier plate 230 (as shown in fig. 45);

s2012: adding layers on the other side of the fan-in carrier plate 230;

S2013: step S2012 is repeated until the number of layers is increased to the desired level (fig. 49 shows a fan-in structure obtained by adding layers three times).

Wherein, S2012: the process flow of adding layers on the other side of the fan-in carrier 230 at least includes:

S2012a: coating liquid photosensitive build-up material or pressing photosensitive build-up material on the other surface of the fan-in carrier 230, baking, exposing, developing, and leaking out the place needing the fan-in via hole 2111, thus forming a layer of insulating medium layer (i.e. the fan-in medium layer 2113) of the fan-in structure, and obtaining the structure shown in fig. 46;

S2012b: a seed layer is manufactured in the fan-in via hole 2111 and on the insulating medium layer by adopting a method of sputtering metals such as Ti/Cu or electroless copper plating, and the thickness of the seed layer is about 5-10um; then, the fan-in via hole 2111 is filled up by a via filling plating method, and a plated metal layer 2114 is formed on the surface of the insulating dielectric layer, resulting in the structure shown in fig. 47.

In addition, the fanin conductive layer 2115 may be a first fanin conductive layer, a second fanin conductive layer in the first scenario, or an upper conductive layer, a lower conductive layer, a fanin conductive layer in the second scenario. The material of the metal layer 2114 in step S2012b includes, but is not limited to, copper, but may be other metal materials.

S2012c: a liquid photosensitive resist layer is coated on the metal layer, or the photosensitive resist layer is attached, and then the photosensitive resist layer is sequentially exposed, developed, etched and removed, and finally a patterned fan-in conductive layer 2115 is formed (as shown in fig. 48). It should be noted that, after step S2012b, different layers may be conducted; each layer is added, namely one layer of fan-in dielectric layer is added; the area covered by the photoresist layer is not corroded, that is, the area covered by the photoresist layer is the area where the fan-in via is finally formed.

In the embodiment of the present application, the manufacturing process flow of the fan-out structure in the step S201 may be the same as that in the fifth scenario, and specifically, reference may be made to the descriptions in the steps S1014, S1015 and S1016 in the fifth scenario, which are not repeated here.

It should be noted that, in some embodiments, the fan-out structure may be obtained by reversely layering the fan-in structure, specifically, after step S2013, the protective film of the obtained fan-in structure is removed, then step S2012 is repeated on a surface where the protective film is removed, and the fan-out structure may be obtained after layering several times.

The specific operation steps of step S202 may be referred to as S1021 and S1022 in scenario five, which are not described herein.

In step S203, before the at least one set of fan-in structures and the fan-out structure formed with the semi-cured layer and the sintered layer are pressed and sintered, the protective film on the fan-in structures may be removed.

In the embodiment of the application, by the method for manufacturing the substrate, the distance L2 between adjacent fan-in through holes on the fan-in carrier plate (as shown in fig. 45) can be 300-500mm, and can be in a range outside 300-500mm in some embodiments; the spacing L1 (see fig. 49) between the topmost fan-in conductive layers of the fan-in structure is less than or equal to 130um, although it is also possible in some embodiments to be greater than or equal to 130um; the spacing L3 (see fig. 39) between the two fan-out conductive layers at the bottom end of the fan-out structure is between 650-1000um, although it may be in a range other than 650-1000um in some embodiments; the spacing L4 between fan-out vias on the fan-out carrier (as shown in fig. 37) may be between 300-500mm, although it may be in a range other than 300-500mm in some embodiments. And a larger size substrate can be obtained.

Scene seven

On the basis of the above embodiment, referring to fig. 50, an embodiment of the present application further provides a method for manufacturing a substrate, where the method for manufacturing a substrate at least may include:

s301: providing a fan-out structure and at least one group of fan-in structures, wherein each group of fan-in structures comprises a fan-in carrier plate and a fan-in wiring layer arranged on the fan-in carrier plate;

S302: a patterned semi-cured layer is arranged on one surface of the fan-out structure, and a sintering layer is arranged in the semi-cured layer;

S303: at least one group of fan-in structures and the fan-out structures formed with the semi-solidified layers and the sintering layers are pressed and sintered, the semi-solidified layers and the sintering layers are positioned between the fan-in wiring layers and the fan-out structures, so that the fan-in wiring layers are connected with the fan-out structures in a sintering manner, and fan-in through holes in the fan-in structures are communicated with fan-out through holes in the fan-out structures through the sintering layers.

In the embodiment of the present application, the manufacturing process flow of the fan-in structure and the fan-out structure is the same as that in the sixth scenario, so the manufacturing process flow of the fan-in structure and the fan-out structure may refer to the description in the sixth scenario, and will not be described herein.

In describing embodiments of the present application, it should be noted that, unless explicitly stated or limited otherwise, the terms "mounted," "connected," and "coupled" should be construed broadly, and may be, for example, fixedly coupled, indirectly coupled through an intermediary, in communication between two elements, or in an interaction relationship between two elements. The specific meaning of the above terms in the embodiments of the present application will be understood by those of ordinary skill in the art according to specific circumstances.

The embodiments of the application may be implemented or realized in any number of ways, including as a matter of course, such that the apparatus or elements recited in the claims are not necessarily oriented or configured to operate in any particular manner. In the description of the embodiments of the present application, the meaning of "a plurality" is two or more unless specifically stated otherwise.

The terms first, second, third, fourth and the like in the description and in the claims and in the above-described figures, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that embodiments of the application described herein may be implemented, for example, in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "may include" and "have," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed or inherent to such process, method, article, or apparatus.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the embodiments of the present application, and are not limited thereto. Although embodiments of the present application have been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments may be modified or some or all of the technical features may be replaced with equivalents. Such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A substrate, comprising: the fan-in structure comprises a fan-out structure and at least one group of fan-in structures, wherein each group of fan-in structures is internally provided with a fan-in via hole, the fan-out structure is internally provided with a fan-out via hole corresponding to the fan-in via hole, and the fan-in via hole is communicated with the fan-out via hole;

each group of fan-in structures and each group of fan-out structures are connected in a stacked manner through a sintering process;

A semi-fixed layer is arranged between each group of fan-in structures and each fan-out structure, and a sintered layer corresponding to each fan-in via hole and each fan-out via hole is arranged in the semi-fixed layer;

the sintering layer is respectively connected with the fan-in via hole and the fan-out via hole through a sintering process, and the fan-in via hole is communicated with the fan-out via hole through the sintering layer.

2. The substrate of claim 1, wherein the substrate comprises a plurality of substrates,

A first fan-in conducting layer which is in graphical design is arranged on one surface of the fan-in structure facing the semi-fixed layer, and the first fan-in conducting layer is electrically connected with the fan-in via hole;

A first fan-out conducting layer which is in graphical design is arranged on one surface of the fan-out structure facing the semi-fixed layer, and the first fan-out conducting layer is electrically connected with the fan-out via hole;

The sintering layer is located between the first fan-in conducting layer and the first fan-out conducting layer, and is connected with the first fan-in conducting layer and the first fan-out conducting layer through sintering respectively so as to conduct the fan-in via holes and the fan-out via holes.

3. The base plate of any of claims 1-2, wherein each set of fan-in structures comprises: the fan-in wiring layer is internally provided with the fan-in via hole and a second fan-in conductive layer electrically connected with the fan-in via hole.

4. The substrate of claim 3, wherein said fan-in wiring layer comprises at least one fan-in dielectric layer, each of said fan-in dielectric layers comprising a fan-in dielectric layer, said fan-in via disposed within said fan-in dielectric layer, and said second fan-in conductive layer disposed on said dielectric layer.

5. The substrate of claim 4, wherein the fan-in dielectric layer is a plurality of layers, and a spacing between adjacent two of the second fan-in conductive layers in a topmost one of the plurality of layers of fan-in dielectric layers is 130 um or less.

6. The substrate of claim 4 or 5, wherein the fan-in dielectric layer is an insulating layer made of silicon oxide, polyimide, or polypropylene.

7. A base plate according to claim 3, wherein each set of fan-in structures further comprises: the fan-in carrier plate is arranged in a lamination mode with the fan-in wiring layer, the fan-in through holes are formed in the fan-in carrier plate, and the fan-in through holes in the fan-in carrier plate are communicated with the fan-in through holes in the fan-in wiring layer.

8. The substrate of claim 7, wherein the fan-in carrier is positioned between the fan-in routing layer and the fan-out structure, and wherein the fan-in carrier and the fan-out structure are connected by a sintering process.

9. The substrate of claim 8, wherein a spacing between two adjacent fan-in vias in the fan-in carrier is 300 um or more and 500 um or less.

10. The substrate of claim 7, wherein the fan-in routing layer is located between the fan-in carrier and the fan-out structure, the fan-in routing layer being sinter-bonded to the fan-out structure;

and the second fan-in conducting layer is arranged on one surface of the fan-in carrier plate, which is opposite to the fan-in wiring layer.

11. The substrate of claim 10, wherein a pitch of two adjacent second fan-in conductive layers on the fan-in carrier is 130 or less um.

12. The substrate of any one of claims 7-11, wherein the fan-in carrier has a coefficient of thermal expansion of less than 5ppm and a modulus of elasticity of greater than or equal to 100Gpa.

13. The base plate of claim 12, wherein the fan-in carrier plate is an inorganic plate made of an inorganic material.

14. The substrate of claim 13, wherein the inorganic plate is a glass plate or a ceramic plate.

15. The substrate of any one of claims 1-2, 4-5, 7-11, 13-14, wherein the fan-in structures are in a plurality of groups and wherein the plurality of groups of fan-in structures are spaced apart and juxtaposed on the fan-out structure.

16. The substrate of any one of claims 1-2, 4-5, 7-11, 13-14, wherein the fan-out structure comprises at least: at least one fan-out wiring layer, wherein each fan-out wiring layer is internally provided with a fan-out via hole and a second fan-out conductive layer electrically connected with the fan-out via hole;

the fan-out wiring layer is sintered and connected with the fan-in structure.

17. The substrate of claim 16, wherein the fan-out structure further comprises: the fan-out carrier plate and the fan-out wiring layer are arranged in a stacked mode;

The number of the fan-out wiring layers is two, and the fan-out carrier plate is positioned between the two fan-out wiring layers;

The fan-out carrier plate is internally provided with the fan-out via hole, and the fan-out via hole in the fan-out carrier plate is communicated with the fan-out via hole in the fan-out wiring layer.

18. The substrate of claim 17, wherein each of the fan-out routing layers includes at least one fan-out dielectric layer, each of the fan-out dielectric layers including a fan-out dielectric layer, the fan-out via disposed within the fan-out dielectric layer, and the second fan-out conductive layer disposed on the fan-out dielectric layer and electrically connected to the fan-out via.

19. The substrate of claim 18, wherein each of the fan-out routing layers comprises a plurality of the fan-out dielectric layers, the plurality of fan-out dielectric layers being stacked.

20. The substrate of any one of claims 1-2, 4-5, 7-11, 13-14, 17-19, wherein a plurality of discrete devices are disposed within the fan-out structure, the plurality of discrete devices being horizontally spaced within the fan-out structure.

21. The substrate of claim 20, wherein the discrete device is a capacitor or an inductor.

22. A substrate, comprising: a fan-out structure and at least one set of fan-in structures;

Each group of the fan-in structures comprises a fan-in wiring layer and a fan-in wiring layer, the fan-in wiring layer and the fan-in carrier plate are both arranged in a lamination manner with the fan-out structure, and the fan-in carrier plate is positioned between the fan-in wiring layer and the fan-out structure or the fan-in wiring layer is positioned between the fan-in carrier plate and the fan-out structure; the thermal expansion coefficient of the fan-in carrier plate is smaller than 5ppm, and the elastic modulus of the fan-in carrier plate is larger than or equal to 100Gpa;

the fan-out structure includes: at least one fan-out routing layer;

When the fan-in carrier plate is positioned between the fan-in wiring layer and the fan-out structure, a semi-fixed layer is arranged between the fan-in carrier plate and the fan-out wiring layer, and a sintering layer corresponding to the through holes in the fan-in carrier plate and the through holes in the fan-out wiring layer is arranged in the semi-fixed layer;

The sintering layer is respectively connected with the through holes in the fan-in carrier plate and the through holes in the fan-out wiring layer through a sintering process, and the through holes in the fan-in carrier plate are communicated with the through holes in the fan-out wiring layer through the sintering layer;

or solder balls are arranged between the fan-in carrier plate and the fan-out wiring layer, and the through holes in the fan-in carrier plate and the through holes in the fan-out wiring layer are communicated through the corresponding solder balls.

23. The substrate of claim 22, wherein said fan-in carrier is an inorganic plate made of an inorganic material.

24. The substrate of claim 23, wherein the inorganic plate is a glass plate or a ceramic plate.

25. The substrate of any one of claims 22-24, wherein the fan-out routing layer is connected to the fan-in carrier plate or the fan-out routing layer is connected to the fan-in routing layer.

26. The substrate of claim 25, wherein the fan-out routing layer is connected to the fan-in carrier or to the fan-in routing layer by a sintering process;

or the fan-out wiring layer is connected with the fan-in carrier plate or the fan-in wiring layer through a welding process;

or one surface of the fan-in carrier plate forms the fan-out wiring layer in a semiconductor deposition mode.

27. The substrate of claim 25, wherein the fan-out structure further comprises: the fan-out wiring layers are respectively arranged on two sides of the fan-out carrier plate in a stacked mode;

One fan-out wiring layer is connected with the fan-in carrier plate or the fan-in wiring layer, and the two fan-out wiring layers are conducted through holes arranged on the fan-out carrier plate.

28. The substrate of any one of claims 22-24, 26-27, wherein a patterned upper conductive layer is provided on one side of the fan-in carrier;

a patterned lower conductive layer is arranged on the other surface of the fan-in carrier plate;

A via hole is arranged in the fan-in carrier plate and is used for conducting the upper conductive layer and the lower conductive layer;

and fan-in through holes are formed in the fan-in wiring layer, fan-out through holes are formed in the fan-out structure, and the fan-in through holes are communicated with the fan-out through holes in the fan-in carrier plate, the upper conducting layer and the lower conducting layer.

29. The substrate of claim 28, wherein the fan-in wiring layer comprises at least one fan-in dielectric layer, each of the fan-in dielectric layers comprising a fan-in dielectric layer, the fan-in via disposed within the fan-in dielectric layer, and a fan-in conductive layer disposed on the dielectric layer and electrically connected to the fan-in via.

30. The substrate of claim 29, wherein each fan-out routing layer in the fan-out structure comprises at least one fan-out dielectric layer, each of the fan-out dielectric layers comprising a fan-out dielectric layer, the fan-out via disposed within the fan-out dielectric layer, and a fan-out conductive layer disposed on the fan-out dielectric layer and electrically connected to the fan-out via.

31. The substrate of claim 29 or 30, wherein when the fan-in carrier is located between the fan-in wiring layer and the fan-out structure, a spacing between two adjacent fan-in conductive layers in the topmost of the fan-in dielectric layers in the fan-in wiring layer is 130um or less.

32. The substrate of claim 29 or 30, wherein the fan-in dielectric layer in the fan-in wiring layer and the fan-out dielectric layer in the fan-out wiring layer are both insulating layers made of silicon oxide, polyimide, or polypropylene.

33. The substrate of any one of claims 22-24, 26-27, 29-30, wherein the fan-in structures are in a plurality of groups, the plurality of groups of fan-in structures being spaced apart on the fan-out structure.

34. The substrate of any one of claims 22-24, 26-27, 29-30, wherein a plurality of discrete devices are disposed within the fan-out structure, the plurality of discrete devices being horizontally spaced apart within the fan-out routing layer.

35. The substrate of claim 34, wherein the discrete device is a capacitor or an inductor.

36. The substrate of claim 27, wherein the fan-out carrier is an inorganic board or the fan-out carrier is an organic board.

37. A packaging structure comprising at least one electronic component and a substrate as claimed in any one of claims 1 to 36, wherein the electronic component is provided on a fan-in structure of the substrate and is electrically connected to a fan-in via in the fan-in structure.

38. A board-level architecture comprising a circuit board, at least one electronic component, and a substrate as claimed in any one of claims 1-36, said substrate being located between said circuit board and said electronic component, and said electronic component being connected to a fan-in structure in said substrate, said circuit board being connected to a fan-out structure in said substrate.

39. The board level architecture of claim 38, wherein the plurality of electronic components are a plurality of fan-in structures in the substrate, the plurality of electronic components being spaced apart on the fan-in structures.

40. The board level architecture of claim 38, wherein the number of electronic components is multiple, the number of fan-in structures in the substrate is multiple, and each group of fan-in structures is provided with one or more of the electronic components.

41. The board level architecture of any one of claims 38-40, wherein the fan-out structure and the circuit board are connected by a sintering process;

Or the fan-out structure is connected with the circuit board through welding.

42. A method of fabricating a substrate, the method comprising:

Providing a fan-out structure and at least one set of fan-in structures, wherein each set of fan-in structures comprises a fan-in carrier plate and a fan-in wiring layer arranged on the fan-in carrier plate;

a patterned semi-cured layer is arranged on one surface of the fan-out structure, and a sintering layer is arranged in the semi-cured layer;

And pressing and sintering at least one group of fan-in structures and the fan-out structures provided with the semi-solidified layers and the sintering layers, wherein the semi-solidified layers and the sintering layers are positioned between the fan-in carrier plates and the fan-out structures, so that the fan-in carrier plates are connected with the fan-out structures in a sintering manner, and fan-in through holes in the fan-in structures are communicated with the fan-out through holes in the fan-out structures through the sintering layers.

43. A method of fabricating a substrate, the method comprising: providing a fan-out structure and at least one set of fan-in structures, wherein each set of fan-in structures comprises a fan-in carrier plate and a fan-in wiring layer arranged on the fan-in carrier plate;

At least one group of fan-in structures and the fan-out structures formed with the semi-solidified layers and the sintering layers are pressed and sintered, the semi-solidified layers and the sintering layers are positioned between the fan-in wiring layers and the fan-out structures, so that the fan-in wiring layers are connected with the fan-out structures in a sintering mode, and fan-in through holes in the fan-in structures are communicated with the fan-out through holes in the fan-out structures through the sintering layers.