CN114499764B

CN114499764B - Rate matching and dematching method and device, mobile terminal and storage medium

Info

Publication number: CN114499764B
Application number: CN202210239270.2A
Authority: CN
Inventors: 柏青
Original assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Current assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Priority date: 2022-03-11
Filing date: 2022-03-11
Publication date: 2024-06-14
Anticipated expiration: 2042-03-11
Also published as: CN114499764A

Abstract

The embodiment of the disclosure provides a rate matching and de-rate matching method, a device, a mobile terminal and a storage medium. The rate matching method comprises the following steps: taking the code word with the completed data channel coding as a unit of a sub-block, and adjusting the bit sequence according to the first sub-block interleaving sequence; selecting bits and interleaving the bits according to the code words with the adjusted bit sequences to complete the rate matching of the data channel; the first sub-block interleaving sequence is determined according to a sub-block importance priority principle. Accordingly, the de-rate matching method comprises the following steps: after the bit de-selection is completed, the sub-block interleaving inverse operation is performed to restore its bit order for subsequent data decoding. According to the rate matching scheme provided by the embodiment of the disclosure, before bit selection and bit interleaving, the sub-blocks are used as units for carrying out bit sequence adjustment, the sub-blocks with higher importance are arranged in front, physical resources can be saved, the transmission delay of data and the power consumption of a system can be reduced, and the transmission performance of the communication system is comprehensively improved.

Description

Rate matching and dematching method and device, mobile terminal and storage medium

Technical Field

The present invention relates to, but not limited to, the field of mobile communications, and in particular, to a method and apparatus for rate matching and rate de-matching, a mobile terminal, and a storage medium.

Background

In modern digital communication systems, the transmitting end of the digital signal needs to perform rate matching on the code words after channel coding, so that the code stream length matches with the actual transmission capability. A rate matching scheme for NR data channels specified according to 3GPP protocols, comprising: two steps of bit selection and bit interleaving, combining with the HARQ mechanism and/or the bit interleaving scheme, how to more effectively improve the transmission performance, is a direction continuously explored in the art.

Disclosure of Invention

The embodiment of the disclosure provides a rate matching and de-rate matching method, a device, a mobile terminal and a storage medium, which are used for carrying out bit sequence adjustment by taking a sub-block as a unit before carrying out bit selection and bit interleaving in a related scheme, leading the sub-block with higher importance, saving physical resources, reducing the transmission delay of data and the power consumption of a system, and comprehensively improving the transmission performance of a communication system.

The embodiment of the disclosure provides a rate matching method, which comprises the following steps:

taking the code word with the completed data channel coding as a unit of a sub-block, and adjusting the bit sequence according to the first sub-block interleaving sequence;

Selecting bits and interleaving the bits according to the code words with the adjusted bit sequences to complete the rate matching of the data channel;

The first sub-block interleaving sequence is determined according to a sub-block importance priority principle.

The embodiment of the disclosure also provides a method for rate de-matching, which comprises the following steps:

Bit de-interleaving and bit de-selecting are carried out on the demodulated code word, and a code word to be de-interleaved is obtained;

The code word to be deinterleaved takes the sub-blocks as units, and bit sequence adjustment is carried out according to the first sub-block interleaving sequence to obtain the code word to be decoded; the code word to be decoded is used for carrying out data channel decoding to obtain a decoded code word;

The embodiment of the disclosure also provides a rate matching device, which comprises:

The first interleaving module is used for carrying out bit sequence adjustment according to the first subblock interleaving sequence by taking the subblock as a unit for the code word which is subjected to data channel coding;

The selecting and interleaving module is set to perform bit selection and bit interleaving according to the code words after the bit sequence adjustment so as to complete the rate matching of the data channel;

The embodiment of the disclosure also provides a device for rate de-matching, which comprises:

The de-interleaving selection module is used for performing bit de-interleaving and bit de-selection on the demodulated code word to obtain a code word to be de-interleaved;

The first de-interleaving module is used for taking the code word to be de-interleaved as a unit, and carrying out bit sequence adjustment according to the first sub-block interleaving sequence to obtain the code word to be decoded; the code word to be decoded is used for carrying out data channel decoding to obtain a decoded code word;

The disclosed embodiments also provide a mobile terminal including a communication chip configured to perform:

The disclosed embodiments also provide a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements a rate matching method as described in any of the embodiments of the disclosure.

Embodiments of the present disclosure also provide a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements a solution rate matching method according to any of the embodiments of the present disclosure.

Other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to the structures shown in these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a module for implementing data channel rate matching and correlation;

FIG. 2 is a schematic diagram of a structure of NR LDPC coded codewords;

FIG. 3 is a mapping specification of 3GPP for bit (b) to modulation symbol (d);

Fig. 4 is a schematic diagram of a rate matching and de-rate matching flow proposed in an embodiment of the present disclosure;

FIG. 5 is a flow chart of a rate matching method in an embodiment of the disclosure;

FIG. 6 is a schematic diagram of a sub-block interleaving result in an embodiment of the present disclosure;

fig. 7 is a schematic diagram of a block error rate vs. signal-to-noise ratio simulation result (mcs=16) in an embodiment of the disclosure;

fig. 8 is a schematic diagram of a simulation result of another block error rate vs. signal-to-noise ratio (mcs=20) in an embodiment of the disclosure;

fig. 9 is a schematic diagram of a simulation result of another block error rate vs. signal-to-noise ratio (mcs=27) in an embodiment of the disclosure;

FIG. 10 is a flow chart of a method of de-rate matching in an embodiment of the present disclosure;

fig. 11 is a schematic structural diagram of a rate matching device according to an embodiment of the disclosure;

Fig. 12 is a schematic structural diagram of a de-rate matching device according to an embodiment of the disclosure.

The achievement of the objects, functional features and advantages of the present invention will be further described with reference to the accompanying drawings, in conjunction with the embodiments.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

It should be noted that all directional indicators (such as up, down, left, right, front, and rear … …) in the embodiments of the present invention are merely used to explain the relative positional relationship, movement, etc. between the components in a particular posture (as shown in the drawings), and if the particular posture is changed, the directional indicator is changed accordingly.

Furthermore, descriptions such as those referred to as "first," "second," and the like, are provided for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implying an order of magnitude of the indicated technical features in the present disclosure. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present invention, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.

In the present invention, unless specifically stated and limited otherwise, the terms "connected," "affixed," and the like are to be construed broadly, and for example, "affixed" may be a fixed connection, a removable connection, or an integral body; can be mechanically or electrically connected; either directly or indirectly, through intermediaries, or both, may be in communication with each other or in interaction with each other, unless expressly defined otherwise. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.

In addition, the technical solutions of the embodiments of the present invention may be combined with each other, but it is necessary to be based on the fact that those skilled in the art can implement the technical solutions, and when the technical solutions are contradictory or cannot be implemented, the combination of the technical solutions should be considered as not existing, and not falling within the scope of protection claimed by the present invention.

Before the embodiments are described in detail, abbreviations for the relevant terms referred to in this disclosure are as follows:

according to the protocol specification of 3GPP (38.212-5.4.2), rate matching of NR data channels comprises two steps:

1) Bit selection (bit selection)

Writing the bit stream after LDPC coding into a ring buffer with a size of N _cb, and reading data according to the initial position determined by the redundancy version (rv) until the number of the read effective bits reaches a given value E.

2) Bit interleaving (bit interleaving)

Writing a bit-selected bit stream in a row into a dimensionAnd then read out column by column. Where Q _m represents the number of bits each modulation symbol contains (e.g., for 16-QAM Q _m =4, for 256-QAM Q _m＝8),E/Q_m the number of modulation symbols (E is calculated in a rule that ensures it is an integer multiple of Q _m).

The bit stream obtained after rate matching is subjected to the processing of code block connection and scrambling, and is mapped to a modulation symbol through modulation. Note that the code block concatenation and scrambling do not affect the bit order in a single code block. In some implementations, the rate matching process in the NR data channel and its associated modules are shown in fig. 1.

In some achievable bit-level processing of the data channel, the design of rate matching is closely related to the design of the LDPC code and the HARQ mechanism. After the physical resources allocated to PDSCH and the MCS to be used are determined, the system can calculate the size of the Transport Block (TBS), the relevant parameters of the code blocks (size, LDPC coded base map index and lifting values, etc.), and the number of available transmission bits per code block (E). According to the selected base diagram, the LDPC encoder carries out complete encoding on the input information bits to obtain a bit stream corresponding to the lowest encoding rate (BG 1 is 1/3 and BG 2 is 1/5). The complete codeword of NR LDPC has a specific structure as shown in fig. 2: the first part is information bit, the second part is core check bit with length of 4.Z _c, and the third part corresponds to expansion check bit with column degree of 1. In general, the size of the ring buffer is equal to the length of the complete codeword; that is, all check bits can be written to the ring buffer.

When the HARQ mechanism is used, initial transmission starts from the initial position of the code word to select bits, if the number of bits available for transmission is smaller than the size of the ring buffer (E < N _cb), the actually transmitted code word is not a complete code word, and partial check bits are not transmitted, so that the effective code rate is higher than the coding code rate. If the primary transmission fails in decoding, the transmitting end knows that retransmission is needed through feedback (NACK), and then the starting position of new bit selection is determined according to the reselected redundancy version. By retransmission, the system can send check bits which are not sent in the initial transmission, thereby reducing the effective code rate. When the channel condition is poor, and the code block is retransmitted for a plurality of times, all the transmitted bits can generally cover the whole annular buffer, and the effective code rate can be lower than the lowest coding rate because part of the bits are repeatedly transmitted.

The fewer and better the number of transmissions required for successful decoding, taking into account latency, power consumption, physical resources occupied, etc. From the design of bit selection, this means that we should try to place bits that are more "important" for decoding in front of the codeword, making it more likely that it will be sent at the time of initial transmission. It can be seen that the existing LDPC coding and bit selection designs of 3GPP are in accordance with this principle: the information bits are at the forefront of the codeword, followed by core check bits that participate in multiple check equations, and finally by extended check bits that participate in only one check equation. On this basis, the design of the bit interleaver also follows this principle: the order in which bits are read out from the interleaving matrix (i.e., the row order of the interleaving matrix) corresponds to the high-to-low reliability of bits in the modulation symbols (note that the two bits contained in each symbol in QPSK have the same reliability) according to the mapping rule shown in fig. 3. That is, bits written first into the interleaving matrix are given better noise immunity during transmission. For the initial transmission of the code block, the information bits and the core check bits are written into the interleaving matrix before the extended check bits, so that higher reliability is possible.

It has been found that for overall improved decoding performance, the design of bit selection should follow the principle of "high to low importance" for a given LDPC coding scheme and bit-to-modulation symbol mapping scheme. The relevant protocol specification follows this principle as a whole, but leaves room for optimization in detail. For example, these achievable schemes do not take into account ordering problems between information bits and between extended check bits, and do not allow for a greater likelihood that more important bits will appear in the primary transmission and be received with higher reliability. The method and the device have the advantages that the subblock interleaving function is added before the bit selection processing, and the coded bit stream is rearranged to a certain extent, so that more important bits are more likely to appear in the primary transmission and are received with higher reliability, and the decoding performance of the system is improved.

In order to optimize the bit order of the encoded codeword, the disclosed embodiment proposes to add a sub-block interleaver before the bit selection module at the transmitting end, as shown in fig. 4. Accordingly, when the receiving end performs rate de-matching, a sub-block de-interleaver performing inverse operation needs to be added after the bit de-selection.

An embodiment of the present disclosure provides a rate matching method, as shown in fig. 5, including:

Step 510, the code word with the data channel coding completed is used as a unit of sub-blocks, and the bit sequence adjustment is carried out according to the first sub-block interleaving sequence;

step 520, selecting bits and interleaving bits according to the codeword with the bit sequence adjusted to complete data channel rate matching;

In some exemplary embodiments, the rate matching method is applied to rate matching of a data channel.

The codeword with completed data channel coding at least comprises: information bits, first check bits and second check bits;

Wherein the importance of the sub-block corresponding to the information bit and the importance of the sub-block corresponding to the first parity bit are higher than the importance of the sub-block corresponding to the second parity bit.

It is known to those skilled in the art that the sub-block interleaving means that the original sub-block arrangement order is rearranged in units of sub-blocks, and the sub-block interleaving order is an order for indicating the rearrangement of sub-blocks in the sub-block interleaving. For example, before interleaving, the encoded codeword includes N sub-blocks arranged front to back in the order of sub-block numbers 1 to N; after rearrangement (after interleaving), the corresponding sub-blocks from front to back are numbered: i, x, N,1, … (N total sub-blocks, i, x, N representing sub-block numbers, being a number greater than 1 and less than N), where rearranged sub-block numbers (i, x, N,1, …) are sub-block interleaving order, it is understood that sub-block interleaving is: the sub-blocks numbered 1-N are rearranged in this sub-block interleaving order to obtain a new codeword.

It should be noted that, the importance of the sub-block corresponding to the different types of bit data indicates the importance of the bit data included in the sub-block to the success of decoding. In some exemplary embodiments, the importance of the sub-block corresponding to the information bits (SYSTEMATIC BITS) containing traffic data in the data channel is greater than or equal to the parity bits (parity bits) containing parity data. In some exemplary embodiments, the data channel encoded codeword may also include various types of parity bits, such as: the first check bit and the second check bit may correspond to the same or different importance levels according to schemes generated by the check bits of different types and corresponding roles in the decoding process. In some exemplary embodiments, the importance levels of different sub-block bit data may be the same or different among the same type of check bits. In some exemplary embodiments, the first sub-block interleaving order is determined according to a sub-block importance priority principle. For different coding schemes, statistical information of importance of each sub-block (bit) is obtained through theoretical analysis and/or simulation, and the first sub-block interleaving sequence used in the scheme application process is correspondingly determined.

In some exemplary embodiments, the codeword for which the data channel coding has been completed is a low density parity check code, LDPC, encoded codeword, the first parity bits are core parity bits, and the second parity bits are extension parity bits.

It should be noted that, the scheme provided by the embodiment of the disclosure improves the rate matching scheme in the related scheme, and adds a sub-block interleaving module (sub-block interleaver) before the bit selection processing, so as to optimize the bit sequence of the data channel coding codeword, and especially when using high-order modulation and higher code rate, the performance of primary transmission and first retransmission can be improved.

In some exemplary embodiments, the LDPC coded codeword as shown in FIG. 2 includes information bits (SYSTEMATIC BITS), core parity bits (KERNEL PARITY bits), and extended parity bits (granularity-1 parity bits) having a granularity of 1.

In some exemplary embodiments, in the sub-blocks corresponding to the extended check bits, the higher the row weight of each sub-block in the row in the LDPC check matrix, the higher the importance of the sub-block.

In some exemplary embodiments, in the sub-blocks corresponding to the information bits and the core check bits, the importance of each sub-block is determined according to the row order of each sub-block related to the LDPC check matrix.

In some exemplary embodiments, in the sub-blocks corresponding to the information bits and the core check bits, the importance of each sub-block is determined according to the row order of each sub-block related to the LDPC check matrix, including:

determining row sequences of all sub-blocks related to the LDPC check matrix respectively;

The importance of the sub-block preceding in row order is determined to be higher than the importance of the sub-block following in row order.

In some exemplary embodiments, the first sub-block interleaving order is determined according to a sub-block importance priority principle, including:

And sequencing all the subblocks included in the code word subjected to the data channel coding according to the order of the importance of the subblocks from high to low, and determining the sequence of the sequenced subblocks as the first subblock interleaving sequence.

That is, the sub-blocks are rearranged according to the order of importance from high to low included in the code word after the data channel coding is completed, so as to obtain an interleaved code word, and the sub-block order corresponding to the interleaved code word is the first sub-block interleaving order. It can be seen that the importance of the preceding sub-blocks in the interleaved codeword is higher than or equal to the importance of the following sub-blocks, i.e. the importance of the corresponding sub-blocks in the order from front to back in the sub-block interleaved codeword is higher to lower.

In some exemplary embodiments, the size of the sub-block is a lifting value Z _c employed in LDPC coding.

It should be noted that, the first sub-block interleaving order is determined according to the sub-block importance priority principle, and in the determining step 510, the bit sequence of the data channel coding codeword is adjusted according to the determined first sub-block interleaving order.

In some exemplary embodiments, the first sub-block interleaving order determined according to the sub-block importance priority principle satisfies at least one of the following:

Maintaining information bits and core check bits prior to extension check bits;

the extended check bits are arranged according to the row weight of the extended check bits in the LDPC check matrix from high to low;

For the information bits and the core check bits, the bits related to the zeroth row of the LDPC check matrix are arranged at the forefront, and then the bits related to the first, second and third rows but not participating in the sorting are arranged in sequence.

The bit sequence of the LDPC encoded codeword is adjusted according to the determined first sub-block interleaving sequence, which is also referred to as sub-block interleaving. In some exemplary embodiments, the sub-block interleaving may be considered as a certain adjustment of the rank order in the LDPC base graph, so its addition does not actually increase the complexity of the system implementation.

Taking BG1 of LDPC as an example, the codeword after sub-block interleaving is shown in fig. 6. In the code word with the bit sequence adjusted, the information bit and the core check bit are before the expansion check bit; the more the row sequence of each sub-block relative to the LDPC check matrix is, the more the corresponding adjusted position is, namely, the row sequence of the sub-blocks relative to the LDPC check matrix is 0, 1,2 or 3 respectively, the corresponding sub-blocks are arranged from front to back in sequence according to the sequence of the row sequence 0-3; the higher the row weight of each row in the LDPC check matrix, the more front the corresponding adjusted position is, namely, the row with higher row weight is arranged in front and the row with lower row weight is arranged in back in the rearranged extended check bit.

As shown in fig. 7, 8 and 9, the performance simulation results of the initial transmission and the first retransmission at mcs= 16,20,27 (according to 38.214-Table 5.1.3.1-2) are given. Note that the performance of the suboptimal decoding algorithm is greatly affected by parameter selection (for example, the performance of the normalized minimum sum algorithm is closely related to the selection of the normalization factor), while the addition of the sub-block interleaver may change the optimal parameter value, so that in order to ensure fairness of comparison simulation, a sum-product (sum-product) algorithm with better performance and without parameter adjustment is selected as the LDPC decoding algorithm. Other main simulation conditions include: AWGN channel, each SNR point has 20000 simulation times, the redundancy versions of primary transmission and first retransmission are 0,2 respectively; the decoder adopts layered decoding, performs layer scheduling according to the sequence from low row weight to high row weight, and the maximum iteration number is set to be 12. The determined order of sub-block interleaving (base graph one) is seen by comparing the simulation results as follows ：0,1,3,4,7,8,9,10,11,13,14,16,17,18,19,20,21,2,5,6,12,15,22,23,28,29,26,31,25,35,34,32,30,27,44,41,40,39,38,37,36,33,64,63,61,59,58,56,55,54,53,52,51,50,49,48,46,45,43,42,65,62,60,57,47,24. The addition of sub-block interleavers improves decoding performance for several different MCSs. The magnitude of improvement is about 0.1-0.2dB over the BLER e [10 ^-3,10^-2 ]. Other MCSs, maximum retransmission times, and maximum iteration times were also simulated, and different degrees of performance improvement by the sub-block interleaver were observed.

In some exemplary embodiments, the codeword with completed data channel coding is an LDPC BG1 encoded codeword, and the first sub-block interleaving order is:

0，1，3,4,7，8,9,10,11,13,14,16，17，18,19,20,21,2,5，6,12，15,22,23，

28,29,26,31,25,35,34,32,30,27,44,41,40,39,38,37,36,33,64,63,61，

59,58,56,55,54,53,52,51,50，49,48,46,45，43，42，65,62,57，47,24。

It can be seen that in some exemplary implementations, in step 510, the codeword after data channel encoding is performed using LDPC BG1, the bit sequence of the encoded codeword is adjusted according to the first sub-block interleaving sequence described above in units of sub-blocks, and the adjusted codeword is subjected to bit selection and bit interleaving to complete data channel rate matching. For the code word of the data channel coding by using the LDPC BG2, the importance of each sub-block can be determined through correlation analysis and/or simulation, and the interleaving sequence of the corresponding first sub-block is determined for corresponding rate matching and de-rate matching. More detailed examples, which are not one example herein.

It should be noted that, for a digital signal communication system that uses an HARQ mechanism or implements high-to-low reliability symbol mapping by bit interleaving, the rate matching scheme provided by the implementation of the present disclosure may be adopted, so that the bits of the encoded codeword are ordered from high importance to low importance before the bit selection is performed. For different coding schemes, statistical information of importance of each sub-block (bit) is obtained through theoretical analysis and/or simulation, and a corresponding first sub-block interleaving sequence is determined based on the statistical information, so that sub-block interleaving before bit selection is realized. The specific first sub-block interleaving order is not limited to aspects of the examples shown in the above-described embodiments of the present disclosure.

The embodiment of the disclosure also provides a method for rate de-matching, as shown in fig. 10, including:

Step 1010, performing bit de-interleaving and bit de-selection on the demodulated codeword to obtain a codeword to be de-interleaved;

step 1020, adjusting the bit sequence of the codeword to be deinterleaved according to the first subblock interleaving sequence by taking the subblock as a unit to obtain a codeword to be decoded; the code word to be decoded is used for carrying out data channel decoding to obtain a decoded code word;

In some exemplary embodiments, the de-rate matching method is applied to a data channel.

It should be noted that, the rate de-matching method provided by the embodiment of the present disclosure is a codeword processing method of a receiving end corresponding to the rate matching method provided by the embodiment of the present disclosure, which is an inverse operation of the rate matching method. Based on the descriptions of the steps of rate matching, those skilled in the art can clearly know the implementation of the steps corresponding to rate dematching, and the details are not repeated here.

The first sub-block interleaving sequence used in step 1010 is consistent with the first sub-block interleaving sequence determined in the rate matching scheme, and de-interleaving is performed according to the first sub-block interleaving sequence, so that a codeword with recovered bit sequence can be obtained, and the recovered codeword can be decoded according to the relevant channel data decoding scheme to obtain corresponding service data. From the determined first sub-block interleaving order, the implementation steps of the corresponding sub-block interleaving and sub-block de-interleaving will be explicitly known to a person skilled in the art, and specific aspects are not discussed in detail in the embodiments of the present application.

The embodiment of the present disclosure further provides a rate matching device 1100, as shown in fig. 11, including:

A first interleaving module 1110 configured to perform bit sequence adjustment according to a first sub-block interleaving sequence with respect to the codeword for which data channel coding has been completed in units of sub-blocks;

a selecting and interleaving module 1120 configured to perform bit selection and bit interleaving according to the codeword with the bit sequence adjusted to complete data channel rate matching;

In some exemplary embodiments, the selective interleaving module 1120 includes: a bit selection unit 1121 configured to perform bit selection according to the codeword whose bit order is adjusted; bit interleaving unit 1122 is configured to perform bit interleaving on the selected codeword to complete data channel rate matching.

The embodiment of the present disclosure also provides a mobile terminal including the rate matching device 1100 described above.

The embodiment of the present disclosure further provides a rate de-matching apparatus 1200, as shown in fig. 12, including:

A de-interleaving selection module 1210, configured to perform bit de-interleaving and bit de-selection on the demodulated codeword to obtain a codeword to be de-interleaved;

A first de-interleaving module 1220, configured to use the sub-block as a unit and perform bit sequence adjustment according to the first sub-block interleaving sequence to obtain a codeword to be decoded; the code word to be decoded is used for carrying out data channel decoding to obtain a decoded code word;

In some exemplary embodiments, the de-interleaving selection module 1210 includes: a bit de-interleaving unit 1211 configured to bit de-interleave the demodulated codeword; the bit de-selection unit 1212 is configured to perform bit de-selection on the bit de-interleaved codeword to obtain a codeword to be de-interleaved.

It will be appreciated that the codeword to be deinterleaved here corresponds to the output codeword of the first interleaving module 1110 in the rate matching device 1100.

The embodiment of the present disclosure also provides a mobile terminal, including the rate de-matching apparatus 1200 as described above.

The disclosed embodiments also provide a storage medium having a computer program stored therein, wherein the computer program is configured to perform the rate matching method described in any of the embodiments above when run.

The disclosed embodiments also provide a storage medium having a computer program stored therein, wherein the computer program is configured to perform the de-rate matching method described in any of the embodiments above when run.

According to the rate matching method provided by the embodiment of the disclosure, the sub-block interleaving step is added before the bit selection, so that the sub-block (bit) with higher importance is pre-arranged, then the bit selection and the bit interleaving are performed, the sub-block (bit) with higher importance can be retransmitted for the first time or retransmitted for the first time, the physical resource is saved, and the transmission delay of information and the power consumption of a communication system are reduced. Particularly, under the conditions of higher-order modulation and higher code rate, the improvement effect on primary transmission and first retransmission is more obvious.

Those of ordinary skill in the art will appreciate that all or some of the steps, systems, functional modules/units in the apparatus, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between the functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed cooperatively by several physical components. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as known to those skilled in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Furthermore, as is well known to those of ordinary skill in the art, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media.

The foregoing description is only of the preferred embodiments of the present invention and is not intended to limit the scope of the invention, and all equivalent structural changes made by the specification and drawings of the present invention or direct/indirect application in other related technical fields are included in the scope of the present invention.

Claims

1. A method of rate matching comprising:

Wherein, the code word after completing the data channel coding is a low density parity check code LDPC code word, at least comprising: information bits, first check bits and second check bits; the first check bit is a core check bit, and the second check bit is an extension check bit;

The first sub-block interleaving sequence is determined according to a sub-block importance priority principle; the importance of the sub-block corresponding to the information bits and the importance of the sub-block corresponding to the first parity bits are higher than the importance of the sub-block corresponding to the second parity bits.

2. The method of claim 1, wherein,

And in the sub-blocks corresponding to the extended check bits, the higher the row weight of each sub-block in the row of the LDPC check matrix is, the higher the importance of the sub-block is.

3. The method of claim 1, wherein,

And in the sub-blocks corresponding to the information bits and the core check bits, the importance of each sub-block is determined according to the row sequence of each sub-block and the LDPC check matrix.

4. The method of claim 3, wherein,

The importance of each sub-block is determined according to the row sequence of each sub-block and the LDPC check matrix, and the method comprises the following steps:

5. The method of any one of claim 1 to 4,

The first sub-block interleaving order is determined according to a sub-block importance priority principle, and comprises the following steps:

6. A method of de-rate matching, comprising:

Wherein, the codeword to be decoded is a low density parity check code (LDPC) encoded codeword, at least comprising: information bits, first check bits and second check bits; the first check bit is a core check bit, and the second check bit is an extension check bit;

7. A rate matching device, comprising:

8. A de-rate matching device, comprising:

9. A mobile terminal comprising a communication chip configured to perform:

10. A mobile terminal comprising a communication chip configured to perform:

11. A computer readable storage medium having stored thereon a computer program, which when executed by a processor implements the rate matching method according to any of claims 1-5; or the program when executed by a processor implements the method of de-rate matching as claimed in claim 6.