CN114499436A - Passive crystal frequency trimming circuit - Google Patents
Passive crystal frequency trimming circuit Download PDFInfo
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- CN114499436A CN114499436A CN202210059258.3A CN202210059258A CN114499436A CN 114499436 A CN114499436 A CN 114499436A CN 202210059258 A CN202210059258 A CN 202210059258A CN 114499436 A CN114499436 A CN 114499436A
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- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
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Abstract
The invention provides a passive crystal frequency fine-tuning circuit, which comprises a direct-current voltage adjusting module, a capacitance fine-tuning module, a passive crystal clock generating module and a link impedance optimizing circuit, wherein the direct-current voltage adjusting module is used for receiving an input signal, performing high-frequency filtering on the input signal and outputting a direct-current signal; the capacitance trimming module comprises a variable capacitance diode, and the variable capacitance diode receives the direct current signal output by the direct current voltage adjusting module as a reverse voltage to realize capacitance adjustment. The passive crystal output frequency fine-tuning circuit provided by the scheme can adjust the reverse voltage of the variable capacitance diode by changing the direct-current voltage amplitude or the PWM signal frequency duty ratio, change the load capacitance value of the passive crystal, further change the frequency and solve the problem that the frequency cannot be adjusted.
Description
Technical Field
The invention belongs to the technical field of clock circuits, and particularly relates to a passive crystal frequency fine tuning circuit.
Background
With the rapid rise of big data, most of modern circuit systems are digital circuits, a large number of digital chips such as an FPGA, a CPU, a DSP and the like are used in the circuits, and the chips need system clock input during working. The chip multiplies the frequency of the system clock by a phase-locked loop to various frequency values, and the frequency values are used for each module circuit in the chip.
The system clock input scheme is to use a high-cost active crystal oscillator as shown in fig. 1, and directly output a fixed frequency value to obtain a clock. There is also a trimming oscillating circuit built by using a passive crystal and an inverter to output a frequency trimming clock, as shown in fig. 2.
The prior art has the following disadvantages:
1. generally, after the type of the active crystal oscillator is determined, the output frequency value of the active crystal oscillator can only be a fixed value. If the crystal oscillator batches are different, the output frequency of the crystal oscillator generates frequency deviation, and when the frequency deviation exceeds the input index range of a phase-locked loop in a chip and the active crystal oscillator cannot be subjected to frequency fine adjustment, the phase-locked loop cannot work, so that the chip cannot work. Or the frequency value of the phase-locked loop after frequency multiplication is deviated, and the error of the active crystal oscillator is multiplied, so that the chip works abnormally.
2. After the type of a passive crystal is determined, a Colpitts oscillation circuit is formed by matching with an inverter and an adjustable load capacitor, and a frequency fine adjustment clock can be output. However, the common adjustable capacitors are adjusted by mechanical knobs, so that the accuracy and consistency of adjustment of load capacitance values cannot be guaranteed, and the first pass yield of batch production is reduced. Meanwhile, the adjustable capacitor knob is aged, the capacitor is adjusted to be invalid, and the frequency of an output clock is unstable. When the capacitance value is adjusted stably, manual misoperation exists, the capacitance value is changed, and the output frequency is changed.
3. Modern semiconductor technology is constantly breaking through and signal integrity issues also arise at low frequencies. For example, although the frequency of a crystal oscillator or crystal is several hundreds KHz to several tens MHz, the rising time of the crystal oscillator or crystal becomes steeper and the signal bandwidth becomes wider due to the semiconductor process, the first challenge in clock transmission is the influence of the waveform quality of the transmission channel, and the common phenomenon is ringing and overshoot of the rising edge and the falling edge, which may generate high-frequency parasitic oscillation, radiation, noise, and the like. Meanwhile, the tolerance between PCB manufacture and Layout of Layout can also cause the problems.
Disclosure of Invention
In view of the above, the present invention is directed to a passive crystal frequency trimming circuit for achieving precise trimming of a clock frequency.
In order to achieve the purpose, the technical scheme of the invention is realized as follows:
the passive crystal frequency fine tuning circuit comprises a direct-current voltage adjusting module, a capacitance fine tuning module, a passive crystal clock generating module and a link impedance optimizing circuit, wherein the direct-current voltage adjusting module is used for receiving an input signal, performing high-frequency filtering on the input signal and outputting a direct-current signal; the capacitance fine adjustment module comprises a variable capacitance diode, and the variable capacitance diode receives the direct current signal output by the direct current voltage adjustment module as a reverse voltage to realize capacitance adjustment; the passive crystal clock generation module is a clock circuit formed by a passive crystal, and the clock circuit adjusts the clock frequency according to the output of the capacitance trimming module; and the link impedance optimization circuit receives the clock signal output by the passive crystal clock generation module, performs impedance optimization and outputs the clock signal.
Furthermore, the direct-current voltage regulating module is a multi-order variable low-pass filter and comprises a multi-order low-pass filter and a bandwidth selection control circuit, the multi-order low-pass filter comprises a plurality of RC filter structures which are sequentially connected in series, the bandwidth selection control circuit comprises a plurality of switch circuits formed by transistors, each RC filter structure is controlled to be conducted by one switch circuit, and the control end of each switch circuit is controlled by one control signal output by the processor; the input signal of the multistage low-pass filter is a direct current signal or a PWM signal.
Further, the capacitance trimming module comprises a varactor diode D1 and a capacitor C4, the anode of the varactor diode D1 is grounded, and the cathode is connected with the capacitor C4 and the output signal of the direct-current voltage regulation module; the other end of the capacitor C4 is connected to a clock circuit.
Furthermore, the clock circuit comprises a passive crystal Y1 and a follower circuit formed by a transistor Q1, one end of the passive crystal Y1 is connected with the output of the capacitance fine tuning circuit and a capacitor C3, and the other end of the capacitor C3 is grounded; the other end of the passive crystal Y1 is simultaneously connected with one end of a resistor R1, one end of a capacitor C1 and the base electrode of a triode Q1, the other end of the resistor R1 is connected with the collector electrode of a triode Q1, the collector electrode of the triode Q1 is simultaneously connected with a signal VCC _ BAR, the other end of the capacitor C1 is simultaneously connected with the emitter electrode of the triode Q1 and one end of the capacitor C2, the other end of the capacitor C2 is grounded, the emitter electrode of the triode Q1 is grounded through a resistor R2, and the emitter electrode of the triode Q1 is connected with the link impedance optimization circuit.
Further, the link impedance optimization circuit comprises a relay LS1, a low-pass filter and a damping resistor circuit, wherein the low-pass filter consists of a ferrite magnetic ring L1 and a capacitor C5; the relay LS1 is used for selecting a clock signal output channel, the input end of the relay LS1 is connected with the output of the clock circuit, and the output end of the relay LS1 is connected with a damping resistor circuit; the control signal Relay _ control of the Relay is controlled by the coprocessor to be output, and the channel selection of the Relay is controlled, wherein one channel is that the signal of the input end is directly output to the damping resistance circuit, and the other channel is that the signal of the input end passes through the low-pass filter and then is output to the damping resistance circuit.
Furthermore, the damping resistor circuit comprises a resistor R17 and a resistor R5, one end of the resistor R17 is connected with the output end of the relay LS1, the other end of the resistor R17 is simultaneously connected with the output signal end Clock _ OUT and one end of the resistor R5, and the other end of the resistor R5 is grounded.
Compared with the prior art, the invention has the following advantages:
(1) the passive crystal output frequency fine-tuning circuit provided by the scheme can adjust the reverse voltage of the variable capacitance diode by changing the direct-current voltage amplitude or the PWM signal frequency duty ratio, change the load capacitance value of the passive crystal, further change the frequency and solve the problem that the frequency cannot be adjusted.
(2) Aiming at the problems of poor adjustment accuracy and consistency, aging and misoperation of devices of the passive crystal adjustable capacitor, the scheme can accurately and quantitatively adjust the load capacitance value of the passive crystal by controlling the reverse voltage of the variable capacitance diode and matching with a precise direct current adjusting network. The varactor technology is mature, and the device is stable, reliable and durable. The regulating voltage is controlled by the CPU, and the capacitance value cannot be changed by manual misoperation after being finely adjusted and fixed. A series of problems of adjustable capacitance are solved.
(3) The problem of signal integrity can also occur in a low-frequency clock, and the scheme designs a damping resistance circuit and a low-pass filter circuit to shape the clock waveform, so that the rising edge and the falling edge are slowed down, the impedance of a signal link is optimized, and the problems of high-frequency parasitic oscillation, radiation and noise are solved.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the invention without limitation. In the drawings:
FIG. 1 is a clock circuit diagram of a conventional active crystal oscillator;
FIG. 2 is a clock circuit diagram of a conventional passive crystal oscillator;
FIG. 3 is a schematic block diagram of a passive crystal frequency trimming circuit according to an embodiment of the present invention;
FIG. 4 is a circuit diagram of a passive crystal frequency trimming circuit according to an embodiment of the present invention;
fig. 5 is a graph of capacitance versus reverse voltage for a varactor diode according to an embodiment of the present invention;
fig. 6 a and b are schematic diagrams respectively illustrating two link channel selection of a link impedance optimization circuit according to an embodiment of the present invention.
Detailed Description
It should be noted that the embodiments and features of the embodiments of the present invention may be combined with each other without conflict.
The invention will be described in detail with reference to the following embodiments with reference to the attached drawings.
The operation principle of the passive crystal frequency trimming circuit is described in detail below.
As shown in fig. 3, the passive crystal frequency trimming circuit of this embodiment includes A, B, C, D four parts, which are a dc voltage adjusting module, a capacitance trimming module, a passive crystal clock generating module and a link impedance optimizing circuit,
the direct-current voltage regulating module is used for receiving an input signal, performing high-frequency filtering on the input signal and outputting a direct-current signal;
the capacitance fine adjustment module comprises a variable capacitance diode, and the variable capacitance diode receives the direct current signal output by the direct current voltage adjustment module as a reverse voltage to realize capacitance adjustment;
the passive crystal clock generation module is a clock circuit formed by a passive crystal, and the clock circuit adjusts the clock frequency according to the output of the capacitance trimming module;
and the link impedance optimization circuit receives the clock signal output by the passive crystal clock generation module, performs impedance optimization and outputs the clock signal.
The specific circuit structure is as follows:
part A is a direct-current voltage precision regulating circuit,
as shown in fig. 4, the input Signal end PWM _ DC _ Signal may be a direct current Signal or a PWM Signal; an input signal end is connected with a resistor R12, the other end of the resistor R12 is connected with a capacitor C9 and a resistor R6, the other end of the resistor R6 is connected with a capacitor C7 and a resistor R9, the other end of the resistor R9 is connected with a capacitor C8 and a resistor R3, and the other end of the resistor R3 is connected with the capacitor fine tuning circuit;
the input signal end is connected with a signal VCC _ BAR through a resistor R15, the other ends of a capacitor C9, a capacitor C7 and a capacitor C8 are respectively connected with the collector electrodes of a triode Q2, a triode Q3 and a triode Q4, the other ends of a capacitor C9, a capacitor C7 and a capacitor C8 are also connected with the signal VCC _ BAR through a resistor R16, and the other end of a resistor R16 is grounded through a capacitor C10; the base electrodes of the triode Q2, the triode Q3 and the triode Q4 are respectively connected with the respective emitter electrodes through a resistor, and the emitter electrodes are all grounded; the base electrodes of the triode Q2, the triode Q3 and the triode Q4 are also respectively connected with 3 control signals BW _ Select _1-3 of the coprocessor.
In the circuit structure, R12 and C9, R6 and C7, R9 and C8 form a multi-stage variable low-pass filter, the bandwidth of the filter can be flexibly adjusted according to the actual circuit environment, PWM frequency and duty ratio, and high-frequency noise is filtered; the bandwidth adjusting mode is as follows: r16, R14, R8, R11, R13, R7, R10, Q2, Q3, Q4 and C10 form a bandwidth selection control circuit, a BW _ Select _1-3 signal is controlled by a coprocessor, the level is set high, a controlled transistor is conducted, and a low-pass filter connected with the controlled transistor is gated; the level is set low and not gated. Where R15 and R3 are level-matched resistors.
The PWM _ DC _ Signal may be a direct current Signal or a PWM Signal, and is converted into a precise direct current Signal after the high frequency component is filtered by the multi-stage variable low-pass filter. The input amplitude of the direct current signal is changed, and after the direct current signal passes through the filter, the output amplitude is changed along with the change of the input amplitude. The frequency and the duty ratio of the PWM signal are changed, and the output amplitude is changed along with the change of the frequency and the duty ratio after the PWM signal passes through the filter. See at Layout that the copper skin under the C9, C7, and C8 capacitors is hollowed out to reduce the parasitic capacitance.
Part B is a capacitance trimming circuit,
the capacitance fine tuning circuit comprises a variable capacitance diode D1 and a capacitor C4, wherein the anode of the variable capacitance diode D1 is grounded, and the cathode of the variable capacitance diode D1 is connected with a capacitor C4 and a resistor R3;
the direct current voltage input by the part A is reversely applied to two ends of the variable capacitance diode D1, and the part A is used for fine tuning the amplitude of the direct current voltage so as to further fine tune the capacitance value of the D1. In Layout, note that the copper skin under D1 and C4 is hollowed out to reduce parasitic capacitance.
The varactor D1 is designed by using the characteristic that the junction capacitance changes with the applied voltage when the pN junction is reversely biased. When the reverse bias voltage is increased, the junction capacitance is reduced, otherwise, the junction capacitance is increased, the capacitance of the variable capacitance diode is generally smaller, and the maximum value is dozens of picofarads to hundreds of picofarads. It is mainly used in high-frequency circuit as Automatic Frequency Control (AFC), electronic tuning, frequency modulation, phase modulation, frequency multiplier, etc. The varactor mainly emphasizes the linear relation between capacitance and voltage through a series of approaches such as structural design and process.
The varactor diode's relationship to the applied reverse voltage can be expressed as follows:
CTis the junction capacitance of the varactor; cT0A junction capacitance when a zero bias voltage is applied to the varactor; vDBuild-in potential difference for varactor PN junction (silicon tube V)D0.7V, germanium tube VD0.3V); gamma is the capacitance change index of the varactor and is related to the magnitude of frequency deviation; v is the reverse voltage applied across the varactor. Under the condition of small frequency offset, the varactor diode with gamma being 1 can approximately realize linear adjustment capacitance; in case of large frequency offset, a varactor with γ ═ 2 must be selected to achieve better linear tuning capacitance.
Part C is a clock circuit that is,
the clock circuit comprises a follower circuit formed by a passive crystal Y1 and a transistor Q1, one end of a passive crystal Y1 is simultaneously connected with the other end of a capacitor C4 and a capacitor C3, and the other end of a capacitor C3 is grounded; the other end of the passive crystal Y1 is simultaneously connected with one end of a resistor R1, one end of a capacitor C1 and the base electrode of a triode Q1, the other end of the resistor R1 is connected with the collector electrode of a triode Q1, the collector electrode of the triode Q1 is simultaneously connected with a signal VCC _ BAR, the other end of the capacitor C1 is simultaneously connected with the emitter electrode of the triode Q1 and one end of the capacitor C2, the other end of the capacitor C2 is grounded, and the emitter electrode of the triode Q1 is grounded through a resistor R2.
In order to ensure the normal operation of the fine tuning circuit, the values of the positive feedback capacitors C1 and C2 are selected to be larger than the value of the start-up load capacitance of the passive crystal Y1. A capacitor C3 is connected in parallel with the varactor D1 of the B part and is used for fine tuning the deviation of the passive crystal Y1, and the central capacitance value can have a regulation range of tens of pf.
The PNP transistor Q1 is designed as an emitter follower with high input impedance and low output impedance, so that the current drawn from the signal source is small, the load capacity is strong, and the generated clock has fast rising and falling edges. See at Layout that the copper skin under C3 is hollowed out to reduce parasitic capacitance.
Part D is a clock signal link impedance optimization circuit,
the circuit comprises a relay LS1, a low-pass filter and a damping resistance circuit; the relay LS1 is used for selecting a clock signal output channel, the input end of the relay LS1 is connected with the output of the clock circuit, and the output end of the relay LS1 is connected with a damping resistor circuit; the control signal Relay _ control of the Relay is controlled by the coprocessor to be output, and the channel selection of the Relay is controlled, wherein one channel is that the signal of the input end is directly output to the damping resistance circuit, and the other channel is that the signal of the input end passes through the low-pass filter and then is output to the damping resistance circuit.
The damping resistance circuit comprises a resistor R17 and a resistor R5, one end of the resistor R17 is connected with the output end of the relay LS1, the other end of the resistor R17 is simultaneously connected with the output signal end Clock _ OUT and one end of the resistor R5, and the other end of the resistor R5 is grounded.
The low-pass filter composed of the ferrite magnetic ring L1 and the capacitor C5 blunts the fast edge of the clock, smoothes the waveform and reduces the high-frequency oscillation (ringing and overshoot).
However, when the clock frequency is high, after low-pass filtering, the rising edge still has ringing, and a part of the oscillation energy is consumed by the damping resistance circuit, so that the circuit is prevented from forming constant-amplitude oscillation. See at Layout that the copper skin under C5 is hollowed out to reduce parasitic capacitance.
And the relay LS1 is used for selecting a clock signal output channel, when the clock generated by the part C meets the use index requirement of the chip, the pin 4 of the relay is cut to 3, the pin 9 of the relay is cut to 10, and direct output is selected and is output to the chip after entering the damping resistance circuit. If the chip does not support the fast edge clock input, the pin 4 of the relay is cut to 5, the pin 9 is cut to 8, the clock waveform is shaped through the low-pass filter, and then the clock waveform enters the damping resistance circuit and is output to the chip. Fig. 6 a and b are schematic diagrams respectively illustrating two link channel selection of the link impedance optimization circuit according to the embodiment of the present invention, where a represents a link in which an input signal first passes through a low-pass filter and then is output to enter a damping resistor circuit; b represents the link where the input signal is directly output into the damping resistance circuit. The control signal Relay _ control of the Relay is controlled and output by the coprocessor to control the channel selection of the Relay.
1. Aiming at the problem that the high-cost active crystal oscillator cannot adjust the frequency, the output frequency adjustable circuit of the passive crystal oscillator solves the problem by adjusting the output frequency value when the condition occurs. The passive crystal has low cost and reduces the circuit cost.
2. Aiming at the problems of poor accuracy and consistency of load capacitance value adjustment, device aging and misoperation, the passive crystal load capacitance value can be accurately and quantitatively adjusted by voltage control of the variable capacitance diode and the matching of a precise direct current adjusting network. The varactor technology is mature, and the device is stable, reliable and durable. The regulating voltage is controlled by the CPU, and the capacitance value cannot be changed by manual misoperation after being finely adjusted and fixed.
3. Aiming at the problem of signal integrity, the damping resistance circuit and the low-pass filter circuit have a method for enabling the rising edge and the falling edge to change and optimizing the impedance when the situation occurs, so that the problem is solved.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and should not be taken as limiting the invention, so that any modifications, equivalents, improvements and the like, which are within the spirit and principle of the present invention, should be included in the scope of the present invention.
Claims (6)
1. The passive crystal frequency fine tuning circuit is characterized by comprising a direct current voltage adjusting module, a capacitance fine tuning module, a passive crystal clock generating module and a link impedance optimizing circuit,
the direct-current voltage regulating module is used for receiving an input signal, performing high-frequency filtering on the input signal and outputting a direct-current signal;
the capacitance fine adjustment module comprises a variable capacitance diode, and the variable capacitance diode receives the direct current signal output by the direct current voltage adjustment module as a reverse voltage to realize capacitance adjustment;
the passive crystal clock generation module is a clock circuit formed by a passive crystal, and the clock circuit adjusts the clock frequency according to the output of the capacitance trimming module;
and the link impedance optimization circuit receives the clock signal output by the passive crystal clock generation module, performs impedance optimization and outputs the clock signal.
2. The passive crystal frequency trimming circuit of claim 1, wherein: the direct-current voltage regulating module is a multi-order variable low-pass filter and comprises a multi-order low-pass filter and a bandwidth selection control circuit, the multi-order low-pass filter comprises a plurality of RC filter structures which are sequentially connected in series, the bandwidth selection control circuit comprises a plurality of switch circuits formed by transistors, each RC filter structure is controlled to be conducted by one switch circuit, and the control end of each switch circuit is controlled by one control signal output by a processor; the input signal of the multistage low-pass filter is a direct current signal or a PWM signal.
3. The passive crystal frequency trimming circuit of claim 1, wherein: the capacitance trimming module comprises a variable capacitance diode D1 and a capacitor C4, the anode of the variable capacitance diode D1 is grounded, and the cathode of the variable capacitance diode D1 is connected with the capacitor C4 and an output signal of the direct-current voltage adjusting module; the other end of the capacitor C4 is connected to a clock circuit.
4. The passive crystal frequency trimming circuit of claim 1, wherein: the clock circuit comprises a passive crystal Y1 and a follower circuit formed by a transistor Q1, one end of the passive crystal Y1 is simultaneously connected with the output of the capacitance fine tuning circuit and a capacitor C3, and the other end of the capacitor C3 is grounded; the other end of the passive crystal Y1 is simultaneously connected with one end of a resistor R1, one end of a capacitor C1 and the base electrode of a triode Q1, the other end of the resistor R1 is connected with the collector electrode of a triode Q1, the collector electrode of the triode Q1 is simultaneously connected with a signal VCC _ BAR, the other end of the capacitor C1 is simultaneously connected with the emitter electrode of the triode Q1 and one end of the capacitor C2, the other end of the capacitor C2 is grounded, the emitter electrode of the triode Q1 is grounded through a resistor R2, and the emitter electrode of the triode Q1 is connected with the link impedance optimization circuit.
5. The passive crystal frequency trimming circuit of claim 1, wherein: the link impedance optimization circuit comprises a relay LS1, a low-pass filter and a damping resistance circuit, wherein the low-pass filter consists of a ferrite magnetic ring L1 and a capacitor C5; the relay LS1 is used for selecting a clock signal output channel, the input end of the relay LS1 is connected with the output of the clock circuit, and the output end of the relay LS1 is connected with a damping resistor circuit; and the Relay control signal Relay _ control is controlled by the coprocessor to be output, and the channel selection of the Relay is controlled, wherein one channel is that the input end signal is directly output to the damping resistance circuit, and the other channel is that the input end signal passes through the low-pass filter and then is output to the damping resistance circuit.
6. The passive crystal frequency trimming circuit of claim 5, wherein: the damping resistance circuit comprises a resistor R17 and a resistor R5, one end of the resistor R17 is connected with the output end of the relay LS1, the other end of the resistor R17 is simultaneously connected with the output signal end Clock _ OUT and one end of the resistor R5, and the other end of the resistor R5 is grounded.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110162529.3A CN113225043A (en) | 2021-02-05 | 2021-02-05 | Passive crystal frequency trimming circuit |
| CN2021101625293 | 2021-02-05 |
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| CN202210059258.3A Active CN114499436B (en) | 2021-02-05 | 2022-01-19 | Passive crystal frequency trimming circuit |
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| CN209608625U (en) * | 2019-04-26 | 2019-11-08 | 南京信息职业技术学院 | A kind of crystal filter circuit with frequency compensation automatic regulation function |
| CN110719086A (en) * | 2019-11-19 | 2020-01-21 | 无锡中微爱芯电子有限公司 | Microcontroller for temperature compensation quartz crystal oscillator and use method thereof |
| CN111131964A (en) * | 2019-11-18 | 2020-05-08 | 中山市天键通讯技术有限公司 | RC tuning frequency division circuit adjusted through switch |
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2021
- 2021-02-05 CN CN202110162529.3A patent/CN113225043A/en active Pending
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- 2022-01-19 CN CN202210059258.3A patent/CN114499436B/en active Active
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| US6066989A (en) * | 1998-12-21 | 2000-05-23 | Cts Corporation | Frequency synthesizer module for dual band radio |
| CN101431636A (en) * | 2008-12-04 | 2009-05-13 | 康佳集团股份有限公司 | Television set tuner with clock output |
| CN101860243A (en) * | 2010-05-14 | 2010-10-13 | 西安英洛华微电子有限公司 | Line loss compensation circuit for switch power supply |
| CN103869875A (en) * | 2012-12-11 | 2014-06-18 | 北京普源精电科技有限公司 | Signal generator with clock reference source circuit |
| CN209608625U (en) * | 2019-04-26 | 2019-11-08 | 南京信息职业技术学院 | A kind of crystal filter circuit with frequency compensation automatic regulation function |
| CN111131964A (en) * | 2019-11-18 | 2020-05-08 | 中山市天键通讯技术有限公司 | RC tuning frequency division circuit adjusted through switch |
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| CN113225043A (en) | 2021-08-06 |
| CN114499436B (en) | 2022-11-15 |
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