CN114497219A - 半导体装置 - Google Patents
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Abstract
本公开涉及半导体装置,示例性的半导体装置可以包括:基板;N‑外延层,位于基板上;第一P区域和第二P区域,彼此分开定位在N‑外延层上;第一N+区域,位于第一P区域内;第二N+区域,位于第二P区域内;以及栅极层,位于第一P区域与第二P区域之间。
Description
相关申请的引用
本申请要求于2020年11月13号向韩国知识产权局提交的韩国专利申请第10-2020-0151702号的优先权和权益,其全部内容通过引用结合于此。
技术领域
本公开涉及半导体装置,并且更具体地,涉及用于通过组合沟槽栅极装置和平面栅极装置来提高电流密度的半导体装置。
背景技术
近年来,根据应用装置的大规模和大容量的趋势,出现了对具有高击穿电压、高电流和高速开关特性的功率半导体装置的需要。
这种功率半导体装置特别需要低导通电阻或低饱和电压,以便在允许非常大的电流流动时减少导通状态下的功率损耗。另外,在断开状态或当开关断开时,基本上需要能够承受施加到功率半导体装置的相对端的PN结的反向高电压的特性,即,高击穿电压特性。
在制造功率半导体装置时,根据半导体装置的额定电压确定所使用的原材料的外延区域或漂移区域的浓度和厚度。通过适当地利用PN结结构,通过在PN结的反向偏置模式中适当地分散由耗尽层的扩展引起的电场,半导体与电介质之间的界面处的表面电场的增加得以最小化,并且装置必须被设计成承受功率半导体装置击穿时原材料的固有临界电场,以便获得具有击穿电压理论所需的原材料的浓度和厚度的期望水平的适当击穿电压。
在该背景技术部分中所公开的上述信息仅用于增进对本公开的背景技术的理解,因此,其包括的信息可以不形成本领域普通技术人员已知的现有技术。
发明内容
本公开提供了一种提高电流密度的半导体装置。
示例性半导体装置可以包括:基板;N-外延层,位于基板上;第一P区域和第二P区域,彼此分开定位在N-外延层上;第一N+区域,位于第一P区域内;第二N+区域,位于第二P区域内;以及栅极层,位于第一P区域与第二P区域之间。
第一P区域可以包括位于第一N+区域与栅极层之间的第三P区域。第二P区域可以包括位于第二N+区域与栅极层之间的第四P区域。
栅极层可以包括通过蚀刻第一P区域的一部分和第二P区域的一部分而位于第一N+区域与第二N+区域之间的区域。
栅极层可以包括:第一栅极层,位于第一P区域中的突出的第三P区域和第二P区域中的突出的第四P区域之间;以及第二栅极层,通过蚀刻第一P区域的一部分和第二P区域的一部分而位于第一N+区域与第二N+区域之间。
至于N-外延层,第一栅极层的深度可以低于第二栅极层的深度。
栅极层可以包括第一栅极层,该第一栅极层位于第一P区域中的突出的第三P区域和第二P区域中的突出的第四P区域之间。沟道可以形成于第三P区域的面向第一栅极层的表面中,并且沟道可以形成于第四P区域的面向第一栅极层的表面中。
第一栅极层的宽度可以比第二栅极层的宽度窄。
示例性半导体装置还可包括位于第一P区域与栅极层之间以及第二P区域与栅极层之间的栅极绝缘层。
示例性半导体装置可以包括:基板;N-外延层,位于基板上;多个第一P区域和多个第二P区域,彼此分开地定位在N-外延层上;第一N+区域,定位成邻近于多个第一P区域;第二N+区域,定位成邻近于多个第二P区域;以及多个第一栅极层,位于多个第一P区域与多个第二P区域之间。
示例性半导体装置还可包括连接至多个第一P区域的第三P区域和连接至多个第二P区域的第四P区域。第一N+区域可以位于多个第一P区域与第三P区域之间。第二N+区域可以位于多个第二P区域与第四P区域之间。
示例性半导体装置还可包括位于第三P区域与第四P区域之间的多个第二栅极层。
至于N-外延层,多个第一栅极层的深度可以低于多个第二栅极层的深度。
多个第一栅极层和多个第二栅极层可以交替地定位并且形成为单个。
示例性半导体装置还可包括位于第三P区域与多个第二栅极层之间以及第四P区域与多个第二栅极层之间的栅极绝缘层。
沟道可以形成在多个第一P区域中的面向第一栅极层的表面处,并且沟道可以形成在多个第二P区域中的面向第一栅极层的表面处。
示例性半导体装置还可包括栅极绝缘层,该栅极绝缘层位于多个第一P区域与多个第一栅极层之间以及多个第二P区域与多个第一栅极层之间。
根据按照示例性实施方式的半导体装置,沟道的密度增加以提高电流密度。
附图说明
图1是示出根据示例性实施方式的半导体装置的平面图的示图。
图2示出根据示例性实施方式的半导体装置的平面图,其中,部分地去除了上部。
图3是沿着图1的线A-A'截取的截面图。
图4是沿着图1的线B-B'截取的截面图。
图5是沿着图1的线C-C'截取的截面图。
图6示出在图2的平面图中示出的半导体装置的沟道。
图7是沿着图6的D-D'-D”截取的立体截面图。
图8是沿着图6的线G-G'截取的截面图。
图9是沿着图6的线H-H'截取的截面图。
图10是沿着图6的线I-I'截取的截面图。
图11是沿着图6的线J-J'截取的截面图。
图12示出根据示例性实施方式的半导体装置中的沟道表面和电流的流动。
图13示出用于描述示例性实施方式的比较例。
具体实施方式
本公开涉及半导体装置,并且更具体地,涉及用于通过组合沟槽栅极装置和平面栅极装置来提高电流密度的半导体装置。
在下文中,将参照示出本公开的示例性实施方式的附图更全面地描述本公开。本领域的技术人员将认识到,可通过各种不同的方式来修改所描述的实施方式,这些方式都不背离本发明的精神或范围。
在附图中,为了清楚起见,放大了层、膜、面板、区域等的厚度。在整个说明书中,相同的附图标记表示相同的元件。将理解,当诸如层、膜、区域或基板的元件被称为“在”另一个元件“上”时,该元件可直接在另一个元件上或者也可存在中间元件。相反,当称元件“直接”在另一元件“上”时,不存在中间元件。
在下文中,参照附图详细描述根据示例性实施方式的半导体装置。
图1是示出根据示例性实施方式的半导体装置的平面图的示图。
如图1所示,在半导体装置1的平面图中,由虚线表示的半导体装置1的内部结构可能无法从源电极11看到。
栅极层140(可以是多晶硅层)的顶表面延伸至N+区域111和112,并且具有边界PL1和PL2。栅极层140的一些区域的沟槽位于边界PL3与边界PL4之间。栅极层140的一些其他区域的沟槽位于边界PL5与边界PL6之间。
在下文中,为了更好地理解,参照图2描述示例性实施方式,其中,去除了源电极11、栅极绝缘层130的一部分、以及栅极层140的一部分。
图2示出根据示例性实施方式的半导体装置的平面图,其中,部分地去除了上部。
图3是沿着图1的线A-A'截取的截面图。
图4是沿着图1的线B-B'截取的截面图。
图3线E-E'和和图4的截面图中的F-F'是相同的。图2是示出当从图1中去除线E-E'和F-F'上方的配置时的半导体装置1的俯视平面图。
如图2所示,P区域101和102包括沿着x方向朝向半导体装置1的中心延伸预定宽度w1和w2的突出的P区域103和104,并且突出的P区域103和104可以沿着y方向以规则的间隔y1和y2定位。
如图1至图4所示,半导体装置1包括P区域100、N+区域110、N-外延层120、N基板(N衬底)125、栅极绝缘层130、栅极层140、源电极11和漏电极12。
首先,N基板125定位在漏电极12上,并且N-外延层120定位在N基板125上。彼此间隔开的P区域101和102定位在N-外延层120上。
如图3和图4所示,N+区域111和112定位在P区域101和102上。
如图3所示,栅极层141通过栅极绝缘层130而绝缘,并且定位在两个P区域101和102之间。源电极11可以定位在栅极绝缘层130上。此时,如图3所示,P区域101的宽度比N+区域111的宽度宽,并且从N+区域111的右侧边界延伸预定宽度w1。另外,P区域102的宽度比N+区域112的宽度宽,并且从N+区域112的左侧边界延伸预定宽度w2。
在图4中,栅极层142通过栅极绝缘层130而绝缘,并且定位在P区域101与N+区域111和P区域102与N+区域112之间。源电极11可以定位在栅极绝缘层130上。此时,如图4所示,P区域101的宽度比N+区域111的宽度宽,并且N+区域111的右侧边界与P区域101的右侧边界重合。P区域102的宽度比N+区域112的宽度宽,并且N+区域112的左侧边界与P区域102的左侧边界重合。
如图3和图4所示,根据示例性实施方式的栅极层140包括两种类型的栅极结构。例如,图3所示的栅极层141和图4所示的栅极层142为组合了平坦栅极和沟槽栅极的结构(以下称为组合结构),并且图4所示的沟槽栅极的宽度w4比图3所示的沟槽栅极的宽度w3更宽,以及深度d2比图3所示的沟槽栅极的深度d1更深。
如图2所示,栅极层141和栅极层142沿着y方向交替地定位,并且栅极层141可定位在通过蚀刻位于栅极层142之间的N-外延层120而形成的空间中。即,通过在突出的P区域103与P区域104之间蚀刻N-外延层120来形成沟槽结构的栅极层,并且由此在突出的P区域103与P区域104之间的N-外延层120中不存在JFET区域。然后,去除了由于传统的JFET区域而引起的影响流过沟道的电流流动的区被,因此,可去除电阻,并且可形成附加垂直沟道,从而增大流过沟道的电流。
图5是沿着图1的线C-C'截取的截面图。
如图5所示,栅极层141的沟槽深度d1低于栅极层142的沟槽深度d2。与图5不同,当栅极层141的沟槽深度比栅极层142的沟槽深度深时,电场集中在栅极层141的沟槽的下端,从而降低击穿电压。为了防止这种情况,如图5所示,沟槽深度d1被形成为小于沟槽深度d2,使得电场可分布至出现栅极层的深度阶梯的两个点121和122。
在下文中,参考附图详细描述当导通电平的电压(例如,正电压)施加到栅极层时在P区域与栅绝缘层之间形成的沟道。
图6示出在图2的平面图中示出的半导体装置的沟道。
图7是沿着图6的D-D'-D”截取的立体截面图。
在附图以及图6和图7中,平面栅极沟道由↘方向(即,从左上至右下)的斜线表示,并且沟槽栅极沟道由↙方向(即,从右上至左下)的斜线表示。平面栅极沟道和沟槽栅极沟道可以以预定深度形成到P区域的表面中,并且平面栅极沟道和沟槽栅极沟道是可根据电子的移动方向进行区分的。平面栅极沟道中的电子是沿图7的xy平面流动的电荷,并且沟槽栅极沟道中的电子是沿图7的z方向流动的电荷。
如图6所示,平面栅极沟道形成在多个突出的P区域103和104的上表面中。尽管图6中未示出,但是多个突出的P区域103和104的上表面可以与栅极绝缘层130接触。
在图7中,通过透视方式示出了栅极绝缘层130和栅极层140。这是为了更清楚地示出在P区域中形成的平面栅极沟道和沟槽栅极沟道。
如图7所示,沟槽栅极沟道ch1以预定深度形成在位于N+区域111的下部的P区域101的表面中。在位于N+区域111的下部的P区域101的表面上,在两个突出的P区域105和106之间形成与沟槽栅极沟道ch1相同的沟槽栅极沟道。
在下文中参考图8至图13进一步详细描述平面栅极沟道和沟槽栅极沟道。
图8是沿着图6的线G-G'截取的截面图。
如图8所示,平面栅极沟道ch2以预定深度形成于P区域107的表面中。沟槽栅极沟道ch3形成于两个突出的P区域106和107之间的位于N+区域111的下部的P区域101的表面中。沟槽栅极沟道ch4形成于两个突出的P区域107和103之间的位于N+区域111的下部的P区域101的表面中。
图9是沿着图6的线H-H'截取的截面图。
如图9所示,平面栅极沟道ch5形成在P区域107的表面中。
图10是沿着图6的线I-I'截取的截面图。
如图10所示,平面栅极沟道ch6形成在位于N+区域111与栅极层141之间的突出的P区域105的表面中,并且平面栅极沟道ch7形成于位于N+区域112与栅极层141之间的突出的P区域108的表面中。
图11是沿着图6的线J-J'截取的截面图。
如图11所示,沟槽栅极沟道ch8形成于位于N+区域111的下部达预定深度d3的P区域101的表面中,并且沟槽栅极沟道ch9形成于位于N+区域112的下部达预定深度d4的P区域102的表面中。
因而,在根据示例性实施方式的半导体装置中,图6中在x方向上面向彼此的在突出的P区域(例如,103)与突出的P区域(例如,104)之间的N-外延层120,被蚀刻以形成多晶硅层的栅极层141。然后,在P区域中形成的沟道的宽度增加,并且沟道表面的数量也增加。例如,图9中所示的平面栅极沟道ch5表示增加的沟道表面,并且电流流过沟道ch5。那么,与传统技术不同,电流流过沟道而并不经过JFET区域。因此,根据示例性实施方式的半导体装置,电流可以流向漏电极12而不会因JFET区域的阻抗而减小。
图12示出根据示例性实施方式的半导体装置中的沟道表面和电流的流动。
图13示出用于描述示例性实施方式的比较例。
如图12所示,在P区域107的突出表面中形成四个沟道表面CH1、CH2、CH3和CH4。如从箭头所示的电流的流动所理解的,流过沟道表面CH1的电流沿着沟道表面CH4(即,图12中的z方向)直接流向漏电极12而不经过JFET区域。另外,流过沟道表面CH2和CH3的电流的一部分也沿着沟道表面CH4流向漏电极12。
如图13所示,当示例性实施方式的除栅极层141以外的N-外延层129存在于突出的P区域107在x方向上的前方的空间中时,该空间为JFET区域。
那么,如图13中的虚线所示的电流流过JFET区域,从而电流因JFET区域的阻抗而减小。
尽管已结合目前被考虑为实用示例性实施方式的实施方式描述了该公开,但应理解,该公开并不限于所公开的实施方式。相反,该公开旨在涵盖被包含在所附权利要求的精神和范围内的各种修改和等同布置。
Claims (16)
1.一种半导体装置,包括:
基板;
N-外延层,位于所述基板上;
第一P区域和第二P区域,彼此分开定位在所述N-外延层上;
第一N+区域,位于所述第一P区域内;
第二N+区域,位于所述第二P区域内;以及
栅极层,位于所述第一P区域与所述第二P区域之间。
2.根据权利要求1所述的半导体装置,其中,
所述第一P区域包括位于所述第一N+区域与所述栅极层之间的第三P区域;并且
所述第二P区域包括位于所述第二N+区域与所述栅极层之间的第四P区域。
3.根据权利要求2所述的半导体装置,其中,所述栅极层包括通过蚀刻所述第一P区域的一部分和所述第二P区域的一部分而位于所述第一N+区域与所述第二N+区域之间的区域。
4.根据权利要求1所述的半导体装置,其中,所述栅极层包括:
第一栅极层,位于所述第一P区域中的突出的第三P区域与所述第二P区域中的突出的第四P区域之间;以及
第二栅极层,通过蚀刻所述第一P区域的一部分和所述第二P区域的一部分而位于所述第一N+区域与所述第二N+区域之间。
5.根据权利要求4所述的半导体装置,其中,对于所述N-外延层,所述第一栅极层的深度小于所述第二栅极层的深度。
6.根据权利要求4所述的半导体装置,其中,所述第一栅极层的宽度比所述第二栅极层的宽度窄。
7.根据权利要求1所述的半导体装置,其中,
所述栅极层包括位于所述第一P区域中的突出的第三P区域与所述第二P区域中的突出的第四P区域之间的第一栅极层;并且
沟道形成于所述突出的第三P区域的面向所述第一栅极层的表面中,并且沟道形成于所述突出的第四P区域的面向所述第一栅极层的表面中。
8.根据权利要求1所述的半导体装置,还包括:栅极绝缘层,所述栅极绝缘层位于所述第一P区域与所述栅极层之间以及所述第二P区域与所述栅极层之间。
9.一种半导体装置,包括:
基板;
N-外延层,位于所述基板上;
多个第一P区域和多个第二P区域,在所述N-外延层上所述多个第一P区域和所述多个第二P区域彼此分开定位;
第一N+区域,定位成邻近于所述多个第一P区域;
第二N+区域,定位成邻近于所述多个第二P区域;以及
多个第一栅极层,位于所述多个第一P区域与所述多个第二P区域之间。
10.根据权利要求9所述的半导体装置,还包括:
第三P区域,连接至所述多个第一P区域;以及
第四P区域,连接至所述多个第二P区域,
其中,所述第一N+区域位于所述第三P区域与所述多个第一P区域之间,
其中,所述第二N+区域位于所述第四P区域与所述多个第二P区域之间。
11.根据权利要求10所述的半导体装置,还包括:多个第二栅极层,位于所述第三P区域与所述第四P区域之间。
12.根据权利要求11所述的半导体装置,其中,至于所述N-外延层,所述多个第一栅极层的深度小于所述多个第二栅极层的深度。
13.根据权利要求12所述的半导体装置,其中,所述多个第一栅极层和所述多个第二栅极层交替地定位并且形成为单个。
14.根据权利要求11所述的半导体装置,还包括:栅极绝缘层,位于所述第三P区域与所述多个第二栅极层之间以及所述第四P区域与所述多个第二栅极层之间。
15.根据权利要求9所述的半导体装置,其中,
沟道形成于所述多个第一P区域中的面向所述多个第一栅极层的表面处;并且
沟道形成于所述多个第二P区域中的面向所述多个第一栅极层的表面处。
16.根据权利要求9所述的半导体装置,还包括:栅极绝缘层,所述栅极绝缘层位于所述多个第一P区域与所述多个第一栅极层之间以及所述多个第二P区域与所述多个第一栅极层之间。
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