CN114497112B - Manufacturing method of micro LED display panel and display panel - Google Patents

Manufacturing method of micro LED display panel and display panel Download PDF

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CN114497112B
CN114497112B CN202210324921.8A CN202210324921A CN114497112B CN 114497112 B CN114497112 B CN 114497112B CN 202210324921 A CN202210324921 A CN 202210324921A CN 114497112 B CN114497112 B CN 114497112B
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groove
anode
substrate
epitaxial wafer
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CN114497112A (en
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岳大川
蔡世星
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Shenzhen Aoshi Micro Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0093—Wafer bonding; Removal of the growth substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/58—Optical field-shaping elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0058—Processes relating to semiconductor body packages relating to optical field-shaping elements

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Abstract

The invention discloses a manufacturing method of a MicroLED display panel and the display panel, belonging to the field of MicroLED, wherein the method comprises the steps of transferring a first epitaxial wafer to a fourth substrate, removing the first substrate and exposing a first N layer; bonding the second epitaxial wafer and the second epitaxial wafer in the same direction, arranging an insulating layer between the first P layer and the second N layer, and removing the fourth substrate; arranging a first barrier layer to separate the first multi-quantum well layer into a plurality of first multi-quantum wells, and arranging a contact metal in the first barrier layer; bonding the contact metal and the driving electrode, and removing the second substrate; a second barrier film is provided to partition the second multi-quantum well layer into a plurality of second multi-quantum wells, and a second cathode wiring electrically connected to the second N layer through the second barrier film is provided. The display panel manufactured by the method can emit color light, the two multiple quantum wells are in vertical structures and have the same conduction direction, the driving electrodes are arranged on the same side, and the two multiple quantum wells can be actively driven.

Description

MicroLED display panel manufacturing method and display panel
Technical Field
The invention relates to a manufacturing method of a micro LED display panel and the display panel, and belongs to the field of micro LEDs.
Background
The micro LED is a micro light emitting diode, and the micro LED display technology is a display technology in which a self-luminous micron-sized LED is used as a light emitting pixel unit, and an LED chip is assembled on a driving panel to form a high-density LED array. Due to the characteristics of small size, high integration level, self-luminescence and the like of the micro LED chip, compared with an LCD (liquid crystal display) and an OLED (organic light emitting semiconductor), the micro LED chip has the advantages of brightness, resolution, contrast, energy consumption, service life, response speed, thermal stability and the like in the aspect of display. The size of the used LED chip is in the micron level, which makes the assembly of the LED chip to the driving panel very difficult, and the methods in the prior art include film transfer, laser transfer, electrostatic transfer, electromagnetic transfer, fluid self-assembly, etc., which are microscopically long and high in defect rate because the LED chip is assembled with the driving panel one by one or in batches. The bonding technology can bond the electrodes of two wafers together at one time, contact electrodes on the two wafers can be strictly aligned through graphical etching, the wafer bonding technology is applied to a micro LED in the prior art, the whole LED chip is synchronously assembled on a driving panel, the assembly efficiency of the micro LED panel is greatly improved, but the colorful LED epitaxial wafer is absent in the prior art, only an LED epitaxial wafer with a multiple quantum well is available on the market, and after the wafers are bonded, the bonding surface (namely the LED chip and the driving electrode) cannot be processed; if the N-type gallium nitride, the second multi-quantum well and the P-type gallium nitride are generated on the LED epitaxial wafer with the multi-quantum well through secondary epitaxy, the original multi-quantum well is hidden in the middle of the epitaxial wafer, a large processing depth is needed during processing, and the etching difficulty is great, so that the micro LED panel obtained by wafer bonding in the prior art can only emit light of one color.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention provides a manufacturing method of a micro LED display panel and the display panel, which can emit light in color.
The technical scheme adopted by the invention for solving the technical problems is as follows:
in a first aspect, the invention provides a method for manufacturing a micro led display panel, raw materials used for the method include a first epitaxial wafer, a second epitaxial wafer and a driving panel, the first epitaxial wafer sequentially includes a first substrate, a first N layer, a first multi-quantum well layer and a first P layer from bottom to surface, the second epitaxial wafer sequentially includes a second substrate, a second N layer, a second multi-quantum well layer and a second P layer from bottom to surface, the driving panel includes a third substrate and a driving electrode embedded in the third substrate, and the method includes the following steps:
transferring the first epitaxial wafer to a fourth substrate to remove the first substrate and expose the first N layer to obtain a temporary first epitaxial wafer;
bonding the temporary first epitaxial wafer and the second epitaxial wafer together in the same direction, arranging an insulating layer between the first P layer and the second N layer, and removing the fourth substrate;
providing a first barrier layer to separate the first multi-quantum well layer into a plurality of first multi-quantum wells, and providing a contact metal in the first barrier layer, the contact metal comprising a first anode electrically connected to the first P layer and a second anode electrically connected to the second P layer;
bonding the wafer obtained after the last step with the driving panel, bonding the driving electrode with the contact metal, and removing the second substrate to expose the second N layer;
a second barrier film is provided to partition the second multi-quantum well layer into a plurality of second multi-quantum wells, and a second cathode wiring electrically connected to the second N layer through the second barrier film is provided.
The method for manufacturing the micro LED display panel can be used for manufacturing the micro LED display panel with color display, the conduction directions of the two multi-quantum wells are the same, the driving electrodes are arranged on the same side, and the two multi-quantum wells can be driven actively.
It should be noted that as will be appreciated by those skilled in the art, wafers (wafers) are sheet-like in shape, with only one side of the substrate being available for mounting and only the other side being available for processing relative to the substrate. In this application, unless otherwise specified, orientation descriptions such as "up" and "down" are in a frame of reference with the wafer lying horizontally and the substrate facing down, "surface" refers to the surface on the other side relative to the substrate.
Further, the step of transferring the first epitaxial wafer to a fourth substrate to remove the first substrate and expose the first N layer to obtain a temporary first epitaxial wafer includes:
arranging temporary bonding glue on the surface of the first epitaxial wafer;
adhering a fourth substrate on the temporary bonding glue;
grinding the first substrate until the first N layer is exposed to obtain the temporary first epitaxial wafer;
the step of removing the fourth substrate includes:
and stripping the temporary bonding glue to remove the fourth substrate.
Further, the step of bonding the temporary first epitaxial wafer and the second epitaxial wafer PN junction together in the same direction, and providing an insulating layer between the first P layer and the second N layer includes:
generating a third silicon layer on the surface of the temporary first epitaxial wafer, and generating a second silicon layer on the surface of the second epitaxial wafer;
bonding the third silicon layer and the second silicon layer together face to form the insulating layer.
Before the graphical etching is not carried out, the temporary PN junctions of the first epitaxial wafer and the second epitaxial wafer are bonded together in the same direction through silicon-silicon direct bonding, the alignment requirement is low, any bonding agent and an external electric field are not needed, the process is simple, and the PN junctions are convenient to follow-up layout of metal wires in the same direction.
Further, the step of providing a first barrier layer to separate the first multiple quantum well layer into a plurality of first multiple quantum wells, and providing a contact metal in the first barrier layer includes:
the first multi-quantum well layer is etched in a patterning mode, so that the first multi-quantum well layer is separated into a plurality of first multi-quantum wells, a first separation groove is formed at the position of the first N layer in the etching mode, and a second anode original groove is formed at the position of the insulating layer in the etching mode;
arranging a first blocking layer to fill the first isolating groove and the second anode original groove;
patterning the first barrier layer to form a first anode groove above the first P layer and a second anode groove at a position corresponding to the second anode prototype groove;
disposing the contact metal in the first anode groove and the second anode groove.
Further, the step of providing a first barrier layer to separate the first multiple quantum well layer into a plurality of first multiple quantum wells, and providing a contact metal in the first barrier layer includes:
the first multi-quantum well layer is etched in a patterning mode, so that the first multi-quantum well layer is separated into a plurality of first multi-quantum wells, a first separation groove is formed at the position of the first N layer in the etching mode, and a second anode original groove is formed at the position of the insulating layer in the etching mode;
covering a first barrier film;
patterning the first barrier film to form a first anode half-groove above the first P layer;
disposing a first metal in the first anode half cell;
arranging a first blocking layer to fill the first isolating groove and the second anode original groove;
the first barrier layer is etched in a patterning mode, so that a first anode extending groove is formed above the first anode half groove, and a second anode groove is formed at the position corresponding to the second anode prototype groove;
and a second metal is arranged in the first anode extension tank and the second anode tank, and the second metal in the first anode extension tank is in contact with the first metal.
In the finally manufactured micro LED display panel, the two multiple quantum wells are of a vertical structure, and the first metal can be metal with high reflectivity, such as gold and aluminum, so that light can be emitted; the second metal can be selected from metal with high conductivity, such as copper, so that good electrical performance is ensured after the contact metal and the driving electrode are bonded.
Further, the step of patterning the first barrier film to form a first anode half-trench over the first P layer includes:
the first separation film is etched in a patterning mode, so that a first anode half groove is formed above the first P layer, and a first cathode wiring groove is formed at the bottom of the first separation groove;
the step of disposing a first metal in the first anode half cell comprises:
and arranging a first metal in the first anode half-groove and the first cathode wiring groove.
When the micro LED display panel is electrically connected for a long distance, voltage drop causes uneven voltage and uneven brightness, and the metal wiring for the common cathode is beneficial to the uniform brightness of each sub-pixel of the micro LED display panel.
Further, the step of providing a second barrier film to partition the second multiple quantum well layer into a plurality of second multiple quantum wells, and providing a second cathode wiring electrically connected to the second N layer through the second barrier film includes:
the second multi-quantum well layer is etched in a graphical mode, so that the second multi-quantum well layer is separated into a plurality of second multi-quantum wells;
covering a second barrier film;
the second barrier film is etched in a patterning mode to form a second cathode wiring groove, and the second cathode wiring groove is communicated with the second N layer;
and a second cathode wiring is provided in the second cathode wiring groove.
Further, the step of disposing the second cathode wiring in the second cathode wiring groove further comprises:
covering a third indium tin oxide layer on the surface.
Further, before the step of transferring the first epitaxial wafer to a fourth substrate to remove the first substrate and expose the first N layer, obtaining a temporary first epitaxial wafer, the method further includes the following steps:
and sequentially generating a first indium tin oxide layer and a first silicon layer on the first P layer, and sequentially generating a second indium tin oxide layer and a second silicon layer on the second P layer.
In a second aspect, the invention provides a display panel, which is manufactured by the method for manufacturing the micro led display panel of the first aspect.
Two kinds of multiple quantum wells in the manufactured micro LED display panel are of vertical structures, the conduction directions are the same, the driving electrodes are on the same side, and the two kinds of multiple quantum wells can be driven actively.
The beneficial effects of the invention are: the invention flexibly uses the wafer bonding technology and the mixed bonding technology, firstly transfers the substrate of the epitaxial wafer and then bonds, ensures that PN junctions of two multiple quantum wells are in the same direction, is convenient for arranging metal wires, ensures that the two multiple quantum wells can be actively driven, and respectively emits different color lights, so that the manufactured MicroLED display panel can display color, and the two sides of the wafer can be graphically etched by firstly bonding and then removing the substrate in the manufacturing process, so that the etching depth is shallow, and the process difficulty is lower.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the application. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
Fig. 1 is a flowchart of steps S01 to S1 provided in an embodiment of the present application.
Fig. 2 is a flowchart of steps S20 to S2 provided in the embodiment of the present application.
Fig. 3 is a flowchart of steps S31 to S34 provided in the embodiment of the present application.
Fig. 4 is a flowchart of steps S35 to S37 provided in an embodiment of the present application.
Fig. 5 is a flowchart of step S4 provided in an embodiment of the present application.
Fig. 6 is a flowchart of step S5 provided in the embodiment of the present application.
Fig. 7 is a schematic structural diagram of a micro led display panel according to an embodiment of the present application.
Reference numerals are as follows: 11. a first substrate; 12. a second substrate; 13. a third substrate; 14. a fourth substrate; 141. a temporary bonding glue; 21. a first N layer; 22. a second N layer; 31. a first multiple quantum well; 311. a first multi-quantum well layer; 32. a second multiple quantum well; 321. a second multiple quantum well layer; 41. a first P layer; 42. a second P layer; 51. a first indium tin oxide layer; 52. a second indium tin oxide layer; 53. a third indium tin oxide layer; 611. a first anode half cell; 612. a first anode extension tank; 613. a first cathode wiring groove; 614. a first blocking groove; 621. a second anode original groove; 622. a second anode tank; 68. a cathode ring wiring groove; 681. the cathode ring wire is in an original groove; 691. bonding pad original groove; 69. a bonding pad slot; 71. a first barrier layer; 72. a second barrier film; 73. a first barrier film; 81. a first silicon layer; 82. a second silicon layer; 83. a third silicon layer; 823. an insulating layer; 91. a first metal; 911. a first anode first portion; 912. a first cathode wiring; 913. a first anode second portion; 921. a second anode; 922. a second cathode wiring; 93. a drive electrode; 98. a cathode loop wiring; 981. a cathode ring outer lead; 99. a bonding pad; 991. bond pad outer leads.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
The following disclosure provides many different embodiments or examples for implementing different features of the invention. To simplify the disclosure of the present invention, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
The raw materials used in the application comprise a first epitaxial wafer, a second epitaxial wafer and a driving panel, wherein the first epitaxial wafer sequentially comprises a first substrate, a first N layer, a first multi-quantum well layer and a first P layer from bottom to surface, and the second epitaxial wafer sequentially comprises a second substrate, a second N layer, a second multi-quantum well layer and a second P layer from bottom to surface. The application needs that the luminescent colors of the first multiple quantum well and the second multiple quantum well are different, and various single-color epitaxial wafers can be directly bought on the market. The driving panel comprises a third substrate and a driving electrode embedded in the third substrate, and the driving panel is obtained by photoetching-etching the substrate, depositing metal and performing CMP (chemical mechanical polishing) according to the designed pixel distribution. The first substrate 11 and the second substrate 12 are silicon substrates, the N layer is formed by doping gallium nitride with other elements, the bonding capability of silicon and gallium nitride is poor, and a buffer layer can be arranged between silicon and gallium nitride (in the drawings in the description, the number of layers is large, the buffer layer is omitted for the convenience of identifying each layer, and if the buffer layer is arranged, the buffer layer is arranged between the N layer and the substrate).
Fig. 1 to 6 disclose a method for manufacturing a micro led display panel, comprising the steps of:
s1: the first epitaxial wafer is transferred to the fourth substrate 14 to remove the first substrate 11 and expose the first N layer 21, resulting in a temporary first epitaxial wafer. The temporary first epitaxial wafer is held with the fourth substrate 14 as the side to be processed, i.e. the wafer is inverted.
S2: and bonding the temporary first epitaxial wafer and the second epitaxial wafer together in the same direction, arranging an insulating layer 823 between the first P layer 41 and the second N layer 22, and removing the fourth substrate 14 to obtain the wafer bonded wafer. The wafer bonded chip is fixed by using the second substrate 12 as a face to be processed, i.e. the chip is turned upside down, and a portion originally belonging to the first epitaxial wafer can be processed. The PN junction homodromous reduces the difficulty of subsequent wiring.
S3: a first barrier layer 71 is provided on the wafer-bonded wafer to partition the first multiple quantum well layer 311 into a plurality of first multiple quantum wells 31, and a contact metal including a first anode electrically connected to the first P layer 41 and a second anode 921 electrically connected to the second P layer 42 is provided in the first barrier layer 71.
S4: the wafer bonding die and the driving panel are bonded, so that the driving electrode 93 and the contact metal are bonded (bonding), and the second substrate 12 is removed to expose the second N layer 22, thereby obtaining a hybrid bonding die. The hybrid bonded wafer has the third substrate 13 as the side to be fixed during processing, i.e., the wafer is turned upside down again, and the portion originally belonging to the second epitaxial wafer can be processed.
S5: a second barrier film 72 is provided on the hybrid bonding wafer to partition the second multiple quantum well layer 321 into a plurality of second multiple quantum wells 32, and a second cathode wiring 922 electrically connected to the second N layer 22 through the second barrier film 72 is provided, resulting in a micro led display panel.
The wafer bonding is a process for bonding two unpatterned wafers, and only needs to align notches (notch) of the two wafers (wafers) without aligning a pattern, and then patterning is realized through a series of processes such as photoetching. Hybrid bonding (Hybrid bonding) is a process for bonding two patterned wafers, and the wafers are patterned, so that the precision requirement is higher.
The resulting micro LED display panel includes a driving panel and LED chips. The driving panel includes a third substrate 13 and driving electrodes 93 embedded in the third substrate 13. The LED chip comprises a first light-emitting unit and a second light-emitting unit which are distributed and arrayed according to pixels, the second light-emitting unit is arranged above the first light-emitting unit, the first light-emitting unit and the second light-emitting unit are both of a vertical structure, and the first light-emitting unit and the second light-emitting unit respectively emit light of one color when being conducted. The first light emitting unit includes, in order from top to bottom, a first N layer 21, a first multiple quantum well 31, and a first P layer 41, and in some embodiments, may further include a first ito layer 51. The second light emitting unit includes, in order from top to bottom, a second N layer 22, a second multiple quantum well 32, and a second P layer 42, and in some embodiments, may further include a second ito layer 52. The first light emitting unit is wrapped by the first barrier layer 71, and the second light emitting unit is wrapped by the second barrier film 72. The first barrier layer 71 has a first anode (in the embodiment where ito is disposed between the P layer and the anode) that conducts the first P layer 41 and the driving electrode 93, and a second anode 921 that conducts the second P layer 42 and the driving electrode 93. Second cathode wirings 922 for conducting the second N layers 22 are arranged on the surface of the LED chip. An insulating layer 823 is provided between the first N layer 21 and the second P layer 42.
The manufacturing method of the micro LED display panel flexibly uses a wafer bonding technology and a mixed bonding technology, firstly transfers the substrate of an epitaxial wafer and then bonds, ensures that PN junctions of two multiple quantum wells are in the same direction, is convenient for arranging metal wires, enables the two multiple quantum wells to be capable of being actively driven, and respectively emits different color lights, so that the manufactured micro LED display panel can display in color (non-full color).
The specific steps of step S1 are shown in fig. 1, and include:
s11: a temporary bonding paste 141 is provided on the first epitaxial wafer surface.
S12: the fourth substrate 14 is attached to the temporary bonding paste 141. I.e. the surface of the first epitaxial wafer is bonded to a silicon wafer by the temporary bonding paste 141.
S13: the first substrate 11 is ground until the first N layer 21 is exposed, resulting in a temporary first epitaxial wafer. The grinding means may be CMP (chemical mechanical polishing).
The transfer of the substrate using the temporary bonding paste 141 allows the wafer to be inverted without a high temperature environment.
The specific steps of step S2 are shown in fig. 2, and include:
s20: a third silicon layer 83 is grown on the temporary first epitaxial wafer surface.
S21 (this step may be incorporated into step S01 below, so that S21 is not labeled in FIG. 2 and S01 is labeled): a second silicon layer 82 is grown on the second epitaxial wafer surface.
S22: the third silicon layer 83 and the second silicon layer 82 are bonded together face to face, fusing to form the insulating layer 823. I.e., the second silicon layer 82 and the third silicon layer 83, serve both to insulate the first P layer 41 from the second N layer 22 and to facilitate bonding of the two wafers together using direct silicon-silicon bonding techniques. The temporary PN junctions of the first epitaxial wafer and the second epitaxial wafer are bonded together in the same direction by silicon-silicon direct bonding, the alignment requirement is low, any bonding agent and an external electric field are not needed, and the process is simple. It should be noted that, in fig. 2, the layout adjustment is performed to adapt to the page width, the step sequence is based on the arrow, the position relationship of each step in the figure does not mean that the steps must be performed alternately, but the steps are performed in two paths, and then the two paths of semi-finished products are bonded together.
S23: the temporary bonding paste 141 is peeled off, and the fourth substrate 14 is removed along with the temporary bonding paste 141. Depending on the type of temporary bonding adhesive 141, solvent peeling or thermal peeling may be selected.
Preferably, the step of transferring the first epitaxial wafer to the fourth substrate 14 to remove the first substrate 11 and expose the first N layer 21 to obtain the temporary first epitaxial wafer further comprises:
s01: a first ito layer 51 and a first si layer 81 are sequentially formed on the first P layer 41 (fig. 1), and a second ito layer 52 and a second si layer 82 are sequentially formed on the second P layer 42 (fig. 2). The process for forming the ito layer and si layer may employ CVD (chemical vapor deposition). P-GaN (P-type gallium nitride) has a very high work function (7.5 eV), and in order to form a good P-type ohmic contact, an ITO (indium tin oxide) layer is added in some embodiments, which is beneficial to improving the electrical performance of the device. The first silicon layer 81 is removed in the subsequent process (step S3), and in the scenario of applying the temporary bonding glue 141, the residual glue is not removed, and the residual glue on the first silicon layer 81 is removed together with the etching of the first silicon layer 81 after the temporary bonding glue 141 is stripped. The second silicon layer 82 is used to participate in the generation of the insulating layer 823 in step S2.
Step S3 in some embodiments includes the following specific steps:
and patterning and etching the first multiple quantum well layer 311 to separate the first multiple quantum well layer 311 into multiple first multiple quantum wells 31, wherein a first isolation groove 614 is formed in the patterned and etched position as deep as the first N layer 21, and a second anode prototype groove is formed in the patterned and etched position as deep as the insulation layer 823. It will be understood by those skilled in the art that patterned etching refers to a series of operations of photolithography-etch-resist removal to etch trenches or holes in the wafer.
The first barrier layer 71 is disposed to fill the first isolation groove 614 and the second anode prototype groove. First barrier layer 71 may be silicon oxide formed by CVD or PVD (physical vapor deposition).
The first barrier layer 71 is patterned to form a first anode trench above the first P layer 41, and a second anode trench 622 is formed at a position corresponding to the second anode prototype trench.
Contact metal is provided in the first and second anode grooves 622. The specific means for disposing the contact metal may be PVD (physical vapor deposition), CVD, electroplating, etc., and a metal layer is formed on the wafer surface, and then photo-etched to retain the desired portions and remove the excess portions.
In order to solve the problem that the two types of light emitting units of the finally manufactured display panel are vertical structures, light needs to be reflected, the contact metal is made of metal with high reflectivity, which is favorable for light emission, particularly, the first multiple quantum well 31 is buried in the deep layer of the wafer, reflection needs to be enhanced to enable the brightness to be close to that of the second multiple quantum well 32, and the metal with high reflectivity is slightly poor in conductivity, in other embodiments, the first anode is composed of two parts, the metal with high reflectivity and the metal with high conductivity are respectively selected, and referring to fig. 3 and 4, the specific steps of step S3 include:
s31: and patterning the etched wafer bonding wafer to separate the first mqw layer 311 into a plurality of first mqw layers 31, wherein a first isolation groove 614 is formed at a position where the patterning etching is deep to the first N layer 21, and a second anode prototype groove 621 is formed at a position where the patterning etching is deep to penetrate the insulating layer 823.
S32: the wafer bonded chip is covered with a first barrier film 73. The first barrier film 73 may be silicon oxide. When the film is formed to be thin (5. ANG. -10. ANG.) regardless of metal or oxide, the shape of the film is the same as or very similar to that of the upper surface of the wafer.
S33: the first barrier film 73 is pattern-etched to form a first anode half groove 611 above the first P layer 41. In a preferred embodiment, this step also forms a first cathode wiring groove 613 at the bottom of the first partition groove 614.
S34: a first metal 91 is provided in the first anode half-cell 611 forming a first anode first portion 911. In a preferred embodiment, this step is also performed by disposing the first cathode wiring 912 (also using the first metal 91) in the first cathode wiring groove 613, and voltage drop causes voltage non-uniformity and brightness non-uniformity when the first cathode wiring is electrically connected for a long distance. Specifically, a layer of the first metal 91 is deposited on the surface of the wafer obtained in step S33, and then the first metal 91 is patterned and etched, leaving the first anode first portion 911 and the first cathode wiring 912.
S35: the first barrier layer 71 is disposed to fill the first isolation groove 614 and the second anode prototype groove. When the first barrier layer 71 and the first barrier film 73 are both made of silicon oxide, the first barrier layer 71 and the first barrier film 73 are integrated after the first barrier layer 71 is disposed.
S36: the first barrier layer 71 is patterned to form a first anode extension trench 612 above the corresponding first anode half trench 611 and a second anode trench 622 at a position corresponding to the second anode prototype trench. The first anode extension groove 612 communicates with the first anode half groove 611.
S37: a second metal is disposed in the first anode extension groove 612 and the second anode groove 622 to form a first anode second portion 913 and a second anode 921, respectively, and the second metal in the first anode extension groove 612 is in contact with the first metal 91. The first anode second portion 913 and the first anode first portion 911 contact to form a first anode, which is composed of two metals. The second metal is provided by depositing the metal by PVD, CVD, or electroplating until the second metal is higher than the first anode extension groove 612 and the second anode groove 622, and then CMP until the highest point of the first anode extension groove 612 and the second anode groove 622 is level with the second metal.
The first metal 91 can be made of metal with high reflectivity, such as gold and aluminum, which is beneficial to light extraction; the second metal can be selected from a metal with high conductivity, such as copper, so that the electrical property is good after the contact metal and the driving electrode 93 are bonded, and the advantages of the contact metal and the driving electrode are combined, so that the first multiple quantum well 31 can emit light with sufficient brightness.
Referring to fig. 6, the specific step of step S5 includes:
s51: the hybrid bond wafer is patterned to isolate second multiple quantum well 32 into a plurality of second multiple quantum wells 32.
S52: covered with a second barrier film 72. The second barrier film 72 may be silicon oxide.
S53: the second barrier film 72 is pattern-etched to form a second cathode wiring trench, which is in communication with the second N layer 22.
S54: a second cathode wiring 922 is provided in the second cathode wiring groove.
In some embodiments, step S55 may also be included after step S54.
S55: the surface is covered with a third ito layer 53. The third ito layer 53 can increase light emission and conduct the second N layer 22 of the second light emitting unit, so that the second light emitting unit shares a cathode.
In more specific implementation steps, a cathode ring outer lead (cathode) and a bonding pad (bonding pad) located at the edge of the display panel are also required to be manufactured on the display panel. In step S31, when the wafer bonded chip is patterned and etched, the edge of the wafer bonded chip is etched to reach the insulating layer 823 or penetrate the insulating layer 823, so as to form the cathode loop wiring original groove 681 and the bonding pad original groove 691. It should be noted that the cathode ring outer lead and the bonding pad do not need to emit light, and therefore, in step S33, the first barrier film 73 at these two places may be etched away or may remain; in step S34, there is no need to retain metal in these two places. In step S36, when the first barrier layer 71 is patterned, the cathode ring wire groove 68 is formed at a position corresponding to the cathode ring wire groove 681, and the bond pad groove 69 is formed at a position corresponding to the bond pad groove 691. The insulation is realized by arranging the first barrier layer 71 on the inner side walls of the cathode ring wire original groove 681 and the bonding pad original groove 691. In step S37, a second metal having high conductivity is deposited in the cathode loop wiring groove 68 and the bonding pad groove 69 to form a cathode loop wiring 98 and a bonding pad 99. In step S51, the hybrid bond wafer is patterned, etched over the corresponding cathode wire groove 68 to expose the second metal, and etched over the corresponding bond pad groove 69 to expose the second metal. In step S53, the second barrier film 72 is pattern-etched over the corresponding cathode wiring groove 68 to expose the second metal, and over the corresponding bond pad groove 69 to expose the second metal. In step S54, a layer of the first metal 91 or the second metal is deposited, and then photo-etched, leaving the second cathode wiring 922 over the second N layer 22, the cathode ring outer lead 981 over the cathode ring wire 98, and the bond pad outer lead 991 over the bond pad 99.
In the description of the present specification, reference to the terms "one embodiment," "certain embodiments," "an illustrative embodiment," "an example," "a specific example," or "some examples" or the like means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention.

Claims (10)

1. A manufacturing method of a MicroLED display panel is characterized in that raw materials used in the manufacturing method comprise a first epitaxial wafer, a second epitaxial wafer and a driving panel, the first epitaxial wafer sequentially comprises a first substrate, a first N layer, a first multi-quantum well layer and a first P layer from bottom to surface, the second epitaxial wafer sequentially comprises a second substrate, a second N layer, a second multi-quantum well layer and a second P layer from bottom to surface, the driving panel comprises a third substrate and a driving electrode embedded in the third substrate, and the method comprises the following steps:
transferring the first epitaxial wafer to a fourth substrate to remove the first substrate and expose the first N layer to obtain a temporary first epitaxial wafer;
bonding the temporary first epitaxial wafer and the second epitaxial wafer together in the same direction, arranging an insulating layer between the first P layer and the second N layer, and removing the fourth substrate;
providing a first barrier layer to separate the first multi-quantum well layer into a plurality of first multi-quantum wells, and providing a contact metal in the first barrier layer, the contact metal comprising a first anode electrically connected to the first P layer and a second anode electrically connected to the second P layer;
bonding the driving electrode and the contact metal with the driving panel, and removing the second substrate to expose the second N layer;
a second barrier film is provided to partition the second multi-quantum well layer into a plurality of second multi-quantum wells, and a second cathode wiring electrically connected to the second N layer through the second barrier film is provided.
2. A method of fabricating a micro led display panel according to claim 1, wherein the step of transferring the first epitaxial wafer to a fourth substrate to remove the first substrate and expose the first N layer to obtain a temporary first epitaxial wafer comprises:
arranging temporary bonding glue on the surface of the first epitaxial wafer;
adhering a fourth substrate on the temporary bonding glue;
grinding the first substrate until the first N layer is exposed to obtain the temporary first epitaxial wafer;
the step of removing the fourth substrate includes:
and stripping the temporary bonding glue to remove the fourth substrate.
3. A method of fabricating a micro led display panel according to claim 1, wherein said step of co-directionally bonding said temporary first and second epitaxial wafers together with PN junctions and providing an insulating layer between said first P layer and said second N layer comprises:
generating a third silicon layer on the surface of the temporary first epitaxial wafer, and generating a second silicon layer on the surface of the second epitaxial wafer;
bonding the third silicon layer and the second silicon layer together face to form the insulating layer.
4. A method of fabricating a micro led display panel according to claim 1, wherein the step of providing a first barrier layer to separate the first multiple quantum well layer into a plurality of first multiple quantum wells, and providing a contact metal in the first barrier layer includes:
the first multi-quantum well layer is subjected to graphical etching to enable the first multi-quantum well layer to be partitioned into a plurality of first multi-quantum wells, wherein a first isolation groove is formed at the position where the graphical etching is deep to the first N layer, and a second anode original groove is formed at the position where the graphical etching is deep to penetrate through the insulating layer;
arranging a first blocking layer to fill the first isolating groove and the second anode original groove;
the first barrier layer is etched in a patterning mode, so that a first anode groove is formed above the first P layer, and a second anode groove is formed in the position corresponding to the second anode prototype groove;
disposing the contact metal in the first anode groove and the second anode groove.
5. A method of fabricating a micro led display panel according to claim 1, wherein the step of providing a first barrier layer to separate the first multiple quantum well layer into a plurality of first multiple quantum wells, and providing a contact metal in the first barrier layer includes:
the first multi-quantum well layer is subjected to graphical etching to enable the first multi-quantum well layer to be partitioned into a plurality of first multi-quantum wells, wherein a first isolation groove is formed at the position where the graphical etching is deep to the first N layer, and a second anode original groove is formed at the position where the graphical etching is deep to penetrate through the insulating layer;
covering a first barrier film;
patterning the first barrier film to form a first anode half-groove above the first P layer;
disposing a first metal in the first anode half cell;
arranging a first blocking layer to fill the first isolating groove and the second anode original groove;
patterning the first barrier layer to form a first anode extension groove above the first anode half groove, and forming a second anode groove at a position corresponding to the second anode prototype groove;
and a second metal is arranged in the first anode extension tank and the second anode tank, and the second metal in the first anode extension tank is in contact with the first metal.
6. A method of fabricating a MicroLED display panel in accordance with claim 5, wherein said step of patternwise etching the first barrier film to form a first anode half-tub over the first P layer comprises:
the first barrier film is etched in a patterned mode, so that a first anode half groove is formed above the first P layer, and a first cathode wiring groove is formed at the bottom of the first barrier groove;
the step of disposing a first metal in the first anode half cell comprises:
and arranging a first metal in the first anode half-groove and the first cathode wiring groove.
7. A method of fabricating a micro led display panel according to claim 1, wherein the step of providing a second barrier film to separate the second multiple quantum well layer into a plurality of second multiple quantum wells, and providing a second cathode wire electrically connected to the second N layer through the second barrier film comprises:
the second multi-quantum well layer is etched in a graphical mode, so that the second multi-quantum well layer is separated into a plurality of second multi-quantum wells;
covering a second barrier film;
the second barrier film is etched in a patterning mode to form a second cathode wiring groove, and the second cathode wiring groove is communicated with the second N layer;
and a second cathode wiring is provided in the second cathode wiring groove.
8. A method for fabricating a MicroLED display panel according to claim 7, wherein the step of providing a second cathode line in said second cathode line groove further comprises:
and covering a third indium tin oxide layer on the surfaces of the second barrier film and the second cathode wiring.
9. A method of fabricating a micro led display panel according to claim 1, wherein said transferring said first epitaxial wafer to a fourth substrate to remove said first substrate and expose said first N layer further comprises the steps of:
and sequentially generating a first indium tin oxide layer and a first silicon layer on the first P layer, and sequentially generating a second indium tin oxide layer and a second silicon layer on the second P layer.
10. A display panel, characterized by being made by the method for making a micro led display panel according to any one of claims 1 to 9.
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