CN114495785A

CN114495785A - GOA unit, driving method thereof, GOA circuit and display device

Info

Publication number: CN114495785A
Application number: CN202011271302.4A
Authority: CN
Inventors: 汪祥; 邵秀晨; 唐如稳; 马俊才; 汤洋
Original assignee: BOE Technology Group Co Ltd; Hefei BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei BOE Optoelectronics Technology Co Ltd
Priority date: 2020-11-13
Filing date: 2020-11-13
Publication date: 2022-05-13

Abstract

The invention provides a GOA unit, a driving method thereof, a GOA circuit and a display device, and relates to the technical field of display. An input module in a GOA unit is connected with an input signal end and a pull-up node, an output control module is connected with the pull-up node, a first clock signal end and an output control node, the output module comprises a plurality of output sub-modules, each output sub-module is connected with the output control node, a second clock signal end and an output signal end which are connected with each output sub-module are different, a reset module is connected with the pull-up node, a reset signal end and a first level signal end, a pull-down control module is connected with the pull-up node, a second level signal end, a pull-down node and the first level signal end, and the pull-down module is connected with the pull-down node, the pull-up node, the output control node, each output signal end and the first level signal end. The number of the GOA units is reduced by controlling a plurality of output signal ends through one GOA unit so as to realize narrow-frame display.

Description

GOA unit, driving method thereof, GOA circuit and display device

Technical Field

The present invention relates to the field of display technologies, and in particular, to a GOA unit, a driving method thereof, a GOA circuit, and a display device.

Background

With the development of the display industry, display devices with narrow frames are becoming more popular, and in order to realize a display substrate with narrow frames, Gate Driver on Array (GOA) units are usually used to replace the original Gate Driver chips.

At present, the frame of the display device can be reduced to a certain extent by adopting the GOA unit to replace the original gate driving chip, but when the frame of the display device needs to be further reduced to obtain the display device with an ultra-narrow frame, the size of the GOA unit is reduced by reducing the size of the transistor and the size of the storage capacitor in the GOA unit in the prior art, so that the display device with the ultra-narrow frame is obtained.

In the prior art, the stability of the whole GOA unit is deteriorated and the service life is shortened after the size of a transistor and the size of a capacitor in the GOA unit are reduced.

Disclosure of Invention

The invention provides a GOA unit, a driving method thereof, a GOA circuit and a display device, and aims to solve the problem that the stability of the GOA unit is poor when an ultra-narrow frame is realized by reducing the size of a transistor and the size of a storage capacitor in the GOA unit.

In order to solve the above problem, the present invention discloses a GOA unit, comprising: the device comprises an input module, an output control module, an output module, a reset module, a pull-down control module, a pull-down module and a storage module;

the input module is respectively connected with an input signal end and a pull-up node and is configured to pull up the potential of the pull-up node under the control of the input signal end;

the output control module is respectively connected with the pull-up node, the first clock signal end and the output control node, and is configured to transmit a first clock signal provided by the first clock signal end to the output control node under the control of the pull-up node;

the output module comprises a plurality of output sub-modules, each output sub-module is respectively connected with the output control node, a second clock signal end and an output signal end, and is configured to transmit a second clock signal provided by the second clock signal end to the output signal end under the control of the output control node; the second clock signal end and the output signal end which are connected with any two output sub-modules are different;

the reset module is respectively connected with the pull-up node, a reset signal end and a first level signal end and is configured to reset the pull-up node under the control of the reset signal end;

the pull-down control module is respectively connected with the pull-up node, a second level signal end, a pull-down node and the first level signal end, and is configured to control the potential of the pull-down node under the control of the second level signal end and the pull-up node;

the pull-down module is respectively connected with the pull-down node, the pull-up node, the output control node, each output signal end and the first level signal end, and is configured to pull down the potentials of the pull-up node, the output control node and each output signal end under the control of the pull-down node;

the storage module is connected with the pull-up node and the output control node respectively and is configured to maintain the potential of the pull-up node.

Optionally, the input module includes a first transistor;

and the grid electrode and the first electrode of the first transistor are both connected with the input signal end, and the second electrode of the first transistor is connected with the pull-up node.

Optionally, the output control module includes a second transistor;

the grid electrode of the second transistor is connected with the pull-up node, the first pole of the second transistor is connected with the first clock signal end, and the second pole of the second transistor is connected with the output control node.

Optionally, the output module includes a first output sub-module, a second output sub-module, a third output sub-module, and a fourth output sub-module;

the first output sub-module comprises a third transistor; a grid electrode of the third transistor is connected with the output control node, a first pole of the third transistor is connected with a second clock signal end corresponding to the first output submodule, and a second pole of the third transistor is connected with an output signal end corresponding to the first output submodule;

the second output sub-module comprises a fourth transistor; a grid electrode of the fourth transistor is connected with the output control node, a first pole of the fourth transistor is connected with a second clock signal end corresponding to the second output sub-module, and a second pole of the fourth transistor is connected with an output signal end corresponding to the second output sub-module;

the third output sub-module comprises a fifth transistor; a grid electrode of the fifth transistor is connected with the output control node, a first pole of the fifth transistor is connected with a second clock signal end corresponding to the third output sub-module, and a second pole of the fifth transistor is connected with an output signal end corresponding to the third output sub-module;

the fourth output sub-module comprises a sixth transistor; the grid electrode of the sixth transistor is connected with the output control node, the first pole of the sixth transistor is connected with the second clock signal end corresponding to the fourth output sub-module, and the second pole of the sixth transistor is connected with the output signal end corresponding to the fourth output sub-module.

Optionally, the reset module includes a seventh transistor;

a gate of the seventh transistor is connected to the reset signal terminal, a first pole of the seventh transistor is connected to the pull-up node, and a second pole of the seventh transistor is connected to the first level signal terminal.

Optionally, the pull-down control module includes an eighth transistor, a ninth transistor, a tenth transistor, and an eleventh transistor;

a gate and a first pole of the eighth transistor are both connected with the second level signal end, and a second pole of the eighth transistor is connected with a gate of the ninth transistor;

a first pole of the ninth transistor is connected with the second level signal end, and a second pole of the ninth transistor is connected with the pull-down node;

a gate of the tenth transistor is connected to the pull-up node, a first pole of the tenth transistor is connected to a gate of the ninth transistor, and a second pole of the tenth transistor is connected to the first level signal terminal;

a gate of the eleventh transistor is connected to the pull-up node, a first pole of the eleventh transistor is connected to the pull-down node, and a second pole of the eleventh transistor is connected to the first level signal terminal.

Optionally, the pull-down module includes a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, and a seventeenth transistor;

a gate of the twelfth transistor is connected to the pull-down node, a first pole of the twelfth transistor is connected to the pull-up node, and a second pole of the twelfth transistor is connected to the first level signal terminal;

a gate of the thirteenth transistor is connected to the pull-down node, a first pole of the thirteenth transistor is connected to the output control node, and a second pole of the thirteenth transistor is connected to the first level signal terminal;

a gate of the fourteenth transistor is connected to the pull-down node, a first pole of the fourteenth transistor is connected to an output signal terminal corresponding to the first output submodule, and a second pole of the fourteenth transistor is connected to the first level signal terminal;

a gate of the fifteenth transistor is connected with the pull-down node, a first pole of the fifteenth transistor is connected with an output signal end corresponding to the second output submodule, and a second pole of the fifteenth transistor is connected with the first level signal end;

a gate of the sixteenth transistor is connected with the pull-down node, a first pole of the sixteenth transistor is connected with an output signal end corresponding to the third output submodule, and a second pole of the sixteenth transistor is connected with the first level signal end;

the gate of the seventeenth transistor is connected to the pull-down node, the first pole of the seventeenth transistor is connected to the output signal terminal corresponding to the fourth output sub-module, and the second pole of the seventeenth transistor is connected to the first level signal terminal.

Optionally, the storage module includes a storage capacitor;

the first end of the storage capacitor is connected with the pull-up node, and the second end of the storage capacitor is connected with the output control node.

Optionally, the GOA unit further includes an initialization module; the initialization module is respectively connected with the input signal end, each output signal end and the first level signal end, and is configured to initialize each output signal end under the control of the input signal end.

Optionally, the initialization module includes an eighteenth transistor, a nineteenth transistor, a twentieth transistor, and a twenty-first transistor;

the grid electrode of the eighteenth transistor is connected with the input signal end, the first pole of the eighteenth transistor is connected with the output signal end corresponding to the first output submodule, and the second pole of the eighteenth transistor is connected with the first level signal end;

the gate of the nineteenth transistor is connected with the input signal end, the first pole of the nineteenth transistor is connected with the output signal end corresponding to the second output submodule, and the second pole of the nineteenth transistor is connected with the first level signal end;

a gate of the twentieth transistor is connected to the input signal terminal, a first pole of the twentieth transistor is connected to an output signal terminal corresponding to the third output submodule, and a second pole of the twentieth transistor is connected to the first level signal terminal;

the grid electrode of the twenty-first transistor is connected with the input signal end, the first pole of the twenty-first transistor is connected with the output signal end corresponding to the fourth output submodule, and the second pole of the twenty-first transistor is connected with the first level signal end.

In order to solve the above problems, the present invention further discloses a GOA circuit, which includes a plurality of cascaded GOA units;

except the first-stage GOA unit, the input signal end of each stage of GOA unit is connected with the output control node of the previous-stage GOA unit; except for the last GOA unit, the reset signal end of each GOA unit is connected with the output control node of the next GOA unit.

In order to solve the above problem, the present invention further discloses a display device including the above GOA circuit.

In order to solve the above problem, the present invention further discloses a driving method of a GOA unit, which is applied to driving the above GOA unit, and the method includes:

in the first stage, an input module pulls up the potential of a pull-up node under the control of an input signal end and charges a storage module;

in the second stage, the output control module transmits the first clock signal provided by the first clock signal end to the output control node under the control of the pull-up node, so that each output submodule in the output module transmits the second clock signal provided by the corresponding second clock signal end to each output signal end; in the second stage, the second clock signals provided by the second clock signal terminals connected with the output sub-modules are effective signals in sequence;

in the third stage, the reset module resets the pull-up node under the control of the reset signal end, so that the pull-down control module pulls up the potential of the pull-down node, and further pulls down the potentials of the pull-up node, the output control node and each output signal end through the pull-down module;

and in the fourth stage, the pull-down control module continues to pull up the potential of the pull-down node under the control of a second level signal end and the pull-up node, so that the pull-down module continues to pull down the potentials of the pull-up node, the output control node and each output signal end.

Compared with the prior art, the invention has the following advantages:

in the embodiment of the invention, an input module, an output control module, an output module, a reset module, a pull-down control module, a pull-down module and a storage module are arranged in a GOA unit; the input module is respectively connected with the input signal end and the pull-up node; the output control module is respectively connected with the pull-up node, the first clock signal end and the output control node; the output module comprises a plurality of output sub-modules, each output sub-module is respectively connected with an output control node, a second clock signal end and an output signal end, and the second clock signal end and the output signal end which are connected with any two output sub-modules are different; the reset module is respectively connected with the pull-up node, the reset signal end and the first level signal end; the pull-down control module is respectively connected with the pull-up node, the second level signal end, the pull-down node and the first level signal end; the pull-down module is respectively connected with the pull-down node, the pull-up node, the output control node, each output signal end and the first level signal end; the storage module is respectively connected with the pull-up node and the output control node. By arranging a plurality of output sub-modules in the output module, and respectively connecting different second clock signal terminals and different output signal terminals to any two output sub-modules, one GOA unit is connected with a plurality of output signal terminals, and each output signal terminal controls a row of grid scanning signal lines, so that one GOA unit can control a plurality of rows of grid scanning signal lines, thereby reducing the number of GOA units arranged in the display device, and more space can be used for arranging transistors and storage capacitors in the GOA unit in the column direction of the display device, so that the size of the GOA unit in the row direction of the display device can be reduced, further the frame size of the display device can be reduced, and simultaneously, because enough space can be distributed in the column direction of the display device, the sizes of the transistors and the storage capacitors in the GOA unit are not required to be reduced, therefore, the frame size of the display device can be reduced, and the stability of the GOA unit can be guaranteed.

Drawings

Fig. 1 shows a schematic diagram of a GOA unit in accordance with an embodiment of the present invention;

fig. 2 shows a timing diagram of the operation of a GOA unit according to an embodiment of the present invention;

fig. 3 shows a circuit diagram of a GOA unit in accordance with an embodiment of the present invention;

FIG. 4 is a state diagram of the transistors in the GOA unit in the first stage during one frame time according to the embodiment of the present invention;

FIG. 5 is a state diagram of the transistors in the second stage GOA unit during one frame time according to the embodiment of the present invention;

FIG. 6 is a schematic diagram illustrating operation of the display apparatus when a first output sub-module outputs a valid signal according to an embodiment of the present invention;

FIG. 7 is a schematic diagram illustrating operation of the display apparatus when a second output sub-module outputs a valid signal according to the embodiment of the present invention;

FIG. 8 is a schematic diagram showing the operation of the display apparatus when a third output sub-module outputs a valid signal according to the embodiment of the present invention;

FIG. 9 is a schematic diagram showing the operation of the display apparatus when a fourth output sub-module outputs a valid signal according to the embodiment of the present invention;

FIG. 10 is a state diagram of the transistors in the third-stage GOA unit during a frame time according to the embodiment of the present invention;

FIG. 11 is a state diagram of the transistors in the GOA unit in the fourth stage during one frame time according to the embodiment of the present invention;

FIG. 12 shows a schematic diagram of another GOA unit in accordance with embodiments of the present invention;

fig. 13 shows a circuit diagram of another GOA unit in accordance with an embodiment of the present invention;

fig. 14 shows a circuit diagram of a GOA circuit of an embodiment of the present invention;

fig. 15 is a schematic diagram illustrating the operation of the display device when a plurality of cascaded GOA units operate sequentially according to the embodiment of the present invention.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.

Example one

Referring to fig. 1, a schematic diagram of a GOA unit module according to an embodiment of the present invention is shown.

The embodiment of the invention provides a GOA unit, which comprises: the device comprises an input module 11, an output control module 12, an output module 13, a reset module 14, a pull-down control module 15, a pull-down module 16 and a storage module 17.

The Input module 11 is connected to the Input signal terminal Input and the pull-up node PU, and configured to pull up a potential of the pull-up node PU under the control of the Input signal terminal Input.

The output control module 12 is connected to the pull-up node PU, the first clock signal terminal CLKx, and the output control node K, respectively, and configured to transmit the first clock signal provided by the first clock signal terminal CLKx to the output control node K under the control of the pull-up node PU.

The output module 13 includes a plurality of output sub-modules, each of which is respectively connected to the output control node K, the second clock signal terminal, and the output signal terminal, and is configured to transmit the second clock signal provided by the second clock signal terminal to the output signal terminal under the control of the output control node K; the second clock signal end and the output signal end which are connected with any two output sub-modules are different.

The Reset module 14 is connected to the pull-up node PU, the Reset signal terminal Reset, and the first level signal terminal VGL, and configured to Reset the pull-up node PU under the control of the Reset signal terminal Reset.

The pull-down control module 15 is connected to the pull-up node PU, the second level signal terminal VGH, the pull-down node PD, and the first level signal terminal VGL, and configured to control the potential of the pull-down node PD under the control of the second level signal terminal VGH and the pull-up node PU.

The pull-down module 16 is connected to the pull-down node PD, the pull-up node PU, the output control node K, each output signal terminal, and the first level signal terminal VGL, and configured to pull down potentials of the pull-up node PU, the output control node K, and each output signal terminal under the control of the pull-down node PD.

The memory module 17 is connected to the pull-up node PU and the output control node K, respectively, and configured to hold a potential of the pull-up node PU.

In the embodiment of the present invention, the output module 13 includes a plurality of output sub-modules, for example, as shown in fig. 1, the output sub-module 13 includes a first output sub-module, a second output sub-module, to an nth output sub-module, where N is a positive integer greater than 1, specifically, the first output sub-module is connected to an output control node K, a second clock signal terminal CLKA, and an output signal terminal Out a, the second output sub-module is connected to the output control node K, the second clock signal terminal CLKB, and the output signal terminal Out B, and so on, the nth output sub-module is connected to the output control node K, the second clock signal CLKN, and the output signal terminal Out N. The second clock signal terminal CLKA, the second clock signal terminal CLKB, to the second clock signal terminal CLKN are different second clock signal terminals, and the output signal terminal Out a, the output signal terminal Out B, to the output signal terminal Out N are also different output signal terminals, so different output sub-modules are connected to different second clock signal terminals and different output signal terminals, so that a plurality of output signal terminals can be controlled by one GOA unit, each output signal terminal is correspondingly connected to one row of gate scanning signal lines, and therefore, one GOA unit can control a plurality of rows of gate scanning signal lines.

The pull-down module 16 is connected to the output signal terminal Out a, the output signal terminal Out B, and the output signal terminal Out N, respectively.

Referring to fig. 2, an operation timing diagram of a GOA unit according to an embodiment of the present invention is shown, and an operation process of the GOA unit shown in fig. 1 is described below with reference to fig. 2, where the output module 13 includes four output sub-modules to describe a specific driving process, and the four output sub-modules included in the output module 13 are a first output sub-module, a second output sub-module, a third output sub-module, and a fourth output sub-module, respectively.

In the actual driving process, a display period T1 and an idle period T2 are included in one frame period. The idle period T2 refers to a period from the completion of scanning of the last row of gate scanning signal lines in one frame to the start of scanning of the first row of gate scanning signal lines in the next frame.

In the first stage, the input module pulls up the potential of the pull-up node under the control of the input signal end, and charges the storage module.

In the first stage T1 of the display stage T1, the Input signal from the Input signal terminal is an active signal, and the first clock signal from the CLKx terminal and the Reset signal from the Reset signal terminal Reset are both inactive signals; the Input module 11 is turned on under the control of an Input signal Input from the Input signal terminal Input, so as to pull up the potential of the pull-up node PU, and charge the memory module 17. At this time, the output control module 12 is turned on under the action of the pull-up node PU, but since the first clock signal input by the first clock signal terminal CLKx is an invalid signal, the output control node K is at a low level, so that each output sub-module in the output module 13 is turned off; in addition, the reset module 14 is also in an off state, and the pull-down control module 15 is turned on under the control of the pull-up node PU and the second level signal terminal VGH, so that the pull-down node PD is at a low level, and further controls the pull-down module 16 to be in the off state.

In the second stage, the output control module transmits the first clock signal provided by the first clock signal end to the output control node under the control of the pull-up node, so that each output submodule in the output module transmits the second clock signal provided by the corresponding second clock signal end to each output signal end; in the second stage, the second clock signals provided by the second clock signal terminals connected to the output submodules are effective signals in sequence.

In the second stage T2 of the display stage T1, the first clock signal inputted from the first clock signal terminal CLKx is an active signal, and the Input signal inputted from the Input signal terminal and the Reset signal inputted from the Reset signal terminal Reset are both inactive signals; at the second stage t2, the memory module 17 discharges to keep the potential of the pull-up node PU at a high potential, the output control module 12 continues to be in a conducting state under the control of the pull-up node PU, the output control module 12 transmits the first clock signal provided by the first clock signal terminal CLKx to the output control node K, since the first clock signal provided by the first clock signal terminal CLKx is an active signal, the potential of the output control node K is pulled up, the output control node K controls the conduction of the plurality of output sub-modules connected thereto, the output sub-modules transmit the second clock signal input by the second clock signal terminals connected thereto to the output signal terminals corresponding to the output sub-modules, and the second clock signal terminals connected to different output sub-modules are different, therefore, the output signals output by the output signal terminals corresponding to different output sub-modules are also different, and the second clock signals provided by the second clock signal terminals connected to each output sub-module are sequentially active, therefore, different output signal ends can be sequentially controlled by different output sub-modules.

Specifically, when N is equal to 4, under the condition that the potential of the output control node K is pulled high, the first output sub-module, the second output sub-module, the third output sub-module and the fourth output sub-module are all turned on, when the second clock signal input by the second clock signal terminal CLKA connected with the first output sub-module is an effective signal, and the second clock signal input by the second clock signal terminal CLKB connected with the second output sub-module, the second clock signal terminal CLKC connected with the third output sub-module and the second clock signal input by the second clock signal terminal CLKD connected with the fourth output sub-module are all invalid signals, the output signal terminal Out a outputs a high level signal, and the output signal terminals Out B, Out C and Out D all output low level signals; when a second clock signal input by a second clock signal terminal CLKB connected with the second output submodule is an effective signal and second clock signals input by a second clock signal terminal CLKA connected with the first output submodule, a second clock signal terminal CLKC connected with the third output submodule and a second clock signal terminal CLKD connected with the fourth output submodule are invalid signals, an output signal terminal Out B outputs a high-level signal, and an output signal terminal Out A, an output signal terminal Out C and an output signal terminal Out D all output low-level signals; when a second clock signal input by a second clock signal terminal CLKC connected with the third output sub-module is an effective signal and second clock signals input by a second clock signal terminal CLKA connected with the first output sub-module, a second clock signal terminal CLKB connected with the second output sub-module and a second clock signal terminal CLKD connected with the fourth output sub-module are invalid signals, an output signal terminal Out C outputs a high-level signal, and an output signal terminal Out A, an output signal terminal Out B and an output signal terminal Out D all output low-level signals; when a second clock signal input by a second clock signal terminal CLKD connected with the fourth output submodule is an effective signal and second clock signals input by a second clock signal terminal CLKA connected with the first output submodule, a second clock signal terminal CLKB connected with the second output submodule and a second clock signal terminal CLKC connected with the third output submodule are both invalid signals, the output signal terminal Out D outputs a high-level signal, and the output signal terminal Out A, the output signal terminal Out B and the output signal terminal Out C all output low-level signals.

Because the output module 13 in one GOA unit includes multiple output submodules, one GOA unit can control multiple output signal terminals, the number of output submodules included in the output module 13 is greater than or equal to 2, and the number of output submodules can be determined according to specific practical situations, which is not limited in the present invention.

In addition, if the Input signal Input by the Input signal terminal is an invalid signal, the Input module 11 is turned off, and the Reset signals Input by the Reset signal terminal Reset are both invalid signals, the Reset module 14 is turned off, and is controlled by the pull-up node PU and the second level signal terminal VGH, the pull-down control module 15 is turned on, the pull-down control module 15 pulls down the potential of the pull-down node PD, and the pull-down module 16 is turned off because the potential of the pull-down node PD is pulled down.

And in the third stage, the reset module resets the pull-up node under the control of the reset signal end, so that the pull-down control module pulls up the potential of the pull-down node, and then pulls down the potentials of the pull-up node, the output control node and each output signal end through the pull-down module.

In the third stage T3 of the display stage T1, the Reset signal Input from the Reset signal terminal Reset is an active signal, and the Input signal Input from the Input signal terminal and the first clock signal Input from the first clock signal terminal CLKx are both inactive signals. Reset module 14 switches on under the control of the Reset signal of Reset signal end Reset input, Reset module 14 resets pull-up node PU, pull down the electric potential of pull-up node PU, at this moment, pull-down control module 15 pulls up the electric potential of pull-down node PD under the control of pull-up node PU and second level signal end VGH, after the electric potential of pull-down node PD is pulled up, pull-down module 16 switches on, pull-down module 16 resets pull-up node PU, output control node K and each output signal end, make its electric potential all pulled down. In addition, if the Input signal Input from the Input signal terminal Input is an invalid signal, the Input module 11 is turned off, the potential of the pull-up node PU is pulled low, the output control module 12 is turned off, and the potential of the output control node K is pulled low, and the output module 13 is turned off.

In the fourth stage T4 of the display stage T1, the Input signal inputted from the Input signal terminal Input, the Reset signal inputted from the Reset signal terminal Reset, and the first clock signal inputted from the first clock signal terminal CLKx are all inactive signals. Therefore, the input module 11, the reset module 14 and the output control module 12 are all turned off, the pull-down control module 15 pulls up the potential of the pull-down node PD under the control of the second level signal terminal VGH and the pull-up node PU, so that the pull-down module 16 is turned on, the potentials of the pull-up node PU, the output control node K and each output signal terminal are continuously pulled down by the pull-down module 16, and the output module 13 is continuously in the off state because the potential of the output control node K is pulled down.

In the idle period T2, the Input signal Input from the Input signal terminal, the first clock signal Input from the first clock signal terminal CLKx, the Reset signal Input from the Reset signal terminal Reset, and the second clock signal Input from the second clock signal terminal are all low level signals, at this time, the Input module 11, the output control module 12, the output module 13, and the Reset module 14 are all turned off, and the pull-down module 16 is influenced by the pull-down control module 15 to keep the output signal terminals connected to the output sub-modules in a low level state.

Referring to fig. 3, a circuit diagram of a GOA unit according to an embodiment of the present invention is shown.

In the GOA unit, the input module 11 includes a first transistor T1; a gate and a first pole of the first transistor T1 are both connected to the Input signal terminal Input, and a second pole of the first transistor T1 is connected to the pull-up node PU.

The output control module 12 includes a second transistor T2; a gate of the second transistor T2 is connected to the pull-up node PU, a first pole of the second transistor T2 is connected to the first clock signal terminal CLKx, and a second pole of the second transistor T2 is connected to the output control node K.

The output module 13 includes a first output sub-module, a second output sub-module, a third output sub-module, and a fourth output sub-module. The first output submodule comprises a third transistor T3, the grid electrode of the third transistor T3 is connected with an output control node K, the first pole of the third transistor T3 is connected with a second clock signal end CLKA corresponding to the first output submodule, and the second pole of the third transistor T3 is connected with an output signal end Out A corresponding to the first output submodule; the second output submodule comprises a fourth transistor T4, the gate of the fourth transistor T4 is connected with the output control node K, the first pole of the fourth transistor T4 is connected with a second clock signal end CLKB corresponding to the second output submodule, and the second pole of the fourth transistor T4 is connected with an output signal end Out B corresponding to the second output submodule; the third output submodule comprises a fifth transistor T5, the gate of the fifth transistor T5 is connected with the output control node K, the first pole of the fifth transistor T5 is connected with the second clock signal CLKC end corresponding to the third output submodule, and the second pole of the fifth transistor T5 is connected with the output signal end Out C corresponding to the third output submodule; the fourth output sub-module includes a sixth transistor T6, a gate of the sixth transistor T6 is connected to the output control node K, a first pole of the sixth transistor T6 is connected to the second clock signal terminal CLKD corresponding to the fourth output sub-module, and a second pole of the sixth transistor T6 is connected to the output signal terminal Out D corresponding to the fourth output sub-module.

The reset module 14 includes a seventh transistor T7; a gate of the seventh transistor T7 is connected to the Reset signal terminal Reset, a first pole of the seventh transistor T7 is connected to the pull-up node PU, and a second pole of the seventh transistor T7 is connected to the first level signal terminal VGL.

The pull-down control module 15 includes an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, and an eleventh transistor T11; a gate and a first pole of the eighth transistor T8 are both connected to the second level signal terminal VGH, and a second pole of the eighth transistor T8 is connected to the gate of the ninth transistor T9; a first pole of the ninth transistor T9 is connected to the second level signal terminal VGH, and a second pole of the ninth transistor T9 is connected to the pull-down node PD; a gate of the tenth transistor T10 is connected to the pull-up node PU, a first pole of the tenth transistor T10 is connected to a gate of the ninth transistor T9, and a second pole of the tenth transistor T10 is connected to the first level signal terminal VGL; a gate of the eleventh transistor T11 is connected to the pull-up node PU, a first pole of the eleventh transistor T11 is connected to the pull-down node PD, and a second pole of the eleventh transistor T11 is connected to the first level signal terminal VGL.

The pull-down module 16 includes a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, and a seventeenth transistor T17; a gate of the twelfth transistor T12 is connected to the pull-down node PD, a first pole of the twelfth transistor T12 is connected to the pull-up node PU, and a second pole of the twelfth transistor T12 is connected to the first level signal terminal VGL; a gate of the thirteenth transistor T13 is connected to the pull-down node PD, a first pole of the thirteenth transistor T13 is connected to the output control node K, and a second pole of the thirteenth transistor T13 is connected to the first level signal terminal VGL; a gate of the fourteenth transistor 14 is connected to the pull-down node PD, a first pole of the fourteenth transistor T14 is connected to the output signal terminal Out a corresponding to the first output submodule, and a second pole of the fourteenth transistor T14 is connected to the first level signal terminal VGL; a gate of the fifteenth transistor T15 is connected to the pull-down node PD, a first pole of the fifteenth transistor T15 is connected to the output signal terminal Out B corresponding to the second output submodule, and a second pole of the fifteenth transistor T15 is connected to the first level signal terminal VGL; a gate of the sixteenth transistor T16 is connected to the pull-down node PD, a first pole of the sixteenth transistor T16 is connected to the output signal terminal Out C corresponding to the third output sub-module, and a second pole of the sixteenth transistor T16 is connected to the first level signal terminal VGL; the gate of the seventeenth transistor T17 is connected to the pull-down node PD, the first pole of the seventeenth transistor T17 is connected to the output signal terminal Out D corresponding to the fourth output submodule, and the second pole of the seventeenth transistor T17 is connected to the first level signal terminal VGL.

The storage module 17 includes a storage capacitor C; the first end of the storage capacitor C is connected with the pull-up node PU, and the second end of the storage capacitor C is connected with the output control node K.

In the embodiment of the present invention, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15, the sixteenth transistor T16, and the seventeenth transistor T17 are all N-type transistors, and are turned on when the gate is high level, and turned off when the gate is level, that is, when the signal input to the gate of the transistor is high level, the signal input to the gate of the transistor is an active signal, and when the signal input to the gate of the transistor is low level, the signal input to the gate of the transistor is an inactive signal. In addition, in order to distinguish two poles of the transistors except for the gate, the drains of the first to seventeenth transistors T1 to T17 are referred to as a first pole, and the sources of the first to seventeenth transistors T1 to T17 are referred to as a second pole.

It should be noted that, in the embodiment of the present invention, the output module 13 may include a plurality of output sub-modules, such as three, four, or five, and the like.

In addition, the output signal terminal connected to each output sub-module controls a row of gate scanning signal lines correspondingly, and therefore, when the output module 13 includes four output sub-modules, the corresponding output module 13 correspondingly controls four rows of gate scanning signal lines, i.e., one GOA unit can control four rows of gate scanning signal lines, compared to a conventional one GOA unit which controls only one row of gate scanning signal lines, in one display device, the number of the GOA units can be obviously reduced, and the space for arranging each GOA unit can be increased in the column direction of the display device, when the circuit elements in the GOA units are more distributed in the column direction of the display device, the space occupied by the GOA units in the row direction of the display device decreases, therefore, the size of the frame of the display device can be reduced, and the performance of the circuit elements in the GOA unit is not affected.

For example, when the display device has m rows of gate scan signal lines, in the embodiment of the present invention, one GOA unit corresponds to four rows of gate scan signal lines, the display device needs to be provided with m/4 GOA cells, one GOA cell includes seventeen transistors and one storage capacitor, one GOA cell corresponds to four rows of gate scanning signal lines, then on average one row of gate scan signal lines would correspond to 4.25 transistors and 0.25 storage capacitors, for the conventional display device, one row of gate scanning signal lines corresponds to one GOA unit, and m GOA units are required, and one GOA unit includes 9 transistors and 1 storage capacitor, i.e., one row of gate scan signal lines corresponding to 9 transistors and 1 storage capacitor, the number of GOA cell arrangements of the embodiment of the present invention is significantly reduced compared to the conventional display device, in addition, the number of transistors and storage capacitors corresponding to each row of gate scanning signal lines is also significantly reduced.

The operation of the circuit of the GOA unit shown in fig. 3 is described with reference to fig. 2.

In an actual driving process, the first level signal terminal VGL always inputs a low level signal, and the second level signal terminal VGH always inputs a high level signal, and the following description will use a transistor in the GOA unit as an N-type transistor.

In the first stage T1 of the display stage T1, when the Input signal inputted from the Input signal terminal Input is a high level signal, and the first clock signal inputted from the first clock signal terminal CLKx and the Reset signal inputted from the Reset signal terminal Reset are low level signals, the first transistor T1 is turned on, as shown in fig. 4, the first pole of the first transistor T1 is also connected to the Input signal terminal Input, therefore, when the first transistor T1 is turned on, the Input signal inputted from the Input signal terminal Input causes the potential of the pull-up node PU to be pulled up, and at the same time, the storage capacitor C is charged, and since the potential of the pull-up node PU is pulled up, at this time, the second transistor T2, the eleventh transistor T11 and the tenth transistor T10 are turned on, the potential of the pull-down node PD is pulled down by the first level signal terminal VGL, thereby causing the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15 and the fifteenth transistor T15 to be pulled down, thereby causing the twelfth transistor T12, the thirteenth transistor T13, the thirteenth transistor T8626, the fourteenth transistor T8628, the twelfth transistor T15, the twelfth transistor T8675, the twelfth transistor T8625, the storage capacitor C, to be pulled up, and the storage capacitor C to be charged The sixteenth transistor T16 and the seventeenth transistor T17 are both turned off, and the output control node K is low due to a low level signal input from the first clock signal terminal CLKx, so that the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are all turned off, the eighth transistor T8 and the ninth transistor T9 are all turned on by the second level signal terminal VGH, and the seventh transistor T7 is in a turned off state due to a low level signal input from the Reset signal terminal Reset.

In the second stage T2 of the display stage T1, the Input signal inputted from the Input signal terminal Input and the Reset signal inputted from the Reset signal terminal Reset are low level signals, the first clock signal inputted from the first clock signal terminal CLKx is a high level signal, the potential of the pull-up node PU is further pulled up by the influence of the storage capacitor C, and the second transistor T2 is still in an on state, as shown in fig. 5, since the first clock signal inputted from the first clock signal terminal CLKx is a high level signal, the potential of the output control node K is pulled up, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 connected to the output control node K are all turned on, at this time, the second clock signal terminal CLKA connected to the third transistor T3 is inputted with the corresponding second clock signal, and the second clock signal terminal CLKB connected to the fourth transistor T4 is inputted with the corresponding second clock signal, the second clock signal terminal CLKC connected to the fifth transistor T5 receives the corresponding second clock signal, and the second clock signal terminal CLKD connected to the sixth transistor T6 receives the corresponding second clock signal.

When the second clock signal terminal CLKA is inputted with a high level signal, and the second clock signal terminal CLKB, the second clock signal terminal CLKC and the second clock signal terminal CLKD are all inputted with a low level signal, an output signal terminal Out a connected to the third transistor T3 outputs a high level signal, a gate scan signal line G1 connected to the output signal terminal Out a is in a high level state, the gate scanning signal line G1 is turned on corresponding to the row of transistors, the Source Driver chip (Source Driver) inputs the data signal to the turned-on transistors of the gate scanning signal line G1 through the data signal line, as shown in fig. 6, at this time, the output signal terminal Out B, the output signal terminal Out C and the output signal terminal Out D all output low level signals, the transistors of the corresponding rows of gate scan lines G2, G3, and G4 connected to the output signal terminal Out B, the output signal terminal Out C, and the output signal terminal Out D are all in an off state.

When the second clock signal terminal CLKB inputs a high level signal, and the second clock signal terminal CLKA, the second clock signal terminal CLKC and the second clock signal terminal CLKD all input a low level signal, an output signal terminal Out B connected to the fourth transistor T4 outputs a high level signal, a gate scan signal line G2 connected to the output signal terminal Out B is in a high level state, the gate scanning signal line G2 is turned on corresponding to the row of transistors, Source Driver) inputs a data signal to the transistors whose gate scanning signal line G2 is turned on through the data signal line, as shown in fig. 7, at this time, the output signal terminal Out a, the output signal terminal Out C and the output signal terminal Out D all output low level signals, the transistors of the corresponding rows of gate scan lines G1, G3, and G4 connected to the output signal terminal Out a, the output signal terminal Out C, and the output signal terminal Out D are all in an off state.

When a high-level signal is input to the second clock signal terminal CLKC, and low-level signals are input to the second clock signal terminals CLKA, CLKB, and CLKD, the output signal terminal Out C connected to the fifth transistor T5 outputs a high-level signal, the gate scan signal line G3 connected to the output signal terminal Out C is in a high-level state, the transistors in the row corresponding to the gate scan signal line G3 are turned on, the Source Driver inputs a data signal to the transistors in the row where the gate scan signal line G3 is turned on through the data signal line, as shown in fig. 8, at this time, the transistors in the row corresponding to the output signal terminal Out a, the output signal terminal Out B, and the output signal terminal Out D all output low-level signals, and the transistors in the row corresponding to the gate scan lines G1, G2, and G4 connected to the output signal terminal Out a, the output signal terminal Out B, and the output signal terminal Out D are all in a turned off state.

When the second clock signal terminal CLKD inputs a high-level signal and the second clock signal terminals CLKA, CLKB, and CLKC all input a low-level signal, the output signal terminal Out D connected to the sixth transistor T6 outputs a high-level signal, the gate scan signal line G4 connected to the output signal terminal Out D is in a high-level state, the transistors in the row corresponding to the gate scan signal line G4 are turned on, the Source Driver inputs a data signal to the transistors in which the gate scan signal line G4 is turned on through the data signal line, as shown in fig. 9, at this time, the transistors in the rows corresponding to the output signal terminal Out a, the output signal terminal Out B, and the output signal terminal Out C all output a low-level signal, and the transistors in the rows corresponding to the gate scan lines G1, G2, and G3 connected to the output signal terminal Out a, the output signal terminal Out B, and the output signal terminal Out C are all in a turned off state.

Only one of the second clock signals CLKA, CLKB, CLKC, and CLKD is at a high level state at any time, so that the output signal terminal Out a, the output signal terminal Out B, the output signal terminal Out C, and the output signal terminal Out D can be separately controlled, and each output signal terminal is correspondingly connected with one row of gate scanning signal lines, so that it is possible to separately control four rows of gate scanning signal lines G1, G2, G3, and G4 connected with the output signal terminal Out a, the output signal terminal Out B, the output signal terminal Out C, and the output signal terminal Out D.

In addition, in the second stage T2, the Reset signal inputted from the Reset signal terminal Reset is a low level signal, the seventh transistor T7 is turned off, the potential of the pull-up node PU is pulled high, so the tenth transistor T10 and the eleventh transistor T11 are both turned on, the eighth transistor T8 and the ninth transistor T9 are both turned on under the control of the second level signal terminal VGH, and the eleventh transistor T11 is turned on, so the potential of the pull-down node PD is still in a pulled low state, and the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15, the sixteenth transistor T16 and the seventeenth transistor T17 connected to the pull-down node PD are all turned off.

In the third stage T3 of the display stage T1, when the Reset signal inputted from the Reset signal terminal Reset is a high level signal, the Input signal inputted from the Input signal terminal Input and the first clock signal inputted from the first clock signal terminal CLKx are both low level signals, the seventh transistor T7 is turned on, as shown in fig. 10, the potential of the pull-up node PU is pulled low, the second transistor T2, the tenth transistor T10 and the eleventh transistor T11 are all turned off, the eighth transistor T8 and the ninth transistor T9 are continuously in an on state under the action of the second level signal terminal VGH, the potential of the pull-down node PD is pulled high, the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15, the sixteenth transistor T16 and the seventeenth transistor T17 are all turned on, the twelfth transistor T12 is turned on, and further, the potential of the pull-up node PU is in a low level state, the thirteenth transistor T13 is turned on, so that the potential of the output control node K is pulled low, the fourteenth transistor T14, the fifteenth transistor T15, the sixteenth transistor T16 and the seventeenth transistor T17 are turned on, and the potentials of the output signal terminals Out a, Out B, Out C and Out D are pulled low, respectively. At this time, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are all in an off state.

In the fourth stage T4 of the display stage T1, the Input signal inputted from the Input signal terminal Input, the first clock signal inputted from the first clock signal terminal CLKx, and the Reset signal inputted from the Reset signal terminal Reset are all low level signals, the first transistor T1 and the seventh transistor T7 are turned off, as shown in fig. 11, the eighth transistor T8 and the ninth transistor T9 continue to maintain the on state under the control of the second level signal terminal VGH, the potential of the pull-down node PD also continues to be in the pulled-up state, the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15, the sixteenth transistor T16 and the seventeenth transistor T17 all continue to be in the on state, the potential of the pull-up node PU is pulled low due to the turn-on of the twelfth transistor T12, and the second transistor T2, the tenth transistor T10 and the eleventh transistor T11 all continue to be in the off state. At this time, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are all in an off state.

Since the seventh transistor T7 is turned off in the fourth stage T4, in order to prevent the storage capacitor C from leaking to cause the potential of the pull-up node PU to fluctuate, the twelfth transistor T12 is provided to stabilize the potential of the pull-up node PU in a low state in the fourth stage T4.

In the embodiment of the present invention, in the idle stage T2, the Input signal Input from the Input signal terminal, the first clock signal Input from the first clock signal terminal CLKx, the Reset signal Input from the Reset signal terminal Reset, and the second clock signal Input from the second clock signal terminal are all low level signals, and at this time, the output signal terminals connected to the output submodules in the output module 13 are all in a low level state.

Referring to fig. 12, a schematic diagram of another GOA unit in accordance with an embodiment of the present invention is shown.

On the basis of fig. 1, the GOA unit further includes an initialization module 18; the initialization module 18 is respectively connected to the Input signal terminal Input, each output signal terminal, and the first level signal terminal VGL, and is configured to initialize each output signal terminal under the control of the Input signal terminal Input.

In the embodiment of the present invention, the initialization module 18 is respectively connected to the output signal terminal Out a, the output signal terminal Out B, and the output signal terminal Out N. By adding the initialization module 18 to the GOA unit, the output signal terminal in the GOA unit is initialized in the process of pulling up the potential of the pull-up node PU through the Input signal terminal Input, so as to ensure that the potential of the output signal terminal is in the initialized state before the output module 13 transmits the second clock signal to the output signal terminal.

The main operation of the initialization module 18 is that in the first stage T1 of the display stage T1, the initialization module 18 is connected to the Input signal terminal Input, and in the first stage T1, the Input signal Input by the Input signal terminal Input is an active signal, and under the control of the Input signal terminal Input, the initialization module 18 is turned on to initialize each output signal terminal, so that each output signal terminal is in a low level state.

Referring to fig. 13, a circuit diagram of another GOA unit in accordance with an embodiment of the present invention is shown.

Wherein the initialization module 18 includes an eighteenth transistor T18, a nineteenth transistor T19, a twentieth transistor T20, and a twenty-first transistor T21; the gate of the eighteenth transistor T18 is connected to the Input signal terminal Input, the first pole of the eighteenth transistor T18 is connected to the output signal terminal Out a corresponding to the first output submodule, and the second pole of the eighteenth transistor T18 is connected to the first level signal terminal VGL; the gate of the nineteenth transistor T19 is connected to the Input signal terminal Input, the first pole of the nineteenth transistor T19 is connected to the output signal terminal Out B corresponding to the second output submodule, and the second pole of the nineteenth transistor T19 is connected to the first level signal terminal VGL; a gate of the twentieth transistor T20 is connected to the Input signal terminal Input, a first pole of the twentieth transistor T20 is connected to the output signal terminal Out C corresponding to the third output submodule, and a second pole of the twentieth transistor T20 is connected to the first level signal terminal VGL; the gate of the twenty-first transistor T21 is connected to the Input signal terminal Input, the first pole of the twenty-first transistor T21 is connected to the output signal terminal Out D corresponding to the fourth output submodule, and the second pole of the twenty-first transistor T21 is connected to the first level signal terminal VGL.

Among them, the eighteenth transistor T18, the nineteenth transistor T19, the twentieth transistor T20, and the twenty-first transistor T21 are all N-type transistors.

In the embodiment of the present invention, in the first stage T1 in the display stage T1, the Input signal inputted by the Input signal terminal Input is a high level signal, the eighteenth transistor T18, the nineteenth transistor T19, the twentieth transistor T20, and the twenty-first transistor T21 connected to the Input signal terminal Input are all turned on, the second pole of the eighteenth transistor T18, the second pole of the nineteenth transistor T19, the second pole of the twentieth transistor T20, and the second pole of the twenty-first transistor T21 are all connected to the first level signal terminal VGL, and the first level signal terminal VGL is always inputted with a low level signal, and therefore, the output signal terminal Out a connected to the first pole of the eighteenth transistor T18, the output signal terminal Out B connected to the first pole of the nineteenth transistor T19, the output signal terminal Out C connected to the first pole of the twentieth transistor T20, and the output terminal Out D connected to the first pole of the twenty-first transistor T21 are all pulled low level signal, namely, the initialization of the output signal end Out A, the output signal end Out B, the output signal end Out C and the output signal end Out D is realized.

The operation states of the other transistors in the first stage t1 are the same as those in the first stage t1, and the detailed description of the embodiment of the invention is omitted.

In the second stage T2, the third stage T3, and the fourth stage T4 in the display stage T1, because the Input signals Input by the Input signal terminal are all low-level signals, in the second stage T2, the third stage T3, and the fourth stage T4, the eighteenth transistor T18, the nineteenth transistor T19, the twentieth transistor T20, and the twenty-first transistor T21 are all in an off state, and the operating states of the other transistors in the second stage T2, the third stage T3, and the fourth stage T4 are all the same as the operating states in the second stage T2, the third stage T3, and the fourth stage T4, which is not repeated herein.

In the embodiment of the present invention, the initialization module 18 is disposed in the GOA unit, and in a process of pulling up the potential of the pull-up node PU through the Input signal terminal Input, a high level signal of the Input signal terminal Input turns on the initialization module 18 in the GOA unit, and the initialization module 18 transmits a low level signal of the first level signal terminal VGL to the output signal terminal to initialize the output signal terminal, so that it is ensured that the potential of the output signal terminal is in a low level state before the subsequent output module 13 transmits the second clock signal to the output signal terminal, so as to avoid interference of other signals to the output signal terminal.

It should be noted that, when the display device provided with the GOA units is the dual-edge driving, the first clock signal terminal CLKx may include CLKo and CLKe, where CLKo and CLKe are first clock signals with the same frequency and reverse direction, the first clock signal terminal CLKo is a clock signal for controlling the GOA units in the even rows in the display device, and the first clock signal terminal CLKe is a clock signal for controlling the GOA units in the odd rows in the display device. When the display device with the GOA units is single-side driven, the first clock signal terminal CLKx is the clock signal for controlling each row of GOA units.

In the embodiment of the present invention, by disposing a plurality of output sub-modules in the output module, and the second clock signal terminal and the output signal terminal respectively connected to any two output sub-modules are different, so that one GOA unit is connected to a plurality of output signal terminals, and each output signal terminal controls one row of gate scanning signal lines, and therefore, one GOA unit can control a plurality of rows of gate scanning signal lines, so as to reduce the number of GOA units disposed in the display device, and there is more space in the column direction of the display device for disposing transistors and storage capacitors in the GOA unit, so that the size of the GOA unit in the row direction of the display device can be reduced, and further the frame size of the display device can be reduced, and at the same time, because there is enough space in the column direction of the display device to distribute the transistors and storage capacitors in the GOA unit, there is no need to reduce the size of the transistors and the size of the capacitors in the GOA unit, therefore, the frame size of the display device can be reduced, and the stability of the GOA unit can be guaranteed.

Example two

The embodiment of the invention provides a GOA circuit, which comprises a plurality of cascaded GOA units; in the GOA circuit, except for a first-stage GOA unit, an Input signal end of each stage of GOA unit is connected with an output control node K of a previous-stage GOA unit; except the last grade of GOA unit, the Reset signal end Reset of each grade of GOA unit is connected with the output control node K of the next grade of GOA unit.

In the embodiment of the present invention, as shown in fig. 14, when the GOA circuit has m/4-level GOA units, for the nth-level GOA unit, the output control node Kn-1 of the nth-1-level GOA unit is connected to the Input signal end Input of the nth-level GOA unit, and is configured to Input a corresponding Input signal to the nth-level GOA unit to pull up the potential of the pull-up node PU; and an output control node Kn +1 of the n +1 th-level GOA unit is connected with a Reset signal end Reset of the n-level GOA unit and is used for resetting the n-level GOA unit, wherein n is greater than 1, and n +1 is less than m/4.

It should be noted that, for a first-stage GOA unit in a GOA unit, an Input signal terminal Input of the GOA unit is connected to an enable signal terminal STV, and transmits a corresponding Input signal to the first-stage GOA unit through the enable signal terminal STV, an output control node K1 of the first-stage GOA unit inputs a corresponding Input signal to an Input signal terminal Input of a second-stage GOA unit, and a Reset signal terminal Reset of the first-stage GOA unit receives a corresponding Reset signal transmitted by an output control node K2 of the second-stage GOA unit. For the last-level GOA unit in the GOA units, that is, for the m/4-level GOA unit in the GOA units, the m/4-level GOA unit receives the corresponding Input signal transmitted by the output control node Km/4-1 of the m/4-1-level GOA unit, the output control node Km/4 of the m/4-level GOA unit transmits the corresponding Reset signal to the Reset signal terminal Reset of the m/4-1-level GOA unit, and the output control node Km/4 of the m/4-level GOA unit does not need to transmit the corresponding Input signal to the Input signal terminals Input of other GOA units.

In the embodiment of the present invention, after the gate scan signal lines connected to the output signal terminals controlled by the output sub-modules in the first GOA unit GOA1 are all turned on, as shown in fig. 9, the next GOA unit starts to operate, i.e., the GOA2 starts to operate, the gate scan signal line G5 connected to the first output sub-module in the GOA2 unit is turned on, and the gate scan signal lines connected to the other output sub-modules in the GOA2 unit are all turned off, as shown in fig. 15, and the output signal terminals connected to the output sub-modules in the GOA1 unit are all reset and kept at a low level state, so that the gate scan signal lines controlled by the GOA1 unit are all in a turned off state.

The embodiment of the invention also provides a display device which comprises the GOA circuit.

In the embodiment of the present invention, the display device may be: any product or part provided with a GOA circuit, such as a mobile phone, a tablet personal computer, a television, a notebook computer, a vehicle-mounted display product and the like.

While, for purposes of simplicity of explanation, the foregoing method embodiments have been described as a series of acts or combination of acts, it will be appreciated by those skilled in the art that the present invention is not limited by the illustrated ordering of acts, as some steps may occur in other orders or concurrently with other steps in accordance with the invention. Further, those skilled in the art should also appreciate that the embodiments described in the specification are preferred embodiments and that the acts and modules referred to are not necessarily required by the invention.

The embodiments in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.

Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The GOA unit, the driving method thereof, the GOA circuit and the display device provided by the present invention are described in detail above, and the principle and the implementation of the present invention are explained in the present document by applying specific examples, and the description of the above embodiments is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed, and in summary, the content of the present specification should not be construed as a limitation to the present invention.

Claims

1. A GOA unit, comprising: the device comprises an input module, an output control module, an output module, a reset module, a pull-down control module, a pull-down module and a storage module;

the pull-down module is respectively connected with the pull-down node, the pull-up node, the output control node, each output signal end and the first level signal end, and is configured to pull down potentials of the pull-up node, the output control node and each output signal end under the control of the pull-down node;

2. The GOA unit of claim 1, wherein the input module comprises a first transistor;

3. The GOA unit of claim 1, wherein the output control module comprises a second transistor;

4. The GOA unit of claim 1, wherein the output module comprises a first output sub-module, a second output sub-module, a third output sub-module and a fourth output sub-module;

the second output sub-module comprises a fourth transistor; a gate of the fourth transistor is connected with the output control node, a first pole of the fourth transistor is connected with a second clock signal end corresponding to the second output sub-module, and a second pole of the fourth transistor is connected with an output signal end corresponding to the second output sub-module;

5. The GOA unit of claim 1, wherein the reset module comprises a seventh transistor;

6. The GOA unit according to claim 1, wherein the pull-down control module comprises an eighth transistor, a ninth transistor, a tenth transistor and an eleventh transistor;

7. The GOA unit of claim 4, wherein the pull-down module comprises a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor and a seventeenth transistor;

8. The GOA unit according to claim 1, wherein the storage module comprises a storage capacitor;

9. The GOA unit of claim 4, further comprising an initialization module; the initialization module is respectively connected with the input signal end, each output signal end and the first level signal end, and is configured to initialize each output signal end under the control of the input signal end.

10. The GOA unit of claim 9, wherein the initialization module comprises an eighteenth transistor, a nineteenth transistor, a twentieth transistor, and a twenty-first transistor;

11. A GOA circuit comprising a plurality of cascaded GOA cells of any one of claims 1-10;

12. A display device comprising the GOA circuit of claim 11.

13. A driving method of a GOA unit, for driving a GOA unit according to any one of claims 1 to 10, said method comprising: