Background
The monocrystalline silicon wafer is an important substrate material in the manufacturing process of an Integrated Circuit (IC), the quality of the silicon wafer directly influences the electrical performance, reliability, yield and the like of a device, so that the requirement on the quality of the silicon material is higher and higher, and downstream customers can put forward specific quantifiable standard requirements, such as oxygen-carbon content, resistivity and crystal orientation of crystal quality, on the silicon wafer of an upstream material manufacturer; the thickness of the silicon wafer, the flatness, particles, roughness, metal impurities, product appearance and the like of the surface of the silicon wafer, but damage residues on the surface of the silicon wafer are difficult to quantitatively put forward as latent invisible requirements, the surface of the silicon wafer meeting the requirements should be in a mirror surface state, no damage residues exist, and the residual damage layer on the surface can seriously influence the application of integrated circuits and devices. However, the processing process flow of the silicon wafer is long, and particularly in a plurality of machining processes, mechanical damage which can form a surface layer can be avoided, such as the processes of silicon wafer linear cutting and silicon wafer grinding. The process of generating damage exists, and a surface damage repairing process is correspondingly available, such as silicon chip corrosion, surface polishing and other processes are also processes of removing surface damage, obtaining perfect surface quality and removing damage residues, so that testing and understanding of the thickness of the damaged layer generated in different process stages has important guiding significance for repairing the damaged layer in acid corrosion and polishing processes.
In the process of grinding and processing the silicon wafer, an amorphous layer or a broken layer can be inevitably formed on the surface of the silicon wafer under the action of the pressure of the grinding disc, and the amorphous layer has incomplete crystal lattices and loose structures and is easy to adsorb impurities. Therefore, it is very important to repair the surface damage of the silicon wafer by the etching process and the polishing process, and in order to better remove and repair the surface damage of the silicon wafer, the surface damage thickness of the grinding sheet needs to be tested and known, so as to obtain a stable silicon wafer surface without damage residue. Therefore, the testing of the thickness of the damaged layer on the surface of the grinding sheet is an important step for ensuring the stability of the process.
The silicon wafers commonly used in the silicon wafers for the existing semiconductor preparation are mainly a (111) crystal orientation silicon wafer and a (100) crystal orientation silicon wafer, and the corrosion morphologies of the two crystal orientation silicon wafers are different in the same corrosion solution. The existing conventional method is to corrode in alkaline solution, the corrosion appearance of the (111) crystal orientation silicon wafer is irregular wafer shape, and the corrosion appearance of the (100) crystal orientation silicon wafer is square. The difference among different corrosion appearances is determined by lattice surface atomic density, corrosion mechanism, corrosion rate and other factors of the single crystal, and the methods can only qualitatively represent the states of the surfaces of the silicon wafers with different crystal orientations, but few methods are used for quantitatively representing the thicknesses of surface damage layers of the silicon wafers with different crystal orientations. In the current research, large-scale analysis and precise analysis instruments such as a TEM (transmission electron microscope) and an SEM (scanning electron microscope) can only analyze the thickness of the subsurface damage layer, the equipment is expensive and needs a complicated sample preparation link, and the precise equipment cannot represent the grinding sheet with the relatively thick depth of the subsurface damage layer.
In actual production, a KOH or NaOH alkaline solution is usually used for corroding the silicon wafer, and then a balance is adopted for weighing the corroded silicon wafer so as to confirm the weight change of the silicon wafer, so that the thickness of a damaged layer on the surface of the silicon wafer is quantitatively analyzed. Specifically, when the silicon grinding piece is corroded in an alkaline solution, the quality of the silicon wafer is gradually reduced along with the increase of the corrosion time, and the thickness of the silicon wafer is correspondingly gradually reduced until the quality of the silicon wafer is almost not changed any more, the thickness removed by corrosion is regarded as a surface damage layer of the silicon wafer, and then the surface damage layer thickness of the crystal-oriented silicon grinding piece can be obtained through conversion and quantitative representation through calculation and analysis. The corrosion behaviors of the <111> crystal orientation silicon wafer and the <100> crystal orientation silicon wafer in an alkaline corrosion solution are greatly different, which is caused by different atom densities in the silicon single crystal of cubic lattice, and the crystal face atom arrangements of the <111> crystal orientation silicon wafer and the <100> crystal orientation silicon wafer are different, so that the atom surface densities of the crystal faces in the <111> crystal orientation silicon wafer and the <100> crystal orientation silicon wafer are different. When a silicon single crystal is grown, the normal growth speed of the {100} crystal plane family is the fastest, and the normal growth speed of the {111} crystal plane family is the slowest. If the silicon single crystal is corroded by the alkaline solution, the corrosion rates of all crystal face groups are different, the corrosion rate of the {100} crystal face group is the fastest, the corrosion rate of the {110} crystal face group is the second highest, and the corrosion rate of the {111} crystal face group is the slowest.
The method for etching silicon wafers with crystal orientation (111) and crystal orientation (100) by using alkali liquor is adopted to etch the silicon wafers in the crystal orientation (111) and the crystal orientation (100) respectively in the etching process of the alkali liquor, the etching weight is measured, the thickness of a damaged layer is quantitatively analyzed, and the obtained result is as follows: for a <111> crystal orientation silicon wafer, the corrosion rate in alkaline liquid is very slow, and as a perfect crystal layer is approached, the corrosion can generate a self-stopping phenomenon, namely constant mass and weight; that is, along with the increase of the corrosion time, the surface layer of the <111> crystal orientation silicon wafer is gradually consumed, the mass of the silicon wafer gradually becomes smaller, the thickness of the silicon wafer gradually becomes thinner, the balance is used for monitoring the weighing of the <111> crystal orientation silicon wafer until the corroded part of the <111> crystal orientation silicon wafer is the damaged layer on the surface when the constant weight of the silicon wafer hardly changes, and then the thickness of the damaged layer on the surface of the <111> crystal orientation silicon wafer is obtained through conversion by weighing calculation and analysis of the electronic balance; therefore, the thickness of the damaged layer of the (111) crystal orientation silicon wafer can be easily judged by adopting the variable of the weight difference. For the silicon wafer with the crystal orientation of <100>, due to the influence of the lattice surface atomic density of the silicon wafer with the crystal orientation of <100>, the corrosion rate in the alkaline solution is high, the thickness in the alkaline corrosion solution is gradually reduced along with the increase of the corrosion time, the quality is continuously reduced all the time, the corrosion self-stop phenomenon can not occur, the condition of constant weight of the silicon wafer can not occur, and therefore, the thickness of the damaged layer on the surface of the silicon wafer with the crystal orientation of <100> can not be obtained qualitatively by using the variable with poor quality.
Disclosure of Invention
The invention provides a method for testing the thickness of a surface damage layer of a <100> crystal orientation silicon single crystal grinding sheet, which solves the technical problem that the thickness of the surface damage layer of the <100> crystal orientation silicon wafer cannot be qualitatively represented by a variable with poor quality in the prior art.
In order to solve at least one technical problem, the technical scheme adopted by the invention is as follows:
a method for testing the thickness of a damaged layer on the surface of a polishing sheet of a (100) crystal-oriented silicon single crystal comprises the following steps:
continuously corroding a plurality of silicon wafers to be tested with the same specification in alkali liquor for a plurality of times;
acquiring the accumulated corrosion thickness and the corrosion rate of each silicon wafer to be tested after each corrosion;
determining whether the change rule of the corrosion rate of all the tested silicon wafers is consistent with the change rule of the accumulated corrosion thickness;
when the thickness rule changes consistently, selecting a point which appears for the first time when the corrosion rate of each silicon wafer to be tested tends to be stable as an inflection point of the silicon wafer to be tested;
and determining the average value of the accumulated corrosion thickness corresponding to each inflection point in the batch of the silicon wafers to be tested as the thickness of the surface damage layer of the batch of the silicon wafers to be tested.
Further, based on that each accumulated corrosion thickness of the silicon wafer to be tested is an abscissa and each corrosion rate is an ordinate, a corrosion rate-accumulated corrosion thickness curve of each silicon wafer to be tested is obtained.
Furthermore, in the corrosion rate-cumulative corrosion thickness curve of each tested silicon wafer, the change rule of the corrosion rate is gradually reduced and tends to be stable along the increase of the cumulative corrosion thickness, and all the corrosion rates are in the first quadrant.
Further, the standard that the average value of the accumulated corrosion thicknesses of all the silicon wafers to be tested corresponding to each inflection point in the batch of silicon wafers to be tested is determined to be the thickness of the surface damage layer of the silicon wafer to be tested is as follows: when the curve slopes of the inflection points of at least half of the tested silicon wafers in all the tested silicon wafers and the curve slopes of the inflection points which are continuously at least 3 times later are consistent, and the curve slopes of the inflection points and the curve slopes behind the inflection points are within the range of 0 +/-3E-04.
Further, the number of etching after the inflection point in the etching rate-cumulative etching thickness curve is at least 3.
Further, the method further comprises the judgment of inflection point selection, and specifically comprises the following steps:
taking the inflection point in the corrosion rate-accumulated corrosion thickness curve of each silicon wafer to be tested and the corrosion rate 3 times after the inflection point, and carrying out average calculation to obtain the average corrosion rate of each silicon wafer to be tested;
secondly, averaging the average corrosion rates of all the tested silicon chips for the second time to obtain the limit corrosion rates of all the tested silicon chips;
and (3) judging whether the inflection point selection is correct or not by determining whether the corrosion rate of the inflection point in the corrosion rate-accumulated corrosion thickness curve of each tested silicon wafer and the corrosion rate of 3 adjacent points behind the inflection point are in a certain range or not by taking the limit corrosion rate as a reference.
Furthermore, if the corrosion rate of the inflection point in the corrosion rate-accumulated corrosion thickness curve of each silicon wafer to be tested and the absolute value of the difference value between the corrosion rate of the adjacent 3 points after the inflection point and the limit corrosion rate are not more than 1.5%, the inflection point is correctly selected.
Further, if half of the corrosion rate of the inflection point in the corrosion rate-accumulated corrosion thickness curve of any tested silicon wafer and the absolute value of the difference between the corrosion rate of the adjacent 3 points after the inflection point and the limit corrosion rate are both greater than 1.5%, the inflection point is selected incorrectly;
and judging after reselecting.
Furthermore, when the silicon wafer is corroded each time, at least two silicon wafers to be tested with the same specification and size are taken, and all the silicon wafers to be tested are synchronously corroded and tested.
Furthermore, each time of corrosion, two silicon wafers with the same specification and size are taken as non-measurement accompanying wafers and are placed in the wafer basket together with all the silicon wafers to be measured.
Furthermore, the non-measurement accompanying wafers are placed at the two side edges of the silicon wafer to be measured at the middle position, and all the silicon wafers are placed at intervals.
Further, after each corrosion, all the silicon wafers to be tested and the non-measurement accompanying wafers are washed in pure water at least once.
Further, the thickness of all the silicon wafers to be tested is measured after each pure water cleaning, so as to obtain the thickness of the silicon wafers to be tested after each corrosion.
Further, obtaining the thickness of each corrosion based on the thickness of the silicon wafer to be tested after each corrosion and the thickness of the silicon wafer to be tested after the last corrosion;
and obtaining the etching rate of each time and the accumulated etching thickness of the current time of the silicon wafer to be tested based on the etching thickness and the etching time of each time.
Further, the time for each etching of the silicon wafer is the same, and the range of 70-120 s.
Further, the time for each etching of the silicon wafer was 100 seconds.
Furthermore, all silicon chips are continuously and repeatedly etched in the same alkali liquor tank, and the concentration and the temperature of the alkali liquor are the same during each etching.
Further, the alkali liquor is KOH solution, the mass concentration of the solution is 40-45%, and the corrosion temperature is 75-85 ℃.
The invention relates to a method for testing the thickness of a surface damage layer of a (100) crystal orientation silicon single crystal grinding sheet, which judges whether the corrosion thickness corresponding to an inflection point is the thickness of the surface damage layer of a silicon wafer or not by monitoring the inflection point in a silicon wafer corrosion rate-accumulated corrosion thickness curve and the curve slopes of a plurality of times thereafter. The method can quickly analyze and monitor the depth of the surface damage layer of the silicon grinding sheet in the silicon wafer production process, provides a basis for the processing (thinning) removal amount of the semiconductor silicon wafer in different process procedures, and has the advantages of accurate judgment result, good reproducibility, convenient and quick operation and simple flow.
Detailed Description
In the process of corrosion of alkaline solution, because the atomic surface density of the crystal orientation of <111> is high and the corrosion rate is slow, the chemical reaction between the crystal orientation of <111> and alkaline solution is self-stopped along with the lengthening of the corrosion time, and the thickness of the damaged layer is judged by the weight change of the crystal orientation of <100 >. And the atomic surface density of the <100> crystal orientation is small, the corrosion rate is high, the chemical reaction with the alkali liquor is continuously carried out along with the lengthening of the corrosion time, and for the <100> crystal orientation silicon wafer with the small diameter of 6 inches, the surface damage layer of the <100> crystal orientation silicon wafer with the same size specification is roughly replaced by testing the surface damage layer of the <111> crystal orientation silicon wafer with the small diameter in the production practice. However, because the atomic surface densities of the <100> crystal-oriented silicon wafer and the <111> crystal-oriented silicon wafer are different, the processing processes in the cutting and grinding processes are not completely the same, and the damaged layers are not completely consistent, so that the damaged layer on the surface of the <100> crystal-oriented silicon wafer cannot be truly represented by the alternative method. Particularly, for the field of large-diameter silicon wafers of 8 inches and 12 inches, the silicon wafers with the crystal orientation of <111> are rarely used due to the production cost, and the mainstream large-diameter silicon wafers of 8 inches and 12 inches are both the silicon wafers with the crystal orientation of <100>, so that the invention is important for designing a simple and quick testing method to quantitatively characterize the thickness of the surface damage layer of the large-diameter silicon wafers with the crystal orientation of <100 >.
The invention is described in detail below with reference to the figures and the specific embodiments.
This embodiment provides a method for testing the thickness of a damaged layer on the surface of a polishing wafer of a <100> crystal-oriented silicon single crystal, as shown in fig. 1, comprising the steps of:
and S1, continuously corroding a plurality of silicon wafers to be tested with the same specification in the alkaline solution for a plurality of times.
Specifically, each batch of silicon wafer test needs to be performed with multiple rounds of corrosion and test, and the silicon wafers to be tested in the same batch are all silicon wafers with the same specification, so that observation and comparison are facilitated. In the test of the same batch, when corroding the silicon chip each time, take two silicon chips of the same specification and size as the silicon chip to be tested to corrode synchronously, and also take two silicon chips of the same specification and size as the non-measurement accompanying chip; all the non-measurement accompanying wafers and all the tested silicon wafers are placed in the wafer basket together, the silicon wafers of the non-measurement accompanying wafers are placed at the edges of the two sides of the tested silicon wafers located in the middle, the placing positions of the tested silicon wafers and the non-measurement accompanying wafers are shown in fig. 2, and all the silicon wafers are placed in the wafer basket at intervals. After each corrosion, only the tested silicon wafer placed in the middle is subjected to thickness test, and two accompanying sheets with the outer edges are not required to be tested.
All the silicon chips to be measured and the non-measurement accompanying chips in the same batch are synchronously carried out in an alkaline solution tank in the same cleaning machine, and the components of the alkaline solution are the same; and after each alkali liquor corrosion, the surfaces of all the silicon wafers to be tested and the non-measurement accompanying wafers are cleaned at least once by pure water so as to remove corrosion layers and alkali liquor on the surfaces of the silicon wafers and also remove impurity particles on the surfaces. The cleaning machine comprises an alkaline solution tank and at least one pure water cleaning tank, namely, the cleaning is carried out once each time of corrosion, then the cleaned silicon wafer to be tested is dried, then the silicon wafer to be tested is measured, and the thickness of the silicon wafer to be tested is measured.
In the test method, an alkali liquor corrosion tank does not need to be specially and independently arranged or the liquid is replaced every time, and the test method can be synchronously carried out along with the alkali liquor cleaning procedure in the conventional production process, is convenient and quick and has lower cost; and the thickness of the damaged layer on the surface of the silicon wafer can be simply and quickly analyzed and tested, and the stability of the production process and the quality of the product are monitored.
Furthermore, all silicon wafers are continuously etched for multiple times in the same alkali liquor tank, and the concentration and the temperature of the alkali liquor are the same during each etching. In the embodiment, the alkali liquor is selected to be KOH solution, the mass concentration of the solution is 40-45%, and the corrosion temperature is 75-85 ℃. Because the corrosion rate of the <100> crystal orientation silicon wafer in the alkaline solution is relatively slow and the corrosion efficiency is low, the setting of relatively high mass concentration can improve the corrosion speed, and simultaneously the corrosion temperature is increased, so that the corrosion efficiency is further improved, and the corrosion times of the <100> crystal orientation silicon wafer are controllable.
And S2, acquiring the accumulated corrosion thickness and the corrosion rate of each silicon wafer after each corrosion, and acquiring a corrosion rate-accumulated corrosion thickness curve of each silicon wafer by taking the accumulated corrosion thickness of each silicon wafer as an abscissa and the corrosion rate of each silicon wafer as an ordinate.
The test data after each alkali liquor corrosion is the measured thickness of the silicon wafer after each corrosion and pure water cleaning. During testing, the thickness of the silicon wafer to be tested is tested by using silicon wafer thickness testing instruments such as an ADE7200 silicon wafer thickness sorter, an E + H thickness sorter or WS 2+. After each time of pure water cleaning and drying, each silicon wafer to be tested is tested to obtain the thickness of the silicon wafer, the thickness can be measured based on the characteristics of thickness measuring equipment during testing, and the thickness value obtained through measurement is the thickness of the silicon wafer to be tested after the silicon wafer is corroded at this time.
And based on the thickness of the silicon wafer to be detected after each corrosion and the thickness of the silicon wafer to be detected after the last corrosion, the difference between the two is the thickness of each corrosion of the silicon wafer to be detected, namely the removal amount of the corrosion thickness.
And accumulating the etching thicknesses of each time based on the etching thicknesses of the silicon wafer to be detected, so as to obtain the accumulated etching thickness of each time, namely the sum of the removal amount of the etching thicknesses, namely subtracting the thickness of the silicon wafer after each etching from the thickness of the silicon wafer without etching, namely the accumulated etching thickness of each time.
And dividing the thickness of each corrosion by the time of each corrosion based on the thickness and the time of each corrosion of the silicon wafer to be tested, thereby obtaining the corrosion rate of the silicon wafer to be tested.
The time for etching the silicon wafer is the same in the range of 70-120 s. This is because if the time is less than 70s, the number of tests is increased, the process is lengthened, the process is complicated, and the efficiency is low; if the time is more than 120s, the removal of the corrosion damage layer is accelerated, and the corrosion damage layer is not tested. Therefore, the time of each etching of the silicon wafer is preferably 100s, so that the thickness of the damaged layer can be tested, the etching times are reduced, and the testing effect is optimal.
For the same batch of silicon wafers to be tested, each silicon wafer to be tested can obtain a plurality of groups of corrosion thickness, corrosion rate and accumulated corrosion thickness after each corrosion, and then a curve is formed based on the obtained accumulated corrosion thickness and corrosion rate of the silicon wafer to be tested after each corrosion, namely the corrosion rate-accumulated corrosion thickness curve of the silicon wafer to be tested is obtained by taking the accumulated corrosion thickness of the silicon wafer to be tested as an abscissa and the corrosion rate of the silicon wafer to be tested as an ordinate.
And S3, determining whether the change rule of the corrosion rate in the corrosion rate-accumulated corrosion thickness curves of all the tested silicon wafers is consistent.
And placing the corrosion rate-accumulated corrosion thickness curves of all the tested silicon wafers in the batch in the same curve coordinate to form a plurality of corrosion rate-accumulated corrosion thickness curves. And comparing the corrosion rate-accumulated corrosion thickness curve of each silicon wafer to be tested, and observing whether the change rules of the corrosion rate in each corrosion rate-accumulated corrosion thickness curve are gradually reduced and tend to be stable along the increase of the accumulated corrosion thickness, wherein all the corrosion rates are in the first quadrant. If so, the etch rate-cumulative etch thickness curve is correct. If not, the test should be restarted.
And S4, selecting the inflection point of each silicon wafer to be tested in the corrosion rate-accumulated corrosion thickness curve when the thickness changes in a consistent manner.
Based on the change rule in the corrosion rate-accumulated corrosion thickness curve of each silicon wafer to be tested, selecting a point which appears for the first time when the corrosion rate in the corrosion rate-accumulated corrosion thickness curve of each silicon wafer to be tested is stable as an inflection point, further obtaining a plurality of inflection points, and determining whether the positions of the inflection points in the corrosion rate-accumulated corrosion thickness curve where the inflection points are located are the same, namely, whether the corrosion times corresponding to the inflection points in each corrosion rate-accumulated corrosion thickness curve are the same.
That is, the slope of a linear fit curve of the etch rate-cumulative etch thickness curve for the inflection point followed by at least 3 consecutive points should be negative and in the range of-1E-04 to 0. The difference between the etch rate at each point in the etch rate-cumulative etch thickness curve and the limit etch rate (explained in detail in the next step) is compared, and the point corresponding to the first time the difference between the two etch rates approaches 0 is the inflection point.
And S5, judging whether the selected inflection point is correct or not.
The method specifically comprises the following steps:
and taking the inflection point in the corrosion rate-accumulated corrosion thickness curve of each silicon wafer to be tested and the corrosion rates of 3 times after the inflection point, and carrying out average calculation to obtain the average corrosion rate of each silicon wafer to be tested.
And carrying out secondary average on the average corrosion rates of all the tested silicon chips to obtain the limit corrosion rates of all the tested silicon chips.
And then, by taking the limit corrosion rate as a reference, determining whether the corrosion rate of the inflection point and the corrosion rates of the adjacent 3 points behind the inflection point are respectively compared with the limit corrosion rate in the corrosion rate-accumulated corrosion thickness curve of each silicon wafer to be detected, and judging whether the selection of the inflection point is correct or not according to whether the absolute values of the differences are within a certain standard range or not.
When the corrosion rate of the inflection point in the corrosion rate-accumulated corrosion thickness curve of each silicon wafer to be tested and the corrosion rate of 3 adjacent points behind the inflection point are respectively compared with the limit corrosion rate, and the absolute value of the difference is not more than 1.5%, the selection of the inflection point of the corrosion rate-accumulated corrosion thickness curve of the silicon wafer to be tested is correct. That is, the first point with deviation less than 1.5% is the inflection point, and the deviations after the inflection point for at least 3 consecutive times are all less than 1.5%.
When the corrosion rate of the inflection point in the corrosion rate-accumulated corrosion thickness curve of any tested silicon wafer and the corrosion rate of the adjacent 3 points behind the inflection point are respectively compared with the limit corrosion rate, and half of the absolute values of the difference values are more than 1.5%, the inflection point of the corrosion rate-accumulated corrosion thickness curve of the tested silicon wafer is incorrectly selected. And returning to the step of S1 again, measuring, then re-selecting the inflection point, and judging again.
And S6, determining the average value of the accumulated corrosion thickness corresponding to the inflection point of the silicon wafer to be tested in the batch as the thickness of the surface damage layer of the silicon wafer to be tested.
And averaging the accumulated corrosion thicknesses corresponding to the inflection points of all the tested silicon wafers to obtain the average accumulated corrosion thickness. When the inflection points of at least half of the tested silicon wafers in all the tested silicon wafers meet the same standard, the average accumulated corrosion thickness corresponding to the inflection points is the thickness of the surface damage layer of the tested silicon wafers.
Specifically, the inflection point of the silicon wafer to be tested meets the following standard: in the corrosion rate-accumulated corrosion thickness curve of each silicon wafer to be tested, the curve slope of the inflection point and the curve slope of the inflection point which is continuous for at least 3 times are consistent, and the curve slope of the inflection point and the curve slope behind the inflection point are within the range of 0 +/-3E-04, so that the average accumulated corrosion thickness corresponding to the inflection point can be judged to be the surface damage layer thickness of the silicon wafer.
For the silicon wafer with the crystal orientation of <100>, the corrosion rate is greatly reduced from the beginning and gradually tends to be stable along with the increase of the corrosion times, namely the corresponding curve slopes are not more than 0, and the curve slopes are gradually increased and approach to 0 along with the increase of the corrosion times. Further, it can be seen that when the corrosion rate tends to be stable, the slope of the corresponding curve is close to 0. I.e., where the etch rate changes very slowly or nearly the same at and after the inflection point, the corresponding slope of the curve is the same and corresponds to 0. When the etching rate of the inflection point and more than 3 times of continuous etching is not changed, namely the etching rate is changed, and the slope of the curve of the inflection point and the slope of the curve of the subsequent 3 times of continuous etching are both in the range of 0 +/-3E-04, the average accumulated etching thickness at the inflection point is the surface damage layer of the silicon wafer.
For the silicon wafer with the crystal orientation of <100>, the corrosion rate in the alkaline solution changes rapidly under the influence of the lattice surface atomic density of the silicon wafer with the crystal orientation of <100>, the thickness in the alkaline corrosion solution gradually decreases along with the increase of the corrosion time, the quality continuously decreases all the time, the corrosion self-stop phenomenon can not occur, the condition of constant weight of the silicon wafer can not occur, and the thickness of the damaged layer can not be judged by taking the variable of the corrosion thickness as the reference. The method comprises the steps of forming a corrosion rate-accumulated corrosion thickness curve based on the relation between the corrosion rate and the accumulated corrosion thickness, observing the change of the corrosion rate, greatly reducing the corrosion rate and then stabilizing the corrosion rate, selecting a first test point when the slope of the curve is stable as an inflection point, confirming that the average accumulated corrosion thickness corresponding to the inflection point is the thickness of a crystal-oriented silicon wafer surface damage layer, and representing and judging the surface damage thickness by using the slope of the curve in the corrosion rate-accumulated corrosion thickness curve.
In order to ensure the above judgment result, the etching frequency after the inflection point in the etching rate-cumulative etching thickness curve is required to be at least 3 times, so that the position of the surface damage layer thickness of the silicon wafer to be tested in the batch can be accurately judged.
In order to make the method of the present invention more comprehensible to those skilled in the art, the technical solutions of the present invention will be explained in detail with reference to specific embodiments, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments.
5 pieces of P-type (100) crystal orientation silicon wafers are prepared, TTV is less than 1um, and the surfaces of the 5 silicon wafers are cleaned. Sequentially placing silicon wafers in a wafer basket at intervals, wherein 3 silicon wafers in the middle are respectively marked with an identifier S1#, an identifier S2# and an identifier S3 #; 2 pieces of the two side edges are used as non-measurement accompanying pieces, and silicon pieces are placed, as shown in figure 2. In the embodiment, before etching, the center point thicknesses of the silicon wafers of S1#, S2# and S3# are respectively tested by adopting an ADE7200 silicon wafer thickness sorter and are respectively recorded as ST100, ST200 and ST 300; because the TTV of the group of silicon wafers is smaller, namely the thickness difference between the center and the outer edge of the group of silicon wafers is smaller, the thickness of the center point can represent the thickness of the silicon wafer. Of course, corresponding tests can be carried out based on the characteristics of the thickness measuring equipment so as to obtain the thickness of the silicon wafer.
Loading a wafer basket containing 5 silicon wafers into an alkaline cleaning machine in a production line for corrosion, wherein the silicon wafer cleaning machine needs to comprise an alkaline tank and at least one pure water cleaning tank, KOH solution is placed in the alkaline tank, the mass concentration of the solution is 40-45%, the corrosion temperature is 75-85 ℃, the time for the silicon wafers to be corroded in the alkaline tank each time is set to be 100s, after the corrosion is finished, all the silicon wafers are placed into the pure water tank for cleaning through a manipulator, and after the cleaning is finished, drying is carried out; after drying, the center point thicknesses of the middle 3 silicon wafers S1#, S2# and S3# were tested, and the obtained data is the thickness of the silicon wafer after the 1 st etching.
The above steps are repeated and the etching is repeated for 5 silicon wafers for 14 times, and the center point thickness is tested for 3 silicon wafers S1#, S2# and S3# after each etching. Taking the sample of S1# as an example, the thickness after the first etching is marked as ST101, the thickness after the second etching is marked as ST102, and so on until ST114 is recorded, the total number of test data is 15, and the above repeated times are still in the same etching tank.
Processing the recorded data, wherein the removal amount of the etching thickness is the thickness before etching or the thickness after one etching on the silicon wafer minus the thickness after the current etching, taking an S1# sample as an example, the removal amount of the etching thickness at the 1 ST time is marked as m1= ST100-ST101, and the etching rate at the 1 ST time is V1= m 1/100; the etch thickness removal at time 2 is labeled m2= ST101-ST102, and etch rate at time 2V 2= m 2/100; the cumulative corrosion thickness at the 1 st time, that is, the cumulative corrosion removal amount is m1, the cumulative corrosion thickness at the 2 nd time, that is, the cumulative corrosion removal amount is m1+ m2, and so on, the corrosion rate VN = mN/100 at the nth time, and the cumulative removal amount at the nth time is m1+ m2+. once.
Determining the corrosion times of the inflection points in the experimental data as the Xth time, carrying out average calculation on the corrosion rates of the Xth time, the X +1 time, the X +2 time and the X +3 time, defining the average value obtained by calculation as the limit corrosion rate of the corrosion process, and marking the average value as Lv. In this example, Lv is the average of the limiting etch rates of three groups of wafers.
Based on the steps, 5 pieces of 12-inch <100> crystal orientation silicon wafers and 5 pieces of 8-inch <100> crystal orientation silicon wafers are selected; the thicknesses of a 12-inch <100> crystal orientation silicon wafer and an 8-inch <100> crystal orientation silicon wafer are 830 +/-10 microns, TTV is less than 1 micron, and the lightly doped silicon single crystal grinding wafer with the resistivity of 5-100 omega cm is obtained, wherein the lightly doped silicon single crystal grinding wafer is repeatedly corroded for 15 times respectively, 3 middle 12-inch <100> crystal orientation silicon wafers and 3 middle 8-inch <100> crystal orientation silicon wafers are obtained, and the final or 6 groups of data are shown in tables 1-6, and the limit corrosion rates of the wafers are calculated.
TABLE 1 test results for 12 inch <100> crystal orientation silicon wafer numbered S1#
TABLE 2 test results for 12 inch <100> crystal orientation silicon wafer numbered S2#
TABLE 3 test results for 12 inch <100> crystal orientation silicon wafer numbered S3#
TABLE 4 test results for 8 inch <100> crystal orientation silicon wafer numbered S1#
TABLE 5 test results for 8 inch <100> crystal orientation silicon wafer numbered S2#
TABLE 6 test results for 8 inch <100> crystal orientation silicon wafer numbered S3#
Drawing the corrosion rate and the accumulated corrosion thickness of each time in the results of three groups of data of the 12 inch <100> crystal orientation silicon wafer and the limit corrosion rate of the group of silicon wafers into a chart to obtain a corrosion rate-accumulated corrosion thickness curve of the 12 inch <100> crystal orientation silicon wafer, as shown in FIG. 3; the etch rate and cumulative etch thickness for each of the three sets of data for an 8 inch <100> crystal orientation wafer, as well as the ultimate etch rate for this set of wafers, are plotted in a graph to obtain an etch rate-cumulative etch thickness curve for an 8 inch <100> crystal orientation wafer, as shown in fig. 4. As can be seen from FIGS. 3 and 4, the three sets of data have good consistency of test results, the result obtained by the whole test method has good reproducibility and stable data, and the method can completely characterize the thickness of the damaged layer on the rear surface of the <100> crystal-oriented silicon wafer grinding sheet. The cumulative etch thickness on the abscissa in fig. 3 and 4 is the average of the cumulative etch thicknesses of 3 silicon wafers. Lv in FIGS. 3 and 4 is the average of the limiting etch rates of 3 wafers.
As can be seen from FIG. 3, the point corresponding to the 6 th etching is an inflection point, the calculated ultimate etching rate is 0.03597um/s, the curve slopes of 3 continuous points behind the inflection point are consistent and are close to 0, and the slopes are respectively 0, -1.96E-04, -9.36E-06 and are all within the range of 0 +/-3E-04; and the corrosion rates of the inflection point and the continuous 3 points behind the inflection point are almost equal to the limit corrosion rate Lv, and the deviations are respectively 0.986%, -0.986%, 0.959%, -1.053%, so that the accumulated thickness removal amount obtained by the 6 th time of corrosion is the thickness of the damaged layer on the surface of the 12 inch <100> crystal orientation silicon wafer, which is 27.02 um/double surface.
As can be seen from FIG. 4, the point corresponding to the 7 th etching is an inflection point, the ultimate etching rate is 0.02798um/s, the curve slopes of 3 consecutive points after the inflection point are consistent and are all close to O, which are respectively-1.32E-04, 3.85E-05 and-4.79E-05, and are all within the range of 0 +/-3E-04; and the etching rates of the inflection point and the continuous 3 points behind the inflection point are almost equal to the limit etching rate Lv, and the deviation is 0.951%, -0.389%, -0.30%, -0.509%, so that the accumulated thickness removal amount obtained by 7 th etching is the thickness of the damaged layer on the surface of the 8-inch <100> crystal orientation silicon wafer, which is 24.12 um/double surface.
In the present example, a total of 14 etching runs were performed, and the etching rates of 10 th to 14 th in FIG. 3 were substantially equivalent to those of 6 th to 9 th. The etch rates of runs 11-14 and 7-10 in FIG. 4 are substantially equivalent, so that the inflection point was identified and it was experimentally concluded that it was followed at least 3 consecutive runs.
The grinding processing equipment, grinding process, cleaning process and the like of the 8-inch <100> crystal orientation silicon wafer and the 12-inch <100> crystal orientation silicon wafer are slightly different, and the damaged layer test of the invention also reflects the difference between the two processing equipment, the product grinding process and the cleaning process, the deviation is 5.67 percent, but also reflects the different characteristics of the processes.
1. The invention designs a method for testing the thickness of a surface damage layer of a crystal orientation silicon single crystal grinding sheet, which judges whether the corrosion thickness corresponding to an inflection point is the thickness of the surface damage layer of a tested silicon wafer or not by monitoring the inflection point in a silicon wafer corrosion rate-accumulated corrosion thickness curve and the curve slopes of a plurality of times thereafter. The method can quickly analyze and monitor the depth of the surface damage layer of the silicon grinding sheet in the silicon wafer production process, provides a basis for the processing (thinning) removal amount of the semiconductor silicon wafer in different process procedures, and has the advantages of accurate judgment result, good reproducibility, convenient and quick operation and simple flow.
2. The invention has simple flow and convenient operation, can realize product test and daily monitoring only by utilizing the existing production test equipment without additionally investing large-scale analytical instruments and facilities, is economic and effective and does not increase the investment of the analytical instruments. The method can be alternately carried out in the conventional production, an experiment is not needed to be carried out independently, the existing equipment in the silicon wafer processing and production process is utilized for corrosion and test, an additional investment experiment facility is not needed, the thickness of the surface damage layer of the silicon wafer is simply and quickly analyzed and tested, the stability of the production process and the product quality are monitored, and a basis is provided for determining product parameters and process control points for the subsequent process.
3. The embodiment of the invention is a lightly doped product, but can also be popularized to a heavily doped silicon wafer test, can reflect the tiny difference of products, and has great guiding effect on process optimization, product quality control and the like.
The embodiments of the present invention have been described in detail, and the description is only for the preferred embodiments of the present invention and should not be construed as limiting the scope of the invention. All equivalent changes and modifications made within the scope of the present invention shall fall within the scope of the present invention.