CN114464533A - Super junction structure for improving EMI (electro-magnetic interference) and manufacturing method - Google Patents
Super junction structure for improving EMI (electro-magnetic interference) and manufacturing method Download PDFInfo
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- CN114464533A CN114464533A CN202111577977.6A CN202111577977A CN114464533A CN 114464533 A CN114464533 A CN 114464533A CN 202111577977 A CN202111577977 A CN 202111577977A CN 114464533 A CN114464533 A CN 114464533A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 208000032365 Electromagnetic interference Diseases 0.000 title description 12
- 238000000034 method Methods 0.000 claims abstract description 30
- 230000008569 process Effects 0.000 claims abstract description 19
- 238000005530 etching Methods 0.000 claims abstract description 17
- 238000000407 epitaxy Methods 0.000 claims abstract description 14
- 238000000151 deposition Methods 0.000 claims abstract description 12
- 238000001259 photo etching Methods 0.000 claims abstract description 11
- 238000000137 annealing Methods 0.000 claims abstract description 6
- 238000002347 injection Methods 0.000 claims abstract description 6
- 239000007924 injection Substances 0.000 claims abstract description 6
- 210000000746 body region Anatomy 0.000 claims abstract description 4
- 239000002184 metal Substances 0.000 claims abstract description 4
- 239000000758 substrate Substances 0.000 claims abstract description 4
- 238000005498 polishing Methods 0.000 claims abstract description 3
- 239000000126 substance Substances 0.000 claims abstract description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 3
- 229920005591 polysilicon Polymers 0.000 claims description 3
- 238000005457 optimization Methods 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 25
- 238000010586 diagram Methods 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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Abstract
The invention discloses a super junction structure for improving EMI and a manufacturing method thereof, wherein epitaxial layers N-and epitaxial layers N-2 are alternately grown on an N + substrate; on the surface of the N-epitaxy, growing a P-type epitaxy after etching a deep trench, and performing a CMP (chemical mechanical polishing) process to form a super junction structure with N columns and P columns alternately; injecting a body region through a PW photoetching plate and annealing to form a PWELL region, depositing a field oxide layer and etching back to form a gate structure of the device; injecting As and annealing to form a source N-source of the device; and depositing ILD and etching back, carrying out hole injection, and finally depositing metal and etching back to form the final structure of the device. According to the invention, through optimization of the epitaxial structure of the device, the C-V characteristic of the device is improved, the EMI performance is improved, the characteristic on-resistance of the device is reduced, the on-loss of the device is reduced, and the efficiency of the device is improved.
Description
Technical Field
The invention belongs to the technical field of semiconductor discrete devices, and relates to a super junction structure for improving EMI (electro-magnetic interference) by a super junction and a manufacturing method thereof, which can effectively improve the capacitance characteristic of a super junction MOSFET (metal-oxide-semiconductor field effect transistor), optimize the EMI performance and reduce the characteristic on-resistance of a device.
Background
The higher on-resistance of the conventional VDMOS device increases the static power consumption of the switch circuit, its RDS (on) is BV2.5In proportion, RDS (on) of the super junction MOSFET is BV1.3Proportionally, the RDS (on) under the same withstand voltage condition is much lower than that of the common MOSFET, and meanwhile, the chip area under the same Ron condition is smaller, the switching loss is lower, and the overall efficiency is high. The super junction device is wideThe power supply or the adapter is widely applied to power supplies or adapters of consumer electronic products such as computers, mobile phones, lighting, liquid crystal or plasma televisions, game machines and the like.
At present, there are two main process paths of a super junction MOSFET device: the super junction process comprises a super junction process of multiple times of epitaxy and injection, and a super junction process of groove etching and filling. The multiple epitaxy and injection processes have more photoetching plates and more photoetching times, the currently advanced multiple epitaxy process usually needs twenty times of photoetching steps, the quality of each epitaxy and the interlayer alignment difficulty are high, the thermal budget is high, the production period is long, the cost is higher, but the processes are all semiconductor standard processes, and the process implementation difficulty is low; the super junction process for etching and filling the groove has the advantages of fewer layers of the used photoetching plates, simple process steps, short production period and low production cost, but the requirement on process control for etching the groove with the extremely high depth-to-width ratio and filling is high, and the process realization difficulty is high. The two process paths are developed in the direction of continuously reducing the cell size of the device, and the reduction of the cell size can continuously improve the power density and accelerate the switching speed. The power MOSFET is used as a power switch tube, works in an on-off fast cycle switching state, has the voltage and current which are all changed rapidly, is a main interference source of electric field coupling and magnetic field coupling, is one of main sources of circuit EMI (electro-magnetic interference) of a switching power supply and the like, and has the important importance on the EMI performance optimization of deep groove etching and filling process structures due to the difference of structures and processes.
Disclosure of Invention
The invention aims to provide a super-junction MOSFET structure and a manufacturing method thereof.
The specific implementation method comprises the following steps:
a manufacturing method of a super junction MOSFET structure is characterized in that:
the method comprises the following steps:
step 1: growing an epitaxial layer N-on the N + substrate, and then growing an epitaxial layer N-2;
step 2: continuously growing an epitaxial layer N-on the epitaxial layer N-2, further growing an epitaxial layer N-2, and continuously growing the epitaxial layer N-until the target epitaxial thickness is reached;
and step 3: on the surface of the N-epitaxy, a Trench is etched through a Trench photoetching plate, a P-type epitaxy with a certain concentration is grown to fill the Trench, a CMP (chemical mechanical polishing) process is carried out, the P-type epitaxy and the N-type epitaxy outside the Trench are removed together, and a super junction structure with N columns and P columns alternating is formed;
and 4, step 4: injecting a body region through a PW photoetching plate and annealing to form a PWELL region, depositing a field oxide layer and etching back, and depositing and etching back a gate oxide Gox and polysilicon to form a gate structure of the device;
and 5: injecting As and annealing to form a source N-source of the device;
step 6: and depositing ILD and etching back, carrying out hole injection, and finally depositing metal and etching back to form the final structure of the device.
The epitaxial layer N-resistivity is higher than the epitaxial layer N-2.
The resistivity of the epitaxial layer N-is 2 times of that of the epitaxial layer N-2.
The thickness of the epitaxial layer N-2 is 2 um.
The N-thickness of the epitaxial layer grown for three times is reduced in sequence.
In step 1, the N-thickness of the epitaxial layer is 60% of the target epitaxial thickness.
In step 2, when the epitaxial layer N-is grown for the first time, the thickness reaches 90% of the target epitaxial thickness.
A super junction MOSFET structure is obtained by the manufacturing method.
The invention has the following advantages:
according to the invention, on the premise of not changing the existing super junction process route and not needing to design and change the photoetching mask again, the C-V characteristic of the device is improved through the optimization of the epitaxial structure of the device, so that the EMI performance is improved, meanwhile, the characteristic on-resistance of the device is reduced, the on-loss of the device is reduced, and the efficiency of the device is improved.
Drawings
FIG. 1 is a schematic diagram of step 1.
FIG. 2 is a schematic diagram of step 2.
FIG. 3 is a schematic diagram of step 3.
FIG. 4 is a schematic diagram of step 4.
FIG. 5 is a schematic diagram of step 5.
FIG. 6 is a schematic diagram of step 6.
FIG. 7 is a graph of the improved Cgd capacitance characteristics of the present invention.
Detailed Description
The present invention will be described in detail with reference to specific embodiments.
The invention relates to a manufacturing method of a super junction MOSFET structure, which comprises the following steps:
step 1: referring to fig. 1, an epitaxial N-with a slightly higher resistivity, whose thick bottom is 60% of the target epitaxial thickness and resistivity is R, is grown on an N + substrate, and an epitaxial layer N-2 with a thickness of 2um, whose resistivity is 0.5 times that of the epitaxial layer, that is, resistivity is 0.5R, is grown at the same time.
Step 2: referring to fig. 2, an epitaxial layer N-2 with resistivity of R is continuously grown on the epitaxial layer N-2 until the thickness reaches 90% of the target epitaxial thickness, and then an epitaxial layer N-2 with resistivity of 2um is grown with resistivity of 0.5 times that of the epitaxial layer, that is, the resistivity is 0.5R, and the epitaxial layer N-is continuously grown until the target epitaxial thickness is reached.
And step 3: referring to fig. 3, on the surface of the N-epi, a Trench is etched by a Trench photolithography plate, a P-type epi with a certain concentration is grown to fill the Trench, a CMP process is performed, and the P-type epi and the N-type epi outside the Trench are removed together to form a super junction structure with alternating N columns and P columns.
And 4, step 4: referring to fig. 4, a body region is implanted through a PW photoetching plate and annealed to form a PWELL region, a field oxide layer is deposited and etched back, and a gate structure of the device is formed through deposition and etching back of gate oxide Gox and polysilicon.
And 5: referring to fig. 5, As is implanted and annealed to form the source N-source of the device.
Step 6: referring to fig. 6, ILD is deposited and etched back, hole injection, and finally metal is deposited and etched back to form the final structure of the device.
Referring to fig. 7, through design and verification of the invention, it is found that, compared with a conventional super junction structure, the C-V characteristic of the device is improved due to the optimization of the doping distribution of the internal epitaxial layer, the capacitance change in the low-voltage section of the VDS is relatively smooth, the capacitance value in the high-voltage section of the VDS is also obviously improved, the EMI problem of the device in the fast switching process can be improved, and meanwhile, due to the reduction of the concentration of the effective drift region, the characteristic on-resistance is reduced by about 6%, and the conduction loss of the device is reduced.
The invention is not limited to the examples, and any equivalent changes to the technical solution of the invention by a person skilled in the art after reading the description of the invention are covered by the claims of the invention.
Claims (8)
1. A manufacturing method of a super junction MOSFET structure is characterized in that:
the method comprises the following steps:
step 1: growing an epitaxial layer N-on the N + substrate, and then growing an epitaxial layer N-2;
step 2: continuously growing an epitaxial layer N-on the epitaxial layer N-2, further growing an epitaxial layer N-2, and continuously growing the epitaxial layer N-until the target epitaxial thickness is reached;
and step 3: on the surface of the N-epitaxy, a Trench is etched through a Trench photoetching plate, a P-type epitaxy with a certain concentration is grown to fill the Trench, a CMP (chemical mechanical polishing) process is carried out, the P-type epitaxy and the N-type epitaxy outside the Trench are removed together, and a super junction structure with N columns and P columns alternating is formed;
and 4, step 4: injecting a body region through a PW photoetching plate and annealing to form a PWELL region, depositing a field oxide layer and etching back, and depositing and etching back a gate oxide Gox and polysilicon to form a gate structure of the device;
and 5: injecting As and annealing to form a source N-source of the device;
step 6: and depositing ILD and etching back, carrying out hole injection, and finally depositing metal and etching back to form the final structure of the device.
2. The method for manufacturing a super junction MOSFET structure according to claim 1, wherein:
the epitaxial layer N-resistivity is higher than the epitaxial layer N-2.
3. The method for manufacturing a super junction MOSFET structure according to claim 2, wherein:
the resistivity of the epitaxial layer N-is 2 times of that of the epitaxial layer N-2.
4. The method for manufacturing a super junction MOSFET structure according to claim 3, wherein:
the thickness of the epitaxial layer N-2 is 2 um.
5. The method for manufacturing a super junction MOSFET structure according to claim 1, wherein:
the N-thickness of the epitaxial layer grown for three times is reduced in sequence.
6. The method for manufacturing a super junction MOSFET structure according to claim 1, wherein:
in step 1, the N-thickness of the epitaxial layer is 60% of the target epitaxial thickness.
7. The method for manufacturing a super junction MOSFET structure according to claim 1, wherein:
in step 2, when the epitaxial layer N-is grown for the first time, the thickness reaches 90% of the target epitaxial thickness.
8. A super junction MOSFET structure obtained by the method of manufacture of claim 1.
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| CN202111577977.6A CN114464533A (en) | 2021-12-22 | 2021-12-22 | Super junction structure for improving EMI (electro-magnetic interference) and manufacturing method |
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| CN202111577977.6A CN114464533A (en) | 2021-12-22 | 2021-12-22 | Super junction structure for improving EMI (electro-magnetic interference) and manufacturing method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115172466A (en) * | 2022-09-05 | 2022-10-11 | 深圳市威兆半导体股份有限公司 | Novel super-junction VDMOS structure and preparation method thereof |
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2021
- 2021-12-22 CN CN202111577977.6A patent/CN114464533A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115172466A (en) * | 2022-09-05 | 2022-10-11 | 深圳市威兆半导体股份有限公司 | Novel super-junction VDMOS structure and preparation method thereof |
| CN115172466B (en) * | 2022-09-05 | 2022-11-08 | 深圳市威兆半导体股份有限公司 | Novel super-junction VDMOS structure and preparation method thereof |
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