CN114462353A

CN114462353A - Chip memory power consumption optimization method and device, electronic equipment and storage medium

Info

Publication number: CN114462353A
Application number: CN202210265614.7A
Authority: CN
Inventors: 段光生; 许俊; 师克龙
Original assignee: Suzhou Centec Communications Co Ltd
Current assignee: Suzhou Centec Communications Co Ltd
Priority date: 2022-03-17
Filing date: 2022-03-17
Publication date: 2022-05-10

Abstract

The embodiment of the invention provides a chip memory power consumption optimization method, a device, electronic equipment and a storage medium, belonging to the technical field of electronics, the method comprises the steps of extracting the design information of a required logic memory, calculating at least one group of preselected indexes according to the compiling indexes of the physical memory of the same type as the logic memory and the design information, obtaining the preselected memory meeting the initial selection condition from a plurality of physical memories meeting the preselected indexes of each group, calculating the initial selection performance of the logic memory formed by the preselected memories, obtaining a target memory meeting the optimal power consumption condition from the physical memories meeting the preselected indexes of each group based on the initial selection performance, designing the required logic memory based on the target memory to obtain a chip memory power consumption optimization scheme, and ensuring that the total area of the chip memory is as optimal as possible, the power consumption of the memory is reduced as much as possible.

Description

Chip memory power consumption optimization method and device, electronic equipment and storage medium

Technical Field

The invention relates to the technical field of electronics, in particular to a chip memory power consumption optimization method and device, electronic equipment and a storage medium.

Background

A chip is a general term for semiconductor device products, and is an integrated circuit in nature. For a large network switching chip with ultra-high performance and ultra-high bandwidth under advanced manufacturing processes, the memory power consumption occupies a significant dominant position in the total power consumption of the chip. The excessive total power consumption can greatly increase the complexity of chip physical design and system design, and also can bring about the increase of dynamic voltage drop of the chip, the silicon chip of the chip and the capacitance added on the package are many, the time sequence is difficult to meet the requirement, the current passed by a single solder ball is too large, the total quantity of the power solder balls is insufficient, and the requirement of a system heat dissipation scheme is too high.

However, the current chip design method has a problem that the power consumption of the designed chip memory is high.

Disclosure of Invention

In view of the above, the present invention provides a method, an apparatus, an electronic device and a storage medium for optimizing power consumption of a chip memory, which can solve the problem of high power consumption of a chip memory designed by the current chip design method.

In order to achieve the above object, the embodiments of the present invention adopt the following technical solutions.

In a first aspect, an embodiment of the present invention provides a method for optimizing power consumption of a chip memory, which adopts the following technical solution.

A method for optimizing power consumption of a chip memory, the method comprising:

extracting design information of a required logic memory, wherein the design information comprises address depth and data width;

calculating at least one group of preselected indexes according to the compiling indexes of a physical memory of the same type as the logic memory and the design information, wherein each group of preselected indexes comprises address depth and data width;

obtaining a preselected memory meeting a primary selection condition from a plurality of physical memories meeting each set of preselected indexes, wherein the primary selection condition comprises a performance condition and has the smallest area;

calculating the initial selection performance of a logic memory formed by the pre-selection memory, wherein the initial selection performance comprises a first area, a first power consumption, an area loss coefficient and a power consumption optimization coefficient;

based on the initial selection performance, obtaining a target memory meeting the optimal power consumption condition from the physical memories meeting the pre-selected indexes of each group;

and designing the logic memory based on the target memory to obtain a chip memory power consumption optimization scheme.

Further, the power consumption optimal condition includes an area condition and a power consumption condition;

the step of obtaining a target memory satisfying the optimal power consumption condition from the physical memories meeting the preselected indexes of each group based on the initial selection performance comprises the following steps:

polling each physical memory meeting the preselected indexes for each group of preselected indexes, and calculating a second area and a second power consumption of a logic memory formed by the physical memories if the currently polled physical memory meets the performance condition;

calculating an area condition according to the first area and the area loss coefficient, and calculating a power consumption condition according to the first power consumption and the power consumption optimization coefficient;

if the second area is smaller than the area condition and the second power consumption is smaller than the power consumption condition, taking the currently polled physical memory as a pre-selection memory and updating the initial selection performance;

based on the updated initial selection performance, after all the physical memories meeting the preselected indexes are polled, each physical memory meeting the next group of preselected indexes is continuously polled until all the physical memories meeting all the preselected indexes are polled;

and after the polling is finished, taking the final pre-selected memory as a target memory.

Further, the area condition includes: a ═ A_c×(1+X_i) (ii) a Wherein A represents an area condition, A_cDenotes a first area, X_iRepresents the area loss coefficient;

the power consumption conditions include: p ═ P_c×(1-Y_i)；

Wherein P represents a power consumption condition, P_cDenotes the first power consumption, Y_iRepresenting power consumption optimization coefficients.

Further, the design information further comprises an instantiation time;

the step of calculating the initial selection performance of the logic memory formed by the pre-selection memory comprises the following steps:

calculating a first area and a first power consumption of a logic memory formed by the preselected memory according to the compiling index of the preselected memory and the instantiation times;

calculating the area ratio and the power consumption ratio of a logic memory formed by the pre-selected memory on a chip according to the first area and the first power consumption;

setting an area loss coefficient matched with the size relation based on the size relation between the area ratio and a preset first group of threshold values;

and setting a power consumption optimization coefficient matched with the size relation based on the size relation between the power consumption ratio and a preset second group of threshold values.

Further, the step of calculating at least one set of pre-selected metrics according to the compiling metrics of the physical memory of the same type as the logical memory and the design information includes:

obtaining a first range value of an address depth segmentation coefficient and a second range value of a data width segmentation coefficient according to the address depth and the data width of the logic memory and a compiling index of a physical memory of the same type;

obtaining a plurality of groups of segmentation coefficients according to the first range value and the second range value, wherein each group of segmentation coefficients comprises an address depth segmentation coefficient and a data width segmentation coefficient;

each set of slicing coefficients determines a set of preselected metrics in conjunction with the address depth and the data width of the logical memory.

Further, the compiling indexes of the same type of physical memory comprise a maximum supported address depth, a minimum supported address depth, a maximum supported data width and a minimum supported data width;

the step of obtaining a first range value of an address depth splitting coefficient and a second range value of a data width splitting coefficient according to the address depth and the data width of the logical memory and a compiling index of a physical memory of the same type includes:

obtaining a first range value of an address depth segmentation coefficient according to a quotient between the address depth of the logic memory and the minimum support address depth and a quotient between the address depth of the logic memory and the maximum support address depth;

and obtaining a second range value of the data width segmentation coefficient according to the quotient between the data width of the logic memory and the minimum support data width and the quotient between the data width of the logic memory and the maximum support data width.

Further, the step of obtaining a preselected memory satisfying a preliminary selection condition from a plurality of physical memories satisfying the respective sets of preselected criteria includes:

initializing a first unit storage area value of the selected memory to infinity;

polling each physical memory according with the preselected indexes according to the sequence of small area to large area for each group of preselected indexes, and calculating a second unit storage area value of the currently polled physical memory if the currently polled physical memory meets the performance condition;

if the second unit storage area value is smaller than the first unit storage area value, taking the currently polled physical memory as a selected memory, and updating the first unit storage area value into the second unit storage area value;

after all the physical memories meeting the preselected indexes are polled based on the updated first unit storage area value, continuing to poll each physical memory meeting the next group of preselected indexes until all the physical memories meeting all the preselected indexes are polled;

and after the polling is finished, taking the final selected memory as a pre-selection memory.

In a second aspect, an embodiment of the present invention provides a device for optimizing power consumption of a chip memory, which adopts the following technical solution.

A power consumption optimization device of a chip memory comprises a preselection module, a final selection module and an optimization module;

the preselection module is used for extracting the design information of the required logic memory, and the design information comprises address depth, data width and instantiation times;

the preselection module is further used for calculating at least one group of preselection indexes according to the compiling indexes of the physical memory of the same type as the logic memory and the design information, wherein each group of preselection indexes comprises address depth and data width;

the preselection module is further used for obtaining a preselection memory meeting the initial selection condition from a plurality of physical memories meeting each group of preselection indexes, wherein the initial selection condition comprises a performance condition and has the smallest area;

the final selection module is used for calculating the initial selection performance of a logic memory formed by the pre-selection memories, and obtaining a target memory meeting the optimal power consumption condition from the physical memories meeting each group of pre-selection indexes based on the initial selection performance, wherein the initial selection performance comprises a first area, a first power consumption, an area loss coefficient and a power consumption optimization coefficient;

and the optimization module is used for designing the required logic memory based on the target memory so as to obtain a power consumption optimization scheme of the chip memory.

In a third aspect, an embodiment of the present invention provides an electronic device, which adopts the following technical solutions.

An electronic device comprising a processor and a memory, the memory storing machine executable instructions executable by the processor to implement a chip memory power consumption optimization method as described in the first aspect.

In a fourth aspect, an embodiment of the present invention provides a storage medium, which adopts the following technical solutions.

A storage medium having stored thereon a computer program which, when executed by a processor, implements a chip memory power consumption optimization method as described in the first aspect.

According to the chip memory power consumption optimization method, device, electronic equipment and storage medium provided by the embodiment of the invention, at least one group of preselected indexes are obtained according to the design information of a logic memory required and the compiling indexes of physical memories of the same type, the physical memory which meets the performance condition and has the smallest area is selected as the preselected memory from a plurality of physical memories which meet the preselected indexes, then the target memory with the optimal power consumption is obtained from the plurality of physical memories which meet the preselected indexes according to the initial selection performance of the logic memory formed by the preselected memories, on the premise of meeting the performance condition, the area of the target memory is enabled to be as small as possible, the power consumption is enabled to be as optimal as possible, and further, the logic memory is designed according to the target memory, so that the design scheme of the chip memory can be realized under the condition that the total area of the chip memory is enabled to be as optimal as possible, the power consumption of the memory is reduced as much as possible.

In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.

Fig. 1 is a block diagram illustrating a system for optimizing power consumption of a chip memory according to an embodiment of the present invention.

Fig. 2 is a schematic flow chart illustrating a method for optimizing power consumption of a chip memory according to an embodiment of the present invention.

Fig. 3 shows a schematic flow chart of a part of the sub-steps of step S102 in fig. 2.

Fig. 4 shows a schematic flow chart of a part of the sub-steps of step S103 in fig. 2.

Fig. 5 shows a schematic flow chart of a part of the sub-steps of step S104 in fig. 2.

Fig. 6 shows a schematic flow chart of a part of the sub-steps of step S105 in fig. 2.

Fig. 7 is a block diagram illustrating a chip memory power consumption optimization apparatus according to an embodiment of the present invention.

Fig. 8 is a block diagram of an electronic device according to an embodiment of the present invention.

Icon: 100-chip memory power consumption optimization system; 110-a terminal; 120-a server; 130-chip memory power consumption optimization means; 140-a pre-selection module; 150-final selection module; 160-an optimization module; 170-electronic device.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.

It is noted that relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

For a large network switching chip with ultra-high performance and ultra-high bandwidth under an advanced manufacturing process, the memory power consumption occupies a significant dominant position in the total power consumption of the chip. The excessive total power consumption can increase the complexity of the physical design and the system design of a chip and also can increase the dynamic voltage drop of the chip, the silicon chip and the packaging of the chip have a large number of capacitors, the time sequence is difficult to meet the requirements, the current passing through a single solder ball is too large, the total number of the power solder balls is insufficient, and the requirement of a system heat dissipation scheme is too high.

The size of the memory power consumption is a key factor for successful chip design and chip competitiveness. However, the current chip design method has the problem that the designed chip memory has high power consumption.

Based on the above consideration, the embodiments of the present invention provide a power consumption optimization scheme for a chip memory, which can reduce power consumption of the chip memory. Hereinafter, description will be made in terms of a chip memory power consumption optimization method and the like.

The power consumption optimization scheme of the chip memory provided by the embodiment of the invention can be applied to the power consumption optimization system 100 of the chip memory shown in fig. 1, the chip upgrading system comprises a terminal 110 and a server 120, the server 120 comprises a database, and the database stores information of various physical memories in the market. Wherein the terminal 110 and the server 120 can communicate through a network. The terminal 110 sends the design information of the required logic memory to the server 120, and the server 120 obtains the target memory with the optimal area and power consumption by adopting a chip memory power consumption optimization method according to the design information.

The terminal 110 may be, but is not limited to, various personal computers, notebook computers, smart phones, tablet computers, and portable wearable devices, and the server 120 may be implemented by an independent server 120 or a server 120 cluster formed by a plurality of servers 120.

It should be noted that the method for optimizing the power consumption of the chip memory provided in the embodiment of the present invention may also be applied to the terminal 110, and at this time, the power consumption of the chip memory may be optimized only by the terminal 110.

In one embodiment, as shown in FIG. 2, a method for optimizing power consumption of a chip memory is provided. This embodiment is mainly illustrated by applying the method to the server 120 in fig. 1.

S101, extracting design information of a required logic memory.

Wherein the design information includes an address depth and a data width.

It should be understood that more than one logical memory may be required. When the required logical storage is plural, the design information of each required logical storage may be extracted one by one.

S102, at least one group of preselected indexes is calculated according to the compiling indexes of the physical memory of the same type as the logic memory and the design information.

Wherein each set of preselected metrics includes an address depth and a data width.

The number of sets of preselected criteria is determined by the design information of the required logical memory and the compilation criteria of the physical memory of the same type as the logical memory.

After determining the type of the logical storage, compiling indexes of various physical storages belonging to the same type as the logical storage can be extracted from the database.

S103, obtaining a pre-selection memory meeting the initial selection condition from a plurality of physical memories meeting each group of pre-selection indexes.

Wherein the initial selection condition comprises a performance condition and the area is minimum.

After the preselected indicators are obtained, all physical memories that meet each set of preselected indicators can be extracted from the database. Meeting a preselected criteria refers to having an address width and a data width in the preselected criteria.

S104, calculating the initial selection performance of the logic memory formed by the pre-selection memory.

The initial selection performance comprises a first area, a first power consumption, an area loss coefficient and a power consumption optimization coefficient.

The address depth and data width of the required logical memory are generally much larger than those of the physical memory, and therefore, one logical memory is generally composed of a plurality of physical memories.

And S105, obtaining a target memory meeting the optimal power consumption condition from the physical memories meeting all groups of preselected indexes based on the initial selection performance.

And S106, designing the required logic memory based on the target memory to obtain a power consumption optimization scheme of the chip memory.

In the method for optimizing the power consumption of the chip memory, according to the design information of the required logic memory, and compiling the indices of the physical memories of the same type to obtain at least one set of preselected indices, selecting, from a plurality of physical memories that meet the preselected indices, selecting the physical memory which meets the performance condition and has the smallest area as a pre-selection memory, obtaining a target memory with the optimal power consumption from a plurality of physical memories which meet pre-selection indexes according to the initial selection performance of a logic memory formed by the pre-selection memory, on the premise of meeting performance conditions, the area of the target memory is as small as possible, the power consumption is as optimal as possible, and then the logic memory is designed according to the target memory, so that the design scheme of the chip memory can reduce the power consumption of the memory as far as possible under the condition of ensuring that the total area of the chip memory is as optimal as possible.

When there are a plurality of required logic memories, the target memory of each required logic memory is obtained by adopting the steps S101 to S106 for each required logic memory, so that power consumption optimization of the chip memory can be completed.

The design information of the required logic memory further includes a port. With respect to step S102, the type of logical memory is determined according to the port. For example, if the design information includes a read port and a write port, the physical memory of the same type as the logical memory also includes a read port and a write port, and if the design information includes only a write port, the physical memory of the same type as the logical memory also includes only a write port.

The method for calculating the preselected index in step S102 may be flexibly selected, for example, the preselected index may be calculated by combining with a neural network, or the preselected index may be calculated according to a preset calculation rule. In one embodiment, referring to fig. 3, a flow chart of a part of the sub-steps of step S102 is shown, and at least one set of preselected indicators is calculated through the following steps.

S102-1, obtaining a first range value of the address depth segmentation coefficient and a second range value of the data width segmentation coefficient according to the address depth and the data width of the logic memory and the compiling index of the physical memory of the same type.

And S102-2, obtaining a plurality of groups of segmentation coefficients according to the first range value and the second range value.

Each group of segmentation coefficients comprises an address depth segmentation coefficient and a data width segmentation coefficient.

For example, if there are 5 address depth slicing coefficients in the first range of values and 5 data width slicing coefficients in the second range of values, the slicing coefficients have a total of 5 × 5 to 25 groups.

And S102-3, determining a group of preselected indexes by combining each group of segmentation coefficients with the address depth and the data width of the logic memory.

Wherein the preselected metrics include a preselected address depth Di and a preselected data width Wi.

And assuming that a group of segmentation coefficients is { D _ div, W _ div }, calculating the segmentation depth D/D _ div and the segmentation width W/W _ div corresponding to the group of segmentation coefficients. The address depth of the physical memory existing in the market closest to the slice depth D/D _ div is rounded up to obtain the pre-selected address depth Di. Similarly, the address depth of the physical memory which is closest to the sliced width W/W _ div and exists in the market is fetched upward to obtain the preselected data width Wi.

Like the above steps S102-1 to S102-3, a plurality of sets of pre-selected indicators of the logical memory satisfying the requirement and the physical memory actually existing can be obtained.

Further, the compilation indexes of the same type of physical memory may include a maximum supported address depth, a minimum supported address depth, a maximum supported data width, and a minimum supported data width. Based on this, the above step S102-1 can be realized by the following method.

And obtaining a first range value of the address depth segmentation coefficient according to the quotient between the address depth of the logic memory and the minimum support address depth and the quotient between the address depth of the logic memory and the maximum support address depth.

For example, assuming that the address depth of the required logical memory is D and the data width is W, the minimum supported address depth is D in the physical memory which is in the same type as the required logical memory in the market_rminMaximum supported address depth of D_rmaxMaximum supported data width of W_rmaxThe minimum supported data width is W_rminThen, the address depth segmentation coefficient and the data width segmentation coefficient are calculated by the following formulas:

and

thus, the first range value of the address depth slicing coefficient is D _ div ═ D_min，D_min+1，…，D_maxA second range value of the data width slicing coefficient is W _ div ═ W_min，W_min+1，…，W_max}。

Performance requirements may also be included in the design information. It should be understood that, in step S103, the performance condition in the initial selection condition may be a performance requirement of the logic memory that meets the requirement under all the operating conditions.

For S103, the mode of obtaining the preselection memory meeting the initial selection condition may be flexibly selected, for example, the preselection memory may be selected according to a machine learning model, or the preselection memory may be selected according to a preset rule. In one embodiment, referring to fig. 4, which is a schematic flow chart of a part of the sub-steps of step S103, obtaining a pre-selected memory satisfying the initial selection condition from a plurality of physical memories meeting each set of pre-selected indicators is achieved by the following steps.

S103-1, initializing the first unit storage area value of the selected memory to infinity.

Initializing the first unit storage area value Rc to infinity provides a sufficiently large judgment range for the polling process, which in turn helps to improve the superiority of the selected pre-selected memory.

And S103-2, polling each physical memory conforming to the preselected indexes according to the sequence of small area to large area for each group of preselected indexes.

S103-3, judging whether the physical memory polled currently meets the performance condition. If not, step S103-5 is executed, and if yes, step S103-4 is executed.

If the currently polled physical memory meets the performance requirement of the required logical memory under all conditions, the currently polled physical memory is determined to meet the performance condition.

S103-5, judging whether the physical memory polled currently is the last physical memory meeting the preselected index. If not, S103-7 is executed. If yes, go to step S103-9.

S103-7, continuing to poll the next physical memory meeting the preselected index. After step S103-7, step S103-3 is performed.

And S103-9, polling a plurality of physical storages according with the next group of preselected indexes in the sequence from small area to large area.

S103-4, calculating a second unit storage area value of the currently polled physical storage.

If the area of the physical memory currently polled is Ak and the total number of bits is Bi, the second unit memory area value is Rk ═ Ak/Bi, where Rk represents the second memory area value. Wherein the value of the total number of bits Bi is equal to the product of the address depth and the data width.

S103-6, judging whether the second unit storage area value is smaller than the first unit storage area value. If not, step S103-5 is executed. If yes, go to step S103-8.

S103-8, the physical memory polled currently is used as the selected memory, and the first unit storage area value is updated to the second unit storage area value. And executes S103-5 after the execution of S103-8 ends.

That is, if Rk < Rc, Rc is made to be Rk.

After all the physical memories meeting the preselection indexes of each group are polled through steps S103-1 to S103-9, namely after the polling is finished, the final selected memory is used as the preselection memory.

Through the steps S103-1 to S103-9, the performance requirement of the logic memory which can meet the requirement under any condition can be selected from the physical memories meeting all the preselected indexes, and the physical memory with the smallest area is used as the preselected memory, so that the area ratio of the chip memory is reduced.

The design information of the required logic memory further includes an instantiation number. In addition, in one embodiment, referring to fig. 5, a flow chart of a part of the sub-steps of step S104 is shown, and the calculation of the initial selection performance of the logic memory formed by the pre-selection memory is realized through the following steps.

S104-1, calculating a first area and a first power consumption of a logic memory formed by the pre-selected memory according to the compiling index and the instantiation times of the pre-selected memory.

Alternatively, the area calculation formula may be used to calculate the first area of the logic memory formed by the pre-selection memory, and the power consumption calculation formula may be used to calculate the first power consumption of the logic memory formed by the pre-selection memory.

The area calculation formula includes:

wherein Ai represents a first area of a logic memory formed by the pre-selection memory, N represents an instantiation time, Ap represents an area of the pre-selection memory, Dp represents an address depth of the pre-selection memory, and Wp represents a data width of the pre-selection memory.

The attack calculation formula comprises:

where Pi denotes a first power consumption of a logic memory constituted by the preliminary memory, and Pp denotes a power consumption of the preliminary memory.

And S104-2, calculating the area ratio and the power consumption ratio of the logic memory formed by the pre-selected memory on the chip according to the first area and the first power consumption.

If the area of the whole chip is At0, the area ratio of the logic memory formed by the pre-selection memory on the chip is Ai/At0, and if the power consumption of the whole chip is Pt0, the power consumption ratio of the logic memory formed by the pre-selection memory on the chip is Pi/Pt 0.

And S104-3, setting an area loss coefficient matched with the size relation based on the size relation between the area occupation ratio and the preset first group of threshold values.

And S104-4, setting a power consumption optimization coefficient matched with the size relation based on the size relation between the power consumption ratio and the preset second group of threshold values.

A first set of thresholds may be provided comprising a plurality of area thresholds having a size relationship therebetween, each two adjacent area thresholds having an area class range therebetween, each area class range having an area loss factor matching therewith. If the area ratio falls between two adjacent area thresholds, that is, if the area ratio is larger than the smaller area threshold and smaller than the larger area threshold, the area loss coefficient matching the area class range is used as the area loss coefficient.

Similarly, a second group of thresholds comprising a plurality of power consumption thresholds can be set, the plurality of power consumption thresholds have size relationship, a power consumption level range is formed between every two power consumption thresholds with adjacent sizes, and each power consumption level range has a power consumption optimization coefficient matched with the power consumption level range. If the power consumption ratio falls between two adjacent power consumption thresholds, namely the power consumption ratio is larger than the smaller power consumption threshold and smaller than the larger power consumption threshold, the power consumption optimization coefficient matched with the power consumption grade range is used as the power consumption optimization coefficient

The area loss calculation formula corresponding to each area grade range can be set, the power consumption grade range is set with the power consumption optimization calculation formula corresponding to each power consumption grade range, the area loss coefficient is calculated based on the area loss calculation formula, and the power consumption optimization coefficient is calculated based on the power consumption optimization calculation formula.

In other embodiments, the area loss coefficient and the power consumption optimization coefficient are obtained by using a neural network or according to a preset calculation rule.

Further, the power consumption optimum condition includes an area condition and a power consumption condition. Based on this, for S105, the method of obtaining the target memory may be flexibly selected, for example, the target memory may be obtained according to a preset rule, or the target memory may be determined by using a method such as a neural network.

In one embodiment, referring to fig. 6, which is a flow chart illustrating a part of the sub-steps of step S105, a target memory satisfying the optimal power consumption condition can be obtained from the physical memories meeting each set of pre-selected indexes based on the initial selection performance.

And S105-1, polling each physical memory which accords with the preselected index for each group of preselected indexes.

Wherein each physical memory meeting a preselected criteria may be polled in order of decreasing area.

S105-2, judging whether the physical memory polled currently meets the performance condition. If not, step S105-3 is executed, and if yes, step S105-4 is executed.

The method includes that when a currently polled physical storage meets the performance requirement of a required logical storage under all conditions, the currently polled physical storage can be judged to meet the performance condition.

And S105-3, judging whether the physical memory polled currently is the last physical memory meeting the preselected index. If not, step S105-5 is executed, and if yes, step S105-7 is executed.

S105-5, continuing to poll the next physical memory meeting the preselected index. After step S105-5, step S105-3 is performed.

And S105-7, polling a plurality of physical storages according with the next group of preselected indexes in the sequence from small area to large area.

And S105-4, calculating a second area and a second power consumption of a logic memory formed by the physical memory, calculating an area condition according to the first area and the area loss coefficient, and calculating a power consumption condition according to the first power consumption and the power consumption optimization coefficient.

Alternatively, the second area of the logical memory formed by the currently polled physical memory may be calculated by using the following first calculation formula, and the second power consumption of the logical memory formed by the currently polled physical memory may be calculated by using the following second calculation formula.

The first calculation formula includes:

wherein, Aj represents a second area of a logic memory formed by the currently polled physical memory, N represents an instantiation frequency, Ak represents an area of the currently polled physical memory, Dk represents an address depth of the currently polled physical memory, and Wk represents a data width of the currently polled physical memory.

The second calculation formula includes:

where Pj represents a second power consumption of the logical memory constituted by the currently polled physical memory, and Pk represents a power consumption of the currently polled physical memory.

Based on this, the area conditions include: a ═ A_c×(1+X_i). Wherein A represents an area condition, A_cDenotes a first area, X_iThe area loss factor is shown.

The power consumption conditions include: p ═ P_c×(1-Y_i). Wherein P represents a power consumption condition, P_cDenotes the first power consumption, Y_iRepresenting power consumption optimization coefficients.

S105-6, judging whether the second area is smaller than the area condition and whether the second power consumption is smaller than the power consumption condition. If the second area is smaller than the area condition and the second power consumption is smaller than the power consumption condition, executing step S105-8, otherwise, executing step S105-3.

If Aj < a and Pj < P, step S105-8 is performed, otherwise step S105-3 is performed.

And S105-8, taking the currently polled physical memory as a pre-selection memory, and updating the initial selection performance. And after the execution of S105-8 is finished, S105-3 is executed.

Wherein the occurrence performance is updated according to the method of step S104.

After all the physical memories meeting the preselection indexes of each group are polled through steps S105-1 to S105-8, namely after the polling is finished, the final preselection memory is used as a target memory.

Through the steps S105-1 to S105-8, the performance requirement of the logic memory which can meet the requirement under any condition can be selected from the physical memories which meet all the preselected indexes based on the preselected memory, and the physical memory which meets the optimal power consumption condition is taken as the target memory, so that the power consumption optimization of the chip memory is realized.

The method for optimizing the power consumption of the chip memory provided by the embodiment of the invention can obviously reduce the power consumption of the memory under the condition of ensuring that the total area of the chip memory is almost close to the optimal area, thereby obviously improving the realizability of the chip and greatly improving the competitiveness of a chip product.

In practical application, the power consumption optimization method of the chip memory provided by the embodiment of the invention is adopted to optimize a large network chip. As shown in Table 1, before optimization, the memory area of the chip is 103.80mm ^2, the memory power consumption is 263.04W, after optimization, the memory area of the chip is 104.41mm ^2, the memory power consumption is 204.10W, the optimization proportion of the memory area is 0.59 percent, and the optimization proportion of the memory power consumption is-22.41 percent.

The area is only increased by 0.59%, but the total power consumption is reduced by 22.41%, and the power consumption of the chip memory is greatly reduced.

TABLE 1

Categories	Memory area (mm ^2)	Memory consumption (W)
			Before optimization	103.80	263.04
After optimization	104.41	204.10
			Optimized ratio	0.59％	-22.41％

It should be understood that although the various steps in the flowcharts of fig. 2-6 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least some of the steps in fig. 2-6 may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performing the sub-steps or stages is not necessarily sequential, but may be performed alternately or alternately with other steps or at least some of the sub-steps or stages of other steps.

In one embodiment, based on the same inventive concept as the chip memory power consumption optimization method described above, as shown in fig. 7, there is provided a chip memory power consumption optimization apparatus 130 including a pre-selection module 140, a final-selection module 150, and an optimization module 160.

And a preselection module 140 for extracting the design information of the required logic memory.

The design information includes address depth, data width, and number of instantiations.

The preselection module 140 is further configured to calculate at least one set of preselection criteria according to the compiling criteria of the physical memory of the same type as the logical memory and the design information.

The preselection module 140 is further configured to obtain a preselection memory satisfying the initial selection condition from a plurality of physical memories meeting each set of preselection criteria.

And a final selection module 150, configured to calculate initial selection performance of a logic memory formed by the preselected memory, and obtain, based on the initial selection performance, a target memory meeting the power consumption optimal condition from the physical memories meeting each set of preselected indexes.

And the optimization module 160 is used for designing the required logic memory based on the target memory so as to obtain a chip memory power consumption optimization scheme.

Through the chip memory power consumption optimization device 130, according to the design information of the logic memory required, the target memory with the optimal power consumption can be obtained from the physical memory actually existing in the market, on the premise that the performance condition is met, the area of the target memory is as small as possible, the power consumption is optimal as possible, and then the logic memory is designed according to the target memory, so that the power consumption of the memory can be reduced as far as possible under the condition that the total area of the chip memory is guaranteed to be optimal as far as possible according to the design scheme of the chip memory.

For specific limitations of the chip memory power consumption optimization device 130, reference may be made to the above limitations of the chip memory power consumption optimization method, which is not described herein again. The respective modules in the chip memory power consumption optimization device 130 can be wholly or partially implemented by software, hardware and a combination thereof. The modules can be embedded in a hardware form or independent from a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.

In one embodiment, an electronic device 170 is provided, and the electronic device 170 may be the terminal 110, and the internal structure thereof may be as shown in fig. 8. The electronic device 170 includes a processor, a memory, a communication interface, a display screen, and an input device connected by a system bus. Wherein the processor of the electronic device 170 is configured to provide computing and control capabilities. The memory of the electronic device 170 includes a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of an operating system and computer programs in the non-volatile storage medium. The communication interface of the electronic device 170 is used for performing wired or wireless communication with the external terminal 110, and the wireless communication may be implemented through WIFI, an operator network, Near Field Communication (NFC), or other technologies. The computer program is executed by a processor to implement a method for optimizing power consumption of a chip memory. The display screen of the electronic device 170 may be a liquid crystal display screen or an electronic ink display screen, and the input device of the electronic device 170 may be a touch layer covered on the display screen, a key, a trackball or a touch pad arranged on the housing of the electronic device 170, or an external keyboard, a touch pad or a mouse.

Those skilled in the art will appreciate that the architecture shown in fig. 8 is merely a block diagram of some of the structures associated with the inventive arrangements and is not intended to limit the computing devices to which the inventive arrangements may be applied, as a particular computing device may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.

In one embodiment, the chip memory power consumption optimization apparatus 130 provided by the present invention can be implemented in the form of a computer program, and the computer program can be executed on the electronic device 170 shown in fig. 8. The memory of the electronic device 170 may store therein various program modules constituting the chip memory power consumption optimizing apparatus 130, such as the pre-selection module 140, the final-selection module 150, and the optimization module 160 shown in fig. 7. The computer program constituted by the respective program modules causes the processor to execute the steps in the chip memory power consumption optimization method of the respective embodiments of the present invention described in this specification.

For example, the electronic device 170 shown in fig. 8 may perform steps S101-S103 through the pre-selection module 140 in the chip memory power consumption optimizing apparatus 130 shown in fig. 7. The electronic device 170 may perform steps S104 and S105 through the final selection module 150. The electronic device 170 may perform step S106 through the optimization module 160.

In one embodiment, there is provided an electronic device 170 comprising a memory and a processor, the memory storing a computer program (or machine executable instructions) capable of being executed by the processor, the processor implementing the following steps when executing the computer program: extracting design information of a required logic memory, wherein the design information comprises address depth and data width; calculating at least one group of preselected indexes according to the compiling indexes of the physical memory of the same type as the logic memory and the design information, wherein each group of preselected indexes comprises address depth and data width; obtaining a pre-selected memory meeting the initial selection condition from a plurality of physical memories meeting each group of pre-selected indexes, wherein the initial selection condition comprises a performance condition and has the smallest area; calculating the initial selection performance of a logic memory formed by the pre-selection memory, wherein the initial selection performance comprises a first area, a first power consumption, an area loss coefficient and a power consumption optimization coefficient; based on the initial selection performance, obtaining a target memory meeting the optimal power consumption condition from the physical memories meeting all groups of preselected indexes; and designing the required logic memory based on the target memory to obtain a chip memory power consumption optimization scheme.

In one embodiment, a storage medium is provided having a computer program stored thereon, the computer program when executed by a processor implementing the steps of: extracting design information of a required logic memory, wherein the design information comprises address depth and data width; calculating at least one group of preselected indexes according to the compiling indexes of the physical memory of the same type as the logic memory and the design information, wherein each group of preselected indexes comprises address depth and data width; obtaining a pre-selected memory meeting the initial selection condition from a plurality of physical memories meeting each group of pre-selected indexes, wherein the initial selection condition comprises a performance condition and has the smallest area; calculating the initial selection performance of a logic memory formed by the pre-selection memory, wherein the initial selection performance comprises a first area, a first power consumption, an area loss coefficient and a power consumption optimization coefficient; based on the initial selection performance, obtaining a target memory meeting the optimal power consumption condition from the physical memories meeting all groups of preselected indexes; and designing the logic memory based on the target memory to obtain a chip memory power consumption optimization scheme.

It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, databases, or other media used in embodiments provided herein may include at least one of non-volatile and volatile memory. Non-volatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical storage, or the like. Volatile Memory can include Random Access Memory (RAM) or external cache Memory. By way of illustration and not limitation, RAM is available in many forms, such as Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), and the like.

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims

1. A method for optimizing power consumption of a chip memory, the method comprising:

calculating the initial selection performance of a logic memory formed by the pre-selection memory, wherein the initial selection performance comprises a first area, first power consumption, an area loss coefficient and a power consumption optimization coefficient;

2. The chip memory power consumption optimization method according to claim 1, wherein the power consumption optimal condition includes an area condition and a power consumption condition;

3. The method of optimizing power consumption of a chip memory according to claim 2, wherein the area condition comprises: a ═ A_c×(1+X_i) (ii) a Wherein A represents an area condition, A_cDenotes a first area, X_iRepresents the area loss coefficient;

the power consumption conditions include: p ═ P_c×(1-Y_i)；

4. The chip memory power consumption optimization method according to any one of claims 1 to 3, wherein the design information further includes an instantiation number;

5. The method for optimizing power consumption of a chip memory according to any one of claims 1 to 3, wherein the step of calculating at least one set of pre-selected metrics according to the compiling metrics of the physical memory of the same type as the logic memory and the design information comprises:

6. The method of claim 5, wherein the compiling indexes of the same type of physical memory comprise a maximum supported address depth, a minimum supported address depth, a maximum supported data width and a minimum supported data width;

7. The method for optimizing power consumption of a chip memory according to any one of claims 1 to 3, wherein the step of obtaining a preselected memory satisfying a preliminary selection condition from a plurality of physical memories satisfying respective sets of the preselected criteria includes:

8. The power consumption optimization device of the chip memory is characterized by comprising a preselection module, a final selection module and an optimization module;

9. An electronic device comprising a processor and a memory, the memory storing machine executable instructions executable by the processor to implement the chip memory power consumption optimization method of any one of claims 1-7.

10. A storage medium having stored thereon a computer program, wherein the computer program, when executed by a processor, implements the chip memory power consumption optimization method of any one of claims 1-7.