CN114448435B

CN114448435B - Comparator threshold error calibration method, device, equipment and medium

Info

Publication number: CN114448435B
Application number: CN202210112557.9A
Authority: CN
Inventors: 贾涵博; 郭轩; 吴旦昱; 周磊; 武锦; 刘新宇
Original assignee: Institute of Microelectronics of CAS
Current assignee: Institute of Microelectronics of CAS
Priority date: 2022-01-29
Filing date: 2022-01-29
Publication date: 2023-01-31
Anticipated expiration: 2042-01-29
Also published as: CN114448435A

Abstract

The invention discloses a method, a device, equipment and a medium for calibrating a comparator threshold value error, relates to the technical field of digital simulation, and is used for solving the problem of error codes caused by misadjustment of the comparator threshold value in an ADC (analog to digital converter) of a production line in the prior art. The method comprises the following steps: the method comprises the steps of obtaining sine wave analog signals of the pipeline analog-to-digital converter to be tested, inputting the sine wave analog signals into a built statistical model to obtain target statistical distribution of output codes of the pipeline analog-to-digital converter, obtaining actual statistical distribution of the output codes of the pipeline analog-to-digital converter, comparing the target statistical distribution with the actual statistical distribution, determining an error value of a comparator threshold value in the pipeline analog-to-digital converter, and calibrating the error value. And an additional calculation circuit is not required to be added, all operations can be completed off chip, and the hardware overhead is low. For the pipeline ADC, the method can effectively improve the overall linearity.

Description

Comparator threshold error calibration method, device, equipment and medium

Technical Field

The invention relates to the technical field of digital simulation, in particular to a method, a device, equipment and a medium for calibrating a comparator threshold error.

Background

Analog-to-digital converters (ADCs) are used to convert analog signals to digital signals and are widely used in the fields of wireless communication, high-end test equipment, image and voice processing, and the like. With the development of advanced processes and design technologies and the expansion of application scenarios, the demand for high-speed and high-precision ADCs is increasingly significant.

The pipeline ADC can achieve a good compromise between speed and precision, so that a pipeline or a pipeline-time interleaving framework is generally adopted for the ultra-high-speed high-precision ADC, but due to the influence of a pipeline ADC process or other non-ideal factors, a comparator of the pipeline ADC has a threshold value maladjustment phenomenon, and error codes are caused.

Therefore, it is desirable to provide a reliable comparator threshold error calibration scheme.

Disclosure of Invention

The invention aims to provide a method, a device, equipment and a medium for calibrating a comparator threshold error, which are used for solving the problem of error codes caused by misadjustment of the comparator threshold in a pipeline ADC in the prior art.

In order to achieve the above purpose, the invention provides the following technical scheme:

the invention provides a method for calibrating a threshold error of a comparator, which comprises the following steps:

acquiring sine wave analog signals of a pipeline analog-to-digital converter to be tested;

inputting the sine wave analog signal into the established statistical model to obtain the target statistical distribution of the output code of the pipeline analog-to-digital converter;

acquiring actual statistical distribution of output codes of the pipeline analog-to-digital converter;

comparing the target statistical distribution with the actual statistical distribution to determine an error value of a comparator threshold in the pipeline analog-to-digital converter;

the error value is calibrated.

The invention provides a comparator threshold error calibration device, comprising:

the sine wave analog signal acquisition module is used for acquiring a sine wave analog signal of the pipeline analog-to-digital converter to be tested;

the target statistical distribution determining module is used for inputting the sine wave analog signal into the established statistical model to obtain the target statistical distribution of the output code of the pipeline analog-to-digital converter;

the actual statistical distribution acquisition module is used for acquiring the actual statistical distribution of the output codes of the pipeline analog-to-digital converter;

an error value determining module, configured to compare the target statistical distribution with the actual statistical distribution, and determine an error value of a comparator threshold in the pipeline analog-to-digital converter;

and the error calibration module is used for calibrating the error value.

The invention provides a comparator threshold error calibration device, which is characterized by comprising:

the communication unit/communication interface is used for acquiring sine wave analog signals of the pipeline analog-to-digital converter to be tested and acquiring actual statistical distribution of output codes of the pipeline analog-to-digital converter;

the processing unit/processor is used for inputting the sine wave analog signal into the established statistical model to obtain the target statistical distribution of the output code of the pipeline analog-to-digital converter;

comparing the target statistical distribution with the actual statistical distribution, and determining an error value of a comparator threshold value in the pipeline analog-to-digital converter;

the error value is calibrated.

The invention provides a computer storage medium, wherein instructions are stored in the computer storage medium, and when the instructions are executed, the comparator threshold error calibration method is realized.

Compared with the prior art, the comparator threshold error calibration scheme provided by the invention has the advantages that the sine wave analog signal of the pipeline analog-to-digital converter to be tested is obtained, the sine wave analog signal is input into the established statistical model, the target statistical distribution of the output codes of the pipeline analog-to-digital converter is obtained, the actual statistical distribution of the output codes of the pipeline analog-to-digital converter is obtained, the target statistical distribution and the actual statistical distribution are compared, the error value of the comparator threshold in the pipeline analog-to-digital converter is determined, and the error value is calibrated. And an additional calculation circuit is not required to be added, all operations can be completed off chip, and the hardware overhead is low. For the pipeline ADC, the method can effectively improve the overall linearity of the pipeline ADC.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:

FIG. 1 is an overall block diagram of a pipeline analog-to-digital converter;

FIG. 2 is a transmission curve for comparator threshold mismatch;

fig. 3 is a schematic flowchart of a method for calibrating a threshold error of a comparator according to an embodiment of the present disclosure;

FIG. 4 is an overall structure diagram of a 14bit Pipelined ADC;

fig. 5 is a structural diagram of a comparator threshold error calibration apparatus according to an embodiment of the present disclosure;

fig. 6 is a schematic diagram of a comparator threshold error calibration mechanism provided in an embodiment of the present disclosure.

Detailed Description

In order to facilitate clear description of technical solutions of the embodiments of the present invention, in the embodiments of the present invention, terms such as "first" and "second" are used to distinguish the same items or similar items having substantially the same functions and actions. For example, the first threshold and the second threshold are only used for distinguishing different thresholds, and the sequence order of the thresholds is not limited. Those skilled in the art will appreciate that the terms "first," "second," etc. do not denote any order or quantity, nor do the terms "first," "second," etc. denote any order or importance.

It is to be understood that the terms "exemplary" or "such as" are used herein to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "e.g.," is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the word "exemplary" or "such as" is intended to present concepts related in a concrete fashion.

In the present invention, "at least one" means one or more, "a plurality" means two or more. "and/or" describes the association relationship of the associated objects, meaning that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone, wherein A and B can be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of the singular or plural items. For example, at least one (one) of a, b, or c, may represent: a, b, c, a and b combination, a and c combination, b and c combination, or a, b and c combination, wherein a, b and c can be single or multiple.

Before describing the embodiments of the present invention, the following explanations will be made for the related terms related to the embodiments of the present invention:

an analog-to-digital converter: also called analog-to-digital converters, i.e. a/D converters, or simply ADCs, may generally represent an electronic component that converts an analog signal into a digital signal. A typical analog-to-digital converter converts an input voltage signal into an output digital signal. Since digital signals do not have practical significance per se, only one relative magnitude is represented. Therefore, any analog-to-digital converter needs a reference analog quantity as a conversion standard, and a common reference standard is the maximum convertible signal size. And the output digital quantity represents the magnitude of the input signal relative to the reference signal.

Pipeline analog-to-digital converter (Pipelined ADC): the high-speed analog-digital conversion structure is a common analog-digital conversion structure, has high conversion rate and low consumed chip area and power consumption, and is commonly used in high-speed application fields such as wireless communication, CCD image data processing, ultrasonic monitoring and the like. Most pipeline ADCs are realized by adopting a switched capacitor circuit, and higher precision and lower power consumption can be achieved. If no self-calibration (calibration) or capacitance correction (trimming) is carried out, the pipeline ADC can only achieve the precision of 10-12 bit, which is mainly because the switched capacitor circuit is sensitive to the precision of capacitance matching. In addition, the limited gain of the operational amplifier, the accuracy of the reference voltage, the charge injection of the switch, and other factors limit the accuracy of the converter. Meanwhile, since influences caused by the manufacturing process, the working environment and the like are randomly changed, the elimination of the influences requires the chip to have a self-correcting function. By self-correction, the precision of the converter can reach 13-15 bit.

Flash ADC: the bandwidth of some high-speed instruments such as a digital oscilloscope reaches GHz level, and an analog-to-digital converter with extremely high conversion speed is required, and a Flash structure is generally adopted.

For a pipelined ADC, this can be explained in connection with fig. 1:

fig. 1 is an overall block diagram of a pipeline analog-to-digital converter. As shown in fig. 1, the principle of sub-Pipelined ADCs within a channel is given, the basic principle being to distribute the high resolution analog-to-digital conversion pressure to each pipeline stage. A small number of bits are sequentially analyzed by each pipeline stage, high-resolution analog-to-digital conversion is realized by continuous work of multiple pipeline stages, the most significant bit is analyzed by the first stage in the pipeline, the least significant bit is analyzed by the last stage in the pipeline, a sub-ADC in each pipeline stage is usually realized by a Flash ADC, but due to non-ideal factors such as process and the like, a comparator in the Flash ADC has a threshold value maladjustment phenomenon, so that a transmission curve of the pipeline stage overflows, and error codes are caused.

To solve this problem, the prior art proposes an MDAC (microsoft database access module) with a 0.5bit redundancy structure, which can tolerate a certain comparator threshold offset of a sub-ADC, and is a popular architecture of a Pipelined ADC, and its principle is: to reduce the likelihood of code loss due to gain error or comparator threshold mismatch, the inter-stage gain is from 2 ⁿ Down to 2 ^n-1 (ii) a Meanwhile, one comparator is reduced, and all the remaining comparator thresholds are shifted, so that the phenomenon that the digital output initial value of the ADC is not 0 and fixed offset exists is avoided.

In this case, the comparator threshold can be corrected as long as it is out of tune within a certain range, when the transfer curve is as shown in fig. 2 below. For the pipeline stage of the last stage of the pipeline ADC, a Flash ADC is usually used for implementation. Because the pipeline stage of the stage is the last stage, the offset of the comparator threshold value within a certain range can be tolerated without a redundant bit structure, and at the moment, the offset of the comparator threshold value of the Flash ADC can seriously affect the overall linearity of the ADC.

Based on this, the present invention provides a calibration scheme for comparator threshold error, and the following describes the scheme provided by the embodiments of the present specification with reference to the accompanying drawings:

fig. 3 is a flowchart illustrating a method for calibrating a threshold error of a comparator according to an embodiment of the present disclosure. From a program perspective, the execution subject of the flow may be a pipeline analog-to-digital converter chip; comparator threshold error extraction circuitry, comparator threshold adjustment circuitry, and the like may be included in the chip.

As shown in fig. 3, the process may include the following steps:

step 310: and acquiring a sine wave analog signal of the pipeline analog-to-digital converter to be tested.

Step 320: and inputting the sine wave analog signal into the established statistical model to obtain the target statistical distribution of the output code of the pipeline analog-to-digital converter.

The sine wave analog signal is a signal that simulates a nearly sine wave. The statistical model can be an ADC model, and the statistical distribution of Flash ADC output codes of the last stage of the statistical model can be obtained by inputting a sine wave analog signal to the ADC model. The statistical distribution of the Flash ADC output codes of the last stage can be determined as target statistical distribution.

Step 330: and acquiring the actual statistical distribution of the output codes of the pipeline analog-to-digital converter.

In an actual test, a Flash ADC at the last stage of the pipeline ADC may correspond to a plurality of output codes, each output code corresponds to an actual statistical distribution, and in a specific implementation process, the statistical distribution of the plurality of output codes may be an occurrence probability corresponding to each output code, for example: the occurrence probability corresponding to the output code 0 is 0.00%, and the occurrence probability corresponding to the output code 4 is 12.88%.

Step 340: and comparing the target statistical distribution with the actual statistical distribution to determine an error value of a comparator threshold value in the pipeline analog-to-digital converter.

The error value of the comparator threshold can be determined by comparing the target statistics output by the model with the actual statistical distribution during actual testing. The actual statistical distribution can represent that a sine wave analog signal which is the same as the model input is input to the actual ADC chip, and further the statistical distribution of the Flash ADC output code of the last stage during the actual test of the ADC chip is counted.

Step 350: the error value is calibrated.

During calibration, calibration can be performed based on the compensation circuit, and other methods can also be used for calibration, as long as the method can be used for calibrating the comparator threshold error in the pipeline ADC, the method can be applied to the calibration scheme provided by the present invention.

The method in fig. 3 obtains a sine wave analog signal of the pipeline analog-to-digital converter to be tested, inputs the sine wave analog signal into the established statistical model to obtain a target statistical distribution of the output codes of the pipeline analog-to-digital converter, obtains an actual statistical distribution of the output codes of the pipeline analog-to-digital converter, compares the target statistical distribution with the actual statistical distribution, determines an error value of a comparator threshold in the pipeline analog-to-digital converter, and calibrates the error value. And an additional calculation circuit is not required to be added, all operations can be completed off chip, and the hardware overhead is low. For the pipeline ADC, the method can effectively improve the overall linearity of the pipeline ADC.

Based on the method of fig. 3, the embodiments of the present specification also provide some specific implementations of the method, which are described below.

Before using the statistical model, the calibrated pipeline ADC needs to be modeled by simulation. In specific implementation, a statistical model with the addition of a comparator threshold error can be established, and an ideal model without the addition of an error can also be directly established. The following are described separately:

the method comprises the steps of establishing a statistical model of threshold errors of an added comparator.

Setting an initial error of the pipeline analog-to-digital converter to be tested, wherein the initial error is a preset error value of a comparator threshold value in the last-stage analog-to-digital converter in a statistical model;

inputting the initial error and a preset sine wave analog signal into an initial statistical model to obtain statistical distribution of output codes of the pipeline analog-to-digital converter;

and adjusting the initial error based on the difference value between the statistical distribution and the known statistical distribution until the statistical distribution meets a preset condition to obtain the established statistical model.

Since the data stream of the pipeline ADC is processed in one stage, i.e. the output of the first stage is the input of the second stage, the transmission curve is foldable laterally. During modeling, the structure of the ADC can be simulated and modeled by Matlab, and the work flow of the structure of fig. 4 is simulated by the model. Fig. 4 is an overall structure diagram of a 14-bit Pipelined ADC, and taking the 14-bit Pipelined ADC as an example, it is assumed that the Pipelined ADC is composed of a 5-stage 2.5-bit pipeline stage and a subsequent stage of 4-bit Flash ADC. When the structure in fig. 4 is implemented, the whole process can be simulated by a model. That is, the calibrated pipeline ADC is modeled by a model, and some errors (e.g., comparator offset) may be added during modeling, for example: when 10% of error is added, if the threshold of the comparator of the last stage Flash ADC is out of order at this time, if the threshold of the fourth comparator is larger than 10%, the statistical distribution of the output codes of the last stage Flash ADC is as follows:

TABLE 1 statistical distribution Table of addition errors

Table 1 above iteratively adjusts the initial by adding an initial error according to probability, for example: according to the existing ADC chip, through testing, the occurrence probability of output codes is different, firstly, an error initial value is set, errors are adjusted according to the output probability until the output errors meet conditions, and the set errors are determined to be close to actual errors.

In the foregoing step, comparing the target statistical distribution with the actual statistical distribution, and determining an error value of a comparator threshold in the pipeline analog-to-digital converter may specifically include:

determining target statistical distribution and actual statistical distribution corresponding to the same output code;

calculating a difference between the target statistical distribution and an actual statistical distribution;

determining the difference as an error value of a comparator threshold in the pipeline analog-to-digital converter.

By the first mode, the error is added into the model training process, and the output result based on the model is compared with the actual statistical distribution, so that the error value of the comparator threshold is determined.

And establishing an ideal model.

The established statistical model can be an ideal model without setting an initial error; the method may further comprise:

acquiring a single-tone sine wave analog signal;

inputting the single-tone sine wave analog signal into the ideal model to obtain ideal statistical distribution;

and comparing the ideal statistical distribution with the target statistical distribution to determine an error value of a comparator threshold value in the pipeline analog-to-digital converter.

For an ideal model, the result output by the ideal model is an ideal result, and the statistical distribution of the output codes output by the ideal model can be described with reference to table 2:

TABLE 2 statistical distribution Table under ideal conditions

Output code	Probability of occurrence
		0	0.00％
1	0.00％
		2	0.00％
3	0.00％
		4	12.88％
5	12.39％
		6	12.36％
7	12.37％
		8	12.37％
9	12.36％
		10	12.39％
11	12.88％
		12	0.00％
13	0.00％
		14	0.00％
15	0.00％

It can be seen that, in an ideal situation, the probability of the output code of the last stage Flash ADC is 0 between 0-3 and 12-15, and the probability of the output code in the 4-11 digital code is basically consistent, and is about 12.5%.

When comparing table 1 with table 2, the statistical result shows that the statistical probability of the digital code 4 is reduced from 12.88% to 11.59% and reduced by about 10% due to the fact that the threshold of the fourth comparator is larger by 10%; while the statistical probability of digital code 3 is improved from 0.00% to 1.28%. It can be seen that, for the Flash ADC of the last stage, there is a linear relationship between the threshold misadjustment degree of the comparator and the occurrence probability of the two digital codes corresponding to the comparator. This shows that we can reversely deduce the misadjustment degree of the comparator threshold corresponding to the digital code according to the statistical probability of the output signal.

In actual test, the output result corresponding to the comparator threshold in the pipeline analog-to-digital converter to be tested is compared with an ideal result, so that the comparator threshold offset information of the last stage Flash ADC can be extracted, and accurate calibration of the comparator threshold offset is realized through feedback adjustment. Modeling is carried out on the basis of an ideal model in simulation, code density and probability statistics are combined, the difference between an actual test result and the ideal model is compared, comparator threshold value maladjustment information of the last-stage Flash ADC is extracted, and accurate calibration of comparator threshold value maladjustment is achieved through feedback adjustment. The method does not need to add an additional computing circuit, all operations can be completed off-chip, and the hardware cost is low. For the Pipelined ADC, the method can effectively improve the overall linearity of the Pipelined ADC.

The calibrating the error value may specifically include:

and calibrating the error value through feedback regulation based on a comparator threshold regulating circuit inside the pipeline analog-to-digital converter chip.

The comparator threshold adjusting circuit can be used for error adjustment or error compensation, and the structure in the adjusting circuit can be set according to the actual application requirements, which is not specifically described in the embodiments of the present specification.

Optionally, the data stream of the pipeline analog-to-digital converter is subjected to stage-by-stage transfer processing; when data transmission processing is carried out between two adjacent stages, the data output of the previous stage is the data input of the next stage.

In the scheme in the embodiment of the description, a linear relation exists between the threshold misadjustment degree of the comparator and the occurrence probability of two digital codes corresponding to the comparator. This shows that the degree of misadjustment of the comparator threshold corresponding to the digital code can be reversely estimated according to the statistical probability of the output signal. And modeling the ideal model in simulation, combining code density and probability statistics, and extracting comparator threshold offset information of the last-stage Flash ADC by comparing the difference between an actual test result and the ideal model. The method can be applied to any Pipelined ADC without the limitation of the circuit structure.

The above embodiments are only individual embodiments capable of realizing the schemes provided in the examples of the present specification, and do not represent the entire scope of protection of the present application, and there may be many other embodiments other than the above-described embodiments, and the examples of the present specification are not particularly limited.

Based on the same idea, the embodiments of the present specification further provide a comparator threshold error calibration apparatus. Fig. 5 is a structural diagram of a comparator threshold error calibration apparatus according to an embodiment of the present disclosure. The method can comprise the following steps:

a sine wave analog signal obtaining module 510, configured to obtain a sine wave analog signal of the pipeline analog-to-digital converter to be tested;

a target statistical distribution determining module 520, configured to input the sine wave analog signal into the established statistical model to obtain a target statistical distribution of the output code of the pipeline analog-to-digital converter;

an actual statistical distribution obtaining module 530, configured to obtain an actual statistical distribution of output codes of the pipeline analog-to-digital converter;

an error value determining module 540, configured to compare the target statistical distribution with the actual statistical distribution, and determine an error value of a comparator threshold in the pipeline analog-to-digital converter;

an error calibration module 550 for calibrating the error value.

The apparatus in fig. 5 further includes some specific implementation modules, and the following description may be continued:

the apparatus may further include:

the initial error setting module is used for setting an initial error of the pipeline analog-to-digital converter to be tested, wherein the initial error is a preset error value of a comparator threshold value in the last-stage analog-to-digital converter in a statistical model;

the initial statistical distribution determining module is used for inputting the initial error and a preset sine wave analog signal into an initial statistical model to obtain the statistical distribution of the output codes of the pipeline analog-to-digital converter;

and the error adjusting module is used for adjusting the initial error based on the difference value between the statistical distribution and the known statistical distribution until the statistical distribution meets the preset condition to obtain the established statistical model.

Optionally, the error value determining module 540 may specifically include:

the statistical distribution determining unit is used for determining target statistical distribution and actual statistical distribution corresponding to the same output code;

a difference calculation unit for calculating a difference between the target statistical distribution and an actual statistical distribution;

a comparator threshold error determination unit for determining the difference as an error value of a comparator threshold in the pipeline analog-to-digital converter.

Optionally, the established statistical model may be an ideal model without setting an initial error; the apparatus may further include:

the single-tone sine wave analog signal acquisition module is used for acquiring a single-tone sine wave analog signal;

an ideal statistical distribution determining module, configured to obtain ideal statistical distribution after the single-tone sine wave analog signal is input into the ideal model;

and the comparison module is used for comparing the ideal statistical distribution with the target statistical distribution and determining an error value of a comparator threshold value in the pipeline analog-to-digital converter.

Optionally, the error calibration module 550 may specifically include:

and the calibration unit is used for calibrating the error value through feedback regulation based on a comparator threshold regulation circuit in the pipeline analog-to-digital converter chip.

Optionally, the data stream of the pipeline analog-to-digital converter may be subjected to stage-by-stage transfer processing; when data transmission processing is carried out between two adjacent stages, the data output of the previous stage is the data input of the next stage.

Based on the same idea, the embodiment of the present specification further provides a comparator threshold error calibration device. Fig. 6 is a schematic diagram of a comparator threshold error calibration mechanism provided in an embodiment of the present disclosure. The method can comprise the following steps:

the error value is calibrated.

As shown in fig. 6, the terminal device may further include a communication line. The communication link may include a path for transmitting information between the aforementioned components.

Optionally, as shown in fig. 6, the terminal device may further include a memory. The memory is used for storing computer-executable instructions for implementing the inventive arrangements and is controlled by the processor for execution. The processor is used for executing the computer execution instructions stored in the memory, thereby realizing the method provided by the embodiment of the invention.

As shown in fig. 6, the memory may be a read-only memory (ROM) or other type of static storage device that may store static information and instructions, a Random Access Memory (RAM) or other type of dynamic storage device that may store information and instructions, an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disk storage, optical disk storage (including compact disc, laser disc, optical disc, digital versatile disc, blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer, but is not limited to. The memory may be separate and coupled to the processor via a communication link. The memory may also be integral to the processor.

Optionally, the computer-executable instructions in the embodiment of the present invention may also be referred to as application program codes, which is not specifically limited in this embodiment of the present invention.

In one implementation, as shown in FIG. 6, a processor may include one or more CPUs, such as CPU0 and CPU1 in FIG. 6, for example.

In a specific implementation, as an embodiment, as shown in fig. 6, the terminal device may include a plurality of processors, such as the processor and the processor in fig. 6. Each of these processors may be a single core processor or a multi-core processor.

Based on the same idea, embodiments of the present specification further provide a computer storage medium corresponding to the foregoing embodiments, where the computer storage medium stores instructions, and when the instructions are executed, the instructions implement:

acquiring a sine wave analog signal of a pipeline analog-to-digital converter to be tested;

the error value is calibrated.

The above description mainly introduces the scheme provided by the embodiment of the present invention from the perspective of interaction between the modules. It is understood that each module, in order to implement the above functions, includes a corresponding hardware structure and/or software unit for performing each function. Those of skill in the art will readily appreciate that the present invention can be implemented in hardware or a combination of hardware and computer software, with the exemplary elements and algorithm steps described in connection with the embodiments disclosed herein. Whether a function is performed as hardware or computer software drives hardware depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

The functional modules may be divided according to the above method examples, for example, the functional modules may be divided corresponding to the functions, or two or more functions may be integrated into one processing module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. It should be noted that, the division of the modules in the embodiment of the present invention is schematic, and is only a logic function division, and there may be another division manner in actual implementation.

The processor in this specification may also have the function of a memory. The memory is used for storing computer-executable instructions for implementing the inventive arrangements and is controlled by the processor for execution. The processor is used for executing the computer execution instructions stored in the memory, thereby realizing the method provided by the embodiment of the invention.

The memory may be, but is not limited to, a read-only memory (ROM) or other type of static storage device that may store static information and instructions, a Random Access Memory (RAM) or other type of dynamic storage device that may store information and instructions, an electrically erasable programmable read-only memory (EEPROM), a compact disk read-only memory (CD-ROM) or other optical disk storage, optical disk storage (including compact disk, laser disk, optical disk, digital versatile disk, blu-ray disk, etc.), magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer. The memory may be separate and coupled to the processor via a communication link. The memory may also be integral to the processor.

The method disclosed by the embodiment of the invention can be applied to a processor or realized by the processor. The processor may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware in a processor or instructions in the form of software. The processor may be a general purpose processor, a Digital Signal Processor (DSP), an ASIC, an FPGA (field-programmable gate array) or other programmable logic device, discrete gate or transistor logic device, or discrete hardware components. The various methods, steps and logic blocks disclosed in the embodiments of the present invention may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the method disclosed in connection with the embodiments of the present invention may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor. The software module may be located in ram, flash memory, rom, prom, or eprom, registers, etc. storage media as is well known in the art. The storage medium is located in a memory, and a processor reads information in the memory and completes the steps of the method in combination with hardware of the processor.

In one possible implementation manner, a computer-readable storage medium is provided, in which instructions are stored, and when executed, the instructions are used to implement the logic operation control method and/or the logic operation reading method in the foregoing embodiments.

In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, it may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, the procedures or functions described in the embodiments of the present invention are performed in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, a terminal, a user device, or other programmable apparatus. The computer program or instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer program or instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wire or wirelessly. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that integrates one or more available media. The usable medium may be a magnetic medium, such as a floppy disk, a hard disk, a magnetic tape; or optical media such as Digital Video Disks (DVDs); it may also be a semiconductor medium, such as a Solid State Drive (SSD).

While the invention has been described in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a review of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

While the invention has been described in conjunction with specific features and embodiments thereof, it will be evident that various modifications and combinations can be made thereto without departing from the spirit and scope of the invention. Accordingly, the specification and figures are merely exemplary of the invention as defined in the appended claims and are intended to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims

1. A method for calibrating a comparator threshold error, comprising:

inputting the sine wave analog signal into the established statistical model to obtain the target statistical distribution of the output code of the pipeline analog-to-digital converter; the statistical model is an ADC model; the target statistical distribution is the statistical distribution of the last-stage Flash ADC output code obtained after a sine wave analog signal is input by the ADC model; establishing a completed statistical model as a model obtained by adding initial error training; the initial error is a preset error value of a comparator threshold value in the last-stage analog-to-digital converter in the statistical model;

acquiring actual statistical distribution of output codes of the pipeline analog-to-digital converter; the Flash ADC of the last stage of the pipeline analog-to-digital converter is correspondingly provided with a plurality of output codes, and each output code is correspondingly distributed in an actual statistic way;

2. The method of claim 1, wherein before inputting the sine wave analog signal into the established statistical model to obtain the target statistical distribution of the output code of the pipeline analog-to-digital converter, the method further comprises:

3. The method of claim 2, wherein comparing the target statistical distribution to the actual statistical distribution to determine an error value for a comparator threshold in the pipeline analog-to-digital converter comprises:

4. The method of claim 1, wherein the data stream of the pipeline analog-to-digital converter is subjected to a stage-by-stage transfer process; when data transmission processing is carried out between two adjacent stages, the data output of the previous stage is the data input of the next stage.

5. A comparator threshold error calibration apparatus, comprising:

the target statistical distribution determining module is used for inputting the sine wave analog signal into the established statistical model to obtain the target statistical distribution of the output code of the pipeline analog-to-digital converter; the statistical model is an ADC model; the target statistical distribution is the statistical distribution of the last-stage Flash ADC output code obtained after a sine wave analog signal is input by the ADC model; establishing a completed statistical model as a model obtained by adding initial error training; the initial error is a preset error value of a comparator threshold value in the last-stage analog-to-digital converter in the statistical model;

the actual statistical distribution acquisition module is used for acquiring the actual statistical distribution of the output codes of the pipeline analog-to-digital converter; the Flash ADC of the last stage of the pipeline analog-to-digital converter is correspondingly provided with a plurality of output codes, and each output code is correspondingly distributed in an actual statistic way;

and the error calibration module is used for calibrating the error value through feedback regulation based on a comparator threshold regulation circuit in the pipeline analog-to-digital converter chip.

6. The apparatus of claim 5, further comprising:

7. A comparator threshold error calibration apparatus, comprising:

the communication unit/communication interface is used for acquiring sine wave analog signals of the pipeline analog-to-digital converter to be tested and acquiring actual statistical distribution of output codes of the pipeline analog-to-digital converter; the Flash ADC of the last stage of the pipeline analog-to-digital converter is correspondingly provided with a plurality of output codes, and each output code is correspondingly distributed in an actual statistic way;

the processing unit/processor is used for inputting the sine wave analog signal into the established statistical model to obtain the target statistical distribution of the output code of the pipeline analog-to-digital converter; the statistical model is an ADC model; the target statistical distribution is the statistical distribution of the last-stage Flash ADC output code obtained after a sine wave analog signal is input by the ADC model; establishing a completed statistical model as a model obtained by adding initial error training; the initial error is a preset error value of a comparator threshold value in the last-stage analog-to-digital converter in the statistical model;

8. A computer storage medium having stored therein instructions which, when executed, implement the comparator threshold error calibration method of any one of claims 1 to 4.