CN114448211A

CN114448211A - Two-level driver for driving IGBT

Info

Publication number: CN114448211A
Application number: CN202011191456.2A
Authority: CN
Inventors: 陈正文; 魏海山; 欧阳柳; 杨乐乐; 马龙昌; 朱武; 唐威; 周思敏; 寇晨晨; 丁清澍; 窦泽春; 陈燕平
Original assignee: CRRC Zhuzhou Institute Co Ltd
Current assignee: CRRC Zhuzhou Institute Co Ltd
Priority date: 2020-10-30
Filing date: 2020-10-30
Publication date: 2022-05-06

Abstract

The invention discloses a two-level driver for driving an IGBT (insulated gate bipolar transistor), which comprises a fault latch unit, a logic control unit, a signal logic processing unit and a power output unit, wherein the fault latch unit is used for latching a signal; the signal logic processing unit is used for realizing the interlocking and fault blocking processing of the PWM input signals according to the PWM input signals provided by the external controller and the fault latch signals provided by the logic control unit and providing the PWM pulse signals obtained after the processing to the logic control unit; the logic control unit is used for generating and outputting corresponding driving control signals according to the PWM pulse signals provided by the signal logic processing unit and the fault latch signals provided by the fault latch unit; the power output unit is used for performing power conversion on the driving control signal provided by the logic control unit, generating and outputting a corresponding driving signal so as to control the on/off function and the 0 level off function of the IGBT driven by the two-level driver.

Description

Two-level driver for driving IGBT

Technical Field

The invention relates to the technical field of power devices, in particular to a two-level driver for driving an IGBT.

Background

With the continuous development of high-speed motor train technology, the requirement on the safety and stability of motor train running is higher and higher. As an important component of a motor vehicle power system, a drive circuit of an inverter module in a traction inverter plays an extremely important role. The two-level driving circuit plays an important role. However, the two-level has a problem in managing the faults of the inner and outer IGBT tubes.

Disclosure of Invention

In view of the above problems, the present invention provides a two-level driver for driving an IGBT, which implements a driving function and a temperature detection function of an IGBT.

According to a first aspect, the present invention provides a two-level driver for driving an IGBT, including a fault latch unit, a logic control unit, a signal logic processing unit, and a power output unit; wherein:

the fault latch unit is used for generating and outputting fault latch signals capable of being locked at fixed time according to various received fault signals;

the first input end of the logic control unit is connected with the output end of the fault latch unit, and the first output end of the logic control unit is connected with the first input end of the signal logic processing unit, and the logic control unit is used for forwarding a fault latch signal provided by the fault latch unit to the signal logic processing unit;

the second input end of the signal logic processing unit is connected with the output end of an external controller, the first output end of the signal logic processing unit is connected with the second input end of the logic control unit, and the signal logic processing unit is used for realizing the processing of the interlocking and the fault blocking of the PWM input signals according to the PWM input signals provided by the controller and the fault latching signals provided by the logic control unit and providing the PWM pulse signals obtained after the processing to the logic control unit;

the logic control unit is also used for generating and outputting a corresponding driving control signal according to the PWM pulse signal provided by the signal logic processing unit and the fault latch signal provided by the fault latch unit; the PWM pulse signal determines the high and low level of the driving control signal, and the fault latch signal controls the soft turn-off of the high and low level of the driving control signal;

and the power output unit is connected with the second output end of the logic control unit and is used for performing power conversion on the driving control signal provided by the logic control unit, generating and outputting a corresponding driving signal so as to control the on/off function and the 0 level off function of the IGBT driven by the two-level driver.

According to some embodiments of the invention, the two-level driver further comprises:

and the signal isolation unit is connected between the signal logic processing unit and the logic control unit and is used for realizing the isolation of the PWM pulse signal and the fault latch signal.

the power supply unit is used for converting an external input power supply into a driving power supply used by the two-level driver for driving the IGBT;

the power supply monitoring unit is connected with the power supply unit and used for monitoring the driving power supply output by the power supply unit and outputting a power supply fault signal when the driving power supply does not meet the preset power supply condition;

the state monitoring unit is used for acquiring state parameters of the IGBT driven by the two-level driver and outputting a state fault signal when the state parameters do not meet preset state conditions;

correspondingly, the fault latch unit is connected with the power supply monitoring unit and the state monitoring unit and used for generating and outputting a fault latch signal capable of being blocked at fixed time according to the power supply fault signal provided by the power supply monitoring unit and the state fault signal provided by the state monitoring unit.

According to some embodiments of the invention, in the above two-level driver, the power supply unit includes:

the EMI filtering subunit is used for carrying out filtering processing on an external input power supply;

the auxiliary power supply electronic unit is connected with the EMI filtering unit and is used for converting the external input power supply subjected to filtering processing into an auxiliary power supply;

and the isolation DC/DC subunit is connected with the auxiliary power supply electronic unit and used for realizing isolation conversion of a power supply under the support of the auxiliary power supply and outputting a driving power supply used by the two-level driver for driving the IGBT.

According to some embodiments of the present invention, in the above two-level driver, the state monitoring unit includes:

a setting subunit, configured to set a state parameter threshold;

the monitoring subunit is used for acquiring the state parameters of the IGBT driven by the two-level driver;

and the comparison subunit is connected with the setting subunit and the monitoring subunit and is used for comparing the state parameter with the state parameter threshold value and judging whether to output a state fault signal according to a comparison result.

According to some embodiments of the present invention, in the above two-level driver, the power failure signal includes an under-voltage failure signal; the state parameters of the IGBT comprise a gate voltage signal and a gate voltage signal of the IGBT.

According to some embodiments of the invention, in the two-level driver described above:

the fault latch signal comprises a fault latch signal of the inner tube IGBT and a fault latch signal of the outer tube IGBT;

the PWM input signals comprise inner tube PWM input signals and outer tube PWM input signals;

the PWM pulse signals comprise inner tube PWM pulse signals and outer tube PWM pulse signals.

According to some embodiments of the present invention, in the above two-level driver, the signal logic processing unit includes a first subunit for implementing signal interlock and a second subunit for implementing signal fault lockout; wherein:

the first subunit comprises a first nand gate and a second nand gate, wherein a first input end of the first nand gate is used for receiving the PWM input signal of the inner tube, a second input end of the first nand gate is connected to an output end of the second nand gate, a first input end of the second nand gate is used for receiving the PWM input signal of the outer tube, and a second input end of the second nand gate is used for connecting an output end of the first nand gate;

the second subunit comprises a fault determination circuit, a third nand gate and a fourth nand gate, two input ends of the fault determination circuit are used for receiving the fault latch signal of the inner tube IGBT and the fault latch signal of the outer tube IGBT, to generate and output a fault lockout signal when receiving a fault latch signal of the inner pipe IGBT and/or a fault latch signal of the outer pipe IGBT, the first input end of the third NAND gate and the first input end of the fourth NAND gate are respectively used for receiving the output signals of the first NAND gate and the second NAND gate which are subjected to inversion processing, a second input of the third nand-gate and a second input of the fourth nand-gate are configured to receive the fail-lock signal, and respectively outputting the inner tube PWM pulse signal and the outer tube PWM pulse signal with the fault blocking function according to the fault blocking signal.

According to some embodiments of the present invention, the above two-level driver further includes an NTC detection unit which forms a frequency signal varying with a resistance value of the resistor by sampling the resistance value of the NTC and voltage-to-frequency converting the sampled voltage, and feeds the signal back to an external controller.

According to some embodiments of the present invention, in the above two-level driver, the second output terminal of the signal logic processing unit is externally connected to the input terminal of the controller, and is configured to forward the fault latch signal provided by the logic control unit to the controller.

Compared with the prior art, one or more embodiments of the above scheme of the invention can have the following advantages or beneficial effects:

1) according to the technical scheme, the NTC element is used for collecting the temperature value in real time, so that the monitoring of the internal temperature of the element is conveniently and quickly realized, the internal temperature of the IGBT can be quickly and accurately read, the real-time control is convenient, and the module faults caused by overheating are reduced.

2) The technical scheme of the invention generates the fault latch signal which can be locked at fixed time based on various types of faults, and feeds the fault latch signal back to the external controller, and the fault latch signal can be directly used for upper-layer intelligent control.

3) The technical scheme of the invention realizes intelligent monitoring of the IGBT power device, can monitor the change state of each voltage of the IGBT power device in real time, and enhances the reliability and stability of intelligent control.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and drawings.

Drawings

The scope of the present disclosure may be better understood by reading the following detailed description of exemplary embodiments in conjunction with the accompanying drawings. Wherein the included drawings are:

FIG. 1 is a schematic diagram of a two-level driver according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of modules in a two-level driver according to an embodiment of the invention;

fig. 3 is a schematic diagram showing a configuration of a signal logic processing unit in the two-level driver shown in fig. 1.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention clearer, the following will describe in detail an implementation method of the present invention with reference to the accompanying drawings and embodiments, so that how to apply technical means to solve the technical problems and achieve the technical effects can be fully understood and implemented.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, however, the present invention may be practiced in other ways than those specifically described herein, and therefore the scope of the present invention is not limited by the specific embodiments disclosed below.

As shown in fig. 1, this embodiment provides an exemplary two-level driver for driving an IGBT. The driver mainly includes a power supply unit 110, a power monitoring unit 120, a status monitoring unit 130, a fault latch unit 140, a signal logic processing unit 150, a signal isolation unit 160, a logic control unit 170, a power output unit 180, an external interface unit 190, and an NTC detection unit 200. These circuit modules are preferably arranged on a driver circuit board. Functionally, the circuit modules cooperate to complete three functions of voltage conversion, drive control and fault monitoring. Wherein:

the power supply unit 110 further includes an EMI filter subunit 111, an auxiliary power supply subunit 112, and an isolation DC/DC subunit 113, configured to use an external input power through the EMI filter subunit 111 for driving the inside of a device board, and generate a driving voltage for driving the IGBT on the IGBT high-voltage side through the auxiliary power supply unit 112 and the isolation DC/DC subunit 113;

the signal logic processing unit 150 completes the conversion of the externally input PWM input signal and the internal and external tube fault control, and converts the PWM input signal into a high-voltage side driving control signal through the signal isolation unit 160, the logic control unit 170 and the power output unit 180, so as to control the driving of the IGBT device;

the power supply monitoring unit 120 monitors whether the driving voltage output by the power supply unit 110 is normal, the state monitoring unit 130 monitors and judges whether the working state of the IGBT device driven by the driver is normal, and the fault latch unit 140 implements a fault protection function according to the fault information fed back by the power supply monitoring unit 120 and the state monitoring unit 130;

the NTC detecting unit 200 samples the resistance value of the NTC and performs voltage-to-frequency conversion on the sampled voltage to form a frequency signal varying with the resistance value of the resistor, and feeds the frequency signal back to an external controller, so as to implement upper layer intelligent control.

As shown in fig. 2, the circuit connection and the functional configuration of each unit are described in detail below.

As described above, in the present embodiment, the power supply unit 110 further includes the EMI filtering subunit 111, the auxiliary power supply subunit 112, and the isolation DC/DC subunit 113, wherein:

an EMI filter subunit 111, configured to perform filtering processing on an external input power supply;

an auxiliary power supply unit 112, connected to the EMI filter unit 111, for converting the filtered external input power into an auxiliary power;

and the isolation DC/DC subunit 113 is connected to the auxiliary power supply electronic unit 112, and is used for realizing isolation conversion of the power supply under the support of the auxiliary power supply and outputting a driving power supply used by the two-level driver to drive the IGBT.

And a power monitoring unit 120 connected to the power supply unit 110, configured to monitor the driving power supplied by the power supply unit 110, and output a power failure signal when the driving power does not meet a preset power condition. In practical applications, the most common scheme is that the power monitoring unit 120 monitors the driving voltage output by the power supply unit 110, and outputs an under-voltage fault signal when the driving voltage is lower than a preset voltage threshold.

The status monitoring unit 130 further comprises a setting subunit 131, a monitoring subunit 132 and a comparing subunit 133, wherein:

a setting subunit 131 configured to set a state parameter threshold;

a monitoring subunit 132, configured to obtain a state parameter of the IGBT driven by the two-level driver;

a comparison subunit 133, connected to the setting subunit 131 and the monitoring subunit 132, for comparing the state parameter with the state parameter threshold, and determining whether to output a state fault signal according to the comparison result.

In this embodiment, the state parameters of the IGBT include at least a gate voltage signal and a gate voltage signal of the IGBT. In addition, in this embodiment, since the inner tube IGBT and the outer tube IGBT are driven and monitored simultaneously, the obtained state parameters include the state parameters of the inner tube IGBT and the state parameters of the outer tube IGBT, and the corresponding state fault signals include two paths of fault signals, that is, the state fault signals of the inner tube IGBT and the state fault signals of the outer tube IGBT.

The fail latch unit 140 is connected to the power monitoring unit 120 and the state monitoring unit 130, and configured to generate and output a fail latch signal that can be locked at regular time according to the power failure signal provided by the power monitoring unit 120 and the state failure signal provided by the state monitoring unit.

The fail latch unit 140 is a set of logic digital circuits, and is used for performing comprehensive processing on various fail signals (such as an under-voltage fail signal and a status fail signal) to form and output a fail latch signal that can be locked out at regular time. It should be noted that, in the present embodiment, since the inner tube IGBT and the outer tube IGBT are driven and monitored at the same time, the states of the inner tube IGBT and the outer tube IGBT are independent from each other, and the probability of failure occurrence is also independent from each other, and the failure latch signal output by the failure latch unit 140 includes two paths of latch signals, that is, includes the inner tube IGBT failure latch signal and the outer tube IGBT failure latch signal.

The logic control unit 170 includes first and second input terminals and first and second output terminals. On one hand, a first input end of the logic control unit 170 is connected to the output end of the fail latch unit 140, and a first output end of the logic control unit 170 is connected to a first input end of the signal logic processing unit 150 through the signal isolation unit 160, and is configured to forward the fail latch signal provided by the fail latch unit 140 to the signal logic processing unit 150; on the other hand, a second input end of the logic control unit 170 is connected to the first output end of the signal logic processing unit 150 through the signal isolation unit 160, and a second output end of the logic control unit 150 is connected to the input end of the power output unit 180, and is configured to generate a corresponding driving control signal according to the PWM pulse signal provided by the signal logic processing unit 150 and the fail latch signal provided by the fail latch unit 140, and output the corresponding driving control signal to the power output unit 180; the PWM pulse signal determines the high and low level of the driving control signal, and the fault latch signal controls the high and low level of the driving control signal to be turned off.

It should be noted that, for simplicity, the output terminal of the fail latch unit 140, the first and second input terminals and the first and second output terminals of the signal logic processing unit 150, the input terminal and the output terminal of the signal isolation unit 160, the first input terminal of the logic control unit 170, the first output terminal of the logic control unit 170, the second input terminal of the logic control unit 170, the second output terminal of the logic control unit 170, and the input terminal and the output terminal of the power output unit 180 in fig. 1 are all indicated by one line, but in practice, these lines are used to transmit two inner pipe signals and two outer pipe signals. In this regard, the signal isolation unit 160 also includes two

sub-units

161 and 162 for isolating the inner tube signal and the outer tube signal, respectively.

As previously mentioned, the signal logic processing unit 150 also includes first and second inputs and first and second outputs. On one hand, a first input end of the signal logic processing unit 150 is connected to a first output end of the logic control unit 170, a second input end of the signal logic processing unit 150 is connected to an output end of an external controller (not shown in the figure), and a first output end of the signal logic processing unit 150 is connected to a second input end of the logic control unit 170, and is configured to implement processing of interlocking and fault blocking of the PWM input signal according to the PWM input signal provided by the controller and a fault latch signal provided by the logic control unit, and provide a processed PWM pulse signal to the logic control unit 170. On the other hand, the second output terminal of the signal logic processing unit 150 is externally connected to the controller, and is configured to forward the fault latch signal provided by the logic control unit 170 to the controller, so as to feed back fault information.

As shown in fig. 3, in the present embodiment, the signal logic processing unit 150 further includes a first subunit 151 for implementing signal interlock and a second subunit 152 for implementing signal fault lockout; wherein:

the first subunit 151 includes a first nand gate 1 and a second nand gate 2, a first input end of the first nand gate 1 is configured to receive the inner tube PWM input signal, a second input end of the first nand gate 1 is connected to an output end of the second nand gate 2, a first input end of the second nand gate 2 is connected to an output end of the first nand gate 1, and a second input end of the second nand gate 2 is configured to receive the outer tube PWM input signal;

the second subunit 152 comprises faulty third and fourth nand gates 3 and 4 and a fault determination circuit 5, two input terminals of the fault determination circuit 5 are used for receiving the fault latch signal of the inner tube IGBT and the fault latch signal of the outer tube IGBT, to generate and output a fault lockout signal when receiving a fault latch signal of the inner pipe IGBT and/or a fault latch signal of the outer pipe IGBT, the first input terminal of the third nand-gate 3 and the first input terminal of the fourth nand-gate 4 are respectively used for receiving the output signals of the first nand-gate 1 and the second nand-gate 2 which are subjected to inversion processing (for example, through an inversion circuit, not shown in the figure), a second input of the third nand-gate 3 and a second input of the fourth nand-gate 4 are adapted to receive the fail-lock signal, and respectively outputting the inner tube PWM pulse signal and the outer tube PWM pulse signal with the fault blocking function according to the fault blocking signal.

In this embodiment, the signal logic processing unit 140 further includes a first filter circuit 6 and a second filter circuit 7, where the first filter circuit 6 and the second filter circuit 7 are respectively disposed between the first nand gate 1 and the second nand gate 2 and the controller, and are used to filter the simultaneously input inner tube PWM input signal and the outer tube PWM input signal.

As shown in fig. 3, based on the above circuit structure, the operation mechanism of the signal logic processing unit 140 is as follows:

the signal receiving logic processing unit carries out comprehensive logic processing on the PWM input signal and the fault latch signal of the controller to realize fault blocking of the PWM signal and output the fault latch signal to the controller.

Therefore, two paths of pulse signals PWM are input to the filter circuit, transmitted to the first subunit after filtering, and pulse interlocking is realized through the NAND gate, and the specific logic is as follows: when both PWM1 and PWM2 are 0, both nand gate outputs are 1; when the PWM1 jumps to 1, the output of the NAND gate 1 is 0, the output of the NAND gate 2 is 1, at the moment, the PWM2 jumps to 1 again, the output of the NAND gate 2 is unchanged, and 1 is maintained, so that the outputs of the two NAND gates are not 0 at the same time; similarly, when the PWM2 jumps to 1, the output of the nand gate 2 is 0, the output of the nand gate 1 is 1, and at this time, the PWM1 jumps to 1 again, the output of the nand gate 1 is unchanged, and remains 1, thereby ensuring that the outputs of the two nand gates are not 0 at the same time. The output of nand gate 1/2 is then inverted back to the same logic as the external input signal.

The fault latch signal is input to a fault judging circuit, the fault judging circuit outputs a fault blocking signal, and when no fault exists, the fault blocking signal is at a high level; when there is a fault, the fault lockout signal is low. The fault locking signal and the output signal of the first NAND gate and the second NAND gate are input to a third NAND gate and a fourth NAND gate simultaneously again, and at the moment, when no fault exists and a pulse is input, the output of the third NAND gate and the fourth NAND gate is 0; when no pulse is input, the output of the third/fourth NAND gate is 1; when a fault exists, the output of the third/fourth NAND gate is 1 no matter whether the pulse input exists or not, so that the interlocking of PWM signals is realized, and the fault blocking is completed.

Therefore, the fault blocking of the PWM signal of the technical scheme of the invention is realized through the working mechanism.

As described above, the logic control unit 170 generates a corresponding driving control signal according to the PWM pulse signal after the fail-lock processing provided by the signal logic processing unit 150 and the fail latch signal provided by the fail latch unit 140, and outputs the driving control signal to the power output unit 180; a second output end of the logic control unit 170 is configured to perform power conversion on the driving control signal provided by the logic control unit 170, and generate and output a corresponding driving signal to control the IGBT driven by the two-level driver. It should be noted that, in the present embodiment, since the inner pipe IGBT and the outer pipe IGBT are driven, the drive control signal and the drive signal each include two drive signals, that is, a drive control signal that drives the inner pipe IGBT and a drive control signal that drives the outer pipe IGBT, and a drive signal that drives the inner pipe IGBT and a drive signal that drives the outer pipe IGBT.

In addition, the two-level driver further includes an external interface 190, which is disposed between the power monitoring unit 120, the state monitoring unit 130, and the power output unit 180, and the IGBT power device driven and controlled by the two-level driver, and is used for isolating and transmitting the driving voltage, the state parameter, and the driving control signal. Since it is the prior art, it is not described herein.

In addition, the NTC detecting unit 200 includes an NTC voltage dividing circuit 201 and a voltage-to-frequency converting circuit 202, forms a frequency signal varying with a resistance value of a resistor by sampling the resistance value of the NTC and voltage-to-frequency converting the sampled voltage, and outputs the frequency signal to an external controller for intelligent monitoring through the third sub-unit 163 of the signal isolating unit 160. The third sub-unit 163 of the signal isolating unit 160 serves for isolation of the NTC temperature signal.

It should be understood that the disclosed apparatus and method may be implemented in other ways in the several embodiments provided in this application. For example, the above-described apparatus embodiments are merely illustrative, and for example, a division of a unit is merely a logical division, and an actual implementation may have another division, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed.

It should be noted that the method of the embodiment of the present invention may be executed by a single device, such as a computer or a server. The method of the embodiment can also be applied to a distributed scene and completed by the mutual cooperation of a plurality of devices. In the case of such a distributed scenario, one of the multiple devices may only perform one or more steps of the method according to the embodiment of the present invention, and the multiple devices interact with each other to complete the method.

Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and alternate implementations are included within the scope of the preferred embodiment of the present invention in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present invention.

It should be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.

Although the embodiments of the present invention have been described above, the above description is only for the convenience of understanding the present invention, and is not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A two-level driver for driving an IGBT is characterized by comprising a fault latch unit, a logic control unit, a signal logic processing unit and a power output unit; wherein:

the second input end of the signal logic processing unit is connected with the output end of an external controller, the first output end of the signal logic processing unit is connected with the second input end of the logic control unit, and the signal logic processing unit is used for realizing the processing of interlocking and fault blocking of the PWM input signals according to the PWM input signals provided by the controller and the fault latch signals provided by the logic control unit and providing the PWM pulse signals obtained after the processing to the logic control unit;

the logic control unit is also used for generating and outputting a corresponding driving control signal according to the PWM pulse signal provided by the signal logic processing unit and the fault latch signal provided by the fault latch unit; the PWM pulse signal determines the high and low level of the driving control signal, and the fault latch signal controls the high and low level of the driving control signal to be turned off;

and the power output unit is connected with the second output end of the logic control unit and is used for performing power conversion on the driving control signal provided by the logic control unit, generating and outputting a corresponding driving signal so as to control the IGBT driven by the two-level driver.

2. The two-level driver for driving an IGBT according to claim 1, further comprising:

3. The two-level driver for driving an IGBT according to claim 1, further comprising:

4. The two-level driver for driving an IGBT according to claim 3, wherein the power supply unit includes:

5. The two-level driver for driving an IGBT according to claim 3, wherein the state monitoring unit includes:

a setting subunit, configured to set a state parameter threshold;

the monitoring subunit is used for acquiring state parameters of the IGBT driven by the two-level driver;

6. The two-level driver for driving an IGBT according to any of claims 3 to 5,

the power failure signal comprises an under-voltage failure signal;

the state parameters of the IGBT comprise a gate voltage signal and a gate voltage signal of the IGBT.

7. The two-level driver for driving an IGBT according to claim 1,

8. The two-level driver for driving an IGBT according to claim 7, wherein the signal logic processing unit includes a first subunit for implementing signal interlock and a second subunit for implementing signal fail-lock; wherein:

9. The two-level driver for driving an IGBT according to claim 1, further comprising an NTC detection unit which forms a frequency signal varying with a resistance value of the resistor by sampling the resistance value of the NTC and voltage-frequency converting the sampled voltage, and feeds the signal back to an external controller.

10. The two-level driver for driving an IGBT according to claim 1, wherein the second output terminal of the signal logic processing unit is externally connected to an input terminal of the controller for forwarding the fail latch signal provided by the logic control unit to the controller.