CN114447250B - Display panel and display device - Google Patents
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- CN114447250B CN114447250B CN202210096515.0A CN202210096515A CN114447250B CN 114447250 B CN114447250 B CN 114447250B CN 202210096515 A CN202210096515 A CN 202210096515A CN 114447250 B CN114447250 B CN 114447250B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K50/00—Organic light-emitting devices
- H10K50/80—Constructional details
- H10K50/805—Electrodes
- H10K50/82—Cathodes
- H10K50/822—Cathodes characterised by their shape
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/131—Interconnections, e.g. wiring lines or terminals
Abstract
The invention relates to the technical field of display, and discloses a display panel and a display device, wherein the display device comprises a display panel and a shell for mounting the display panel, the display panel is provided with a display area, and the display panel comprises a cathode layer and a signal line layer which are arranged at intervals; the cathode layer comprises a plurality of cathode patterns, and the cathode patterns are distributed in the display area at intervals; each cathode pattern is electrically connected with the signal line layer, so that the cathode patterns are connected in parallel through the signal line layer. The display panel and the display device provided by the invention have a better transparent display effect.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a display panel and a display device.
Background
The transparent display technology breaks through the conventional technology, increases the interest of products, brings unprecedented convenience and visual impact to people, and is popular in some creative design display and human-computer interaction fields. In addition, the transparent display panel can meet the backlight requirement by utilizing ambient light, so that the energy consumption is greatly reduced, and the environmental protection requirements of low carbon and green energy conservation are fully met.
In the correlation technique, transparent display panel's cathode layer passes through vacuum thermal evaporation technology and forms at the whole face coating by vaporization in the display area, because the light transmissivity of cathode layer is low, and external light hardly pierces through whole display panel, makes the user be difficult to see through display panel and sees the dorsal scene of display panel to lead to display panel's transparent display effect ideal inadequately.
Disclosure of Invention
The present invention is directed to a display panel, and aims to improve a transparent display effect of the display panel and ensure uniformity of display effects of each portion of the display panel.
In order to achieve the above object, the present invention provides a display panel, the display panel having a display area, the display panel including a cathode layer and a signal line layer arranged at an interval;
the cathode layer comprises a plurality of cathode patterns, and the cathode patterns are distributed in the display area at intervals;
each of the cathode patterns is electrically connected to the signal line layer such that the cathode patterns are connected in parallel by the signal line layer.
In an embodiment of the present invention, a pixel definition layer is disposed in the display region, and the pixel definition layer is located between the cathode layer and the signal line layer;
the pixel definition layer is provided with a plurality of first through holes, and part of the structure of each cathode pattern penetrates through one first through hole to be connected with the signal line layer.
In an embodiment of the invention, the pixel definition layer is further provided with a plurality of pixel definition openings, and each pixel definition opening is spaced apart from each first via hole;
the orthographic projection of each cathode pattern on the pixel definition layer shields one pixel definition opening.
In an embodiment of the invention, it is defined that each of the cathode patterns forms a shadow region by orthographic projection on the pixel defining layer, and a shortest distance between an edge of the shadow region and the pixel defining opening is greater than or equal to 3 μm.
In an embodiment of the present invention, an insulating layer is further disposed in the display area, and the cathode layer, the pixel defining layer, and the insulating layer are sequentially stacked;
the signal line layer is arranged in the insulating layer, the insulating layer is provided with a plurality of channels, each channel is communicated with one first through hole, and part of the structure of each cathode pattern penetrates through one first through hole and one channel to be connected with the signal line layer.
In one embodiment of the present invention, the insulating layer includes a planarization layer and a passivation layer, and the signal line layer is located in the passivation layer;
the flat layer is located between the passivation layer and the pixel defining layer, the flat layer is provided with a plurality of second through holes, the passivation layer is provided with a plurality of third through holes, and each second through hole is communicated with one third through hole to form the channel.
In an embodiment of the present invention, the insulating layer includes a planarization layer, a passivation layer and a dielectric layer stacked in sequence, and the signal line layer is located in the dielectric layer;
the flat layer is located between the passivation layer and the pixel defining layer, the flat layer is provided with a plurality of second through holes, the passivation layer is provided with a plurality of third through holes, the dielectric layer is provided with a plurality of fourth through holes, and each fourth through hole is communicated with one third through hole and one second through hole to form the channel.
In an embodiment of the invention, the signal line layer is disposed in the display area.
In an embodiment of the present invention, the signal line layer includes a plurality of signal lines, and the signal lines are arranged in a staggered manner and form a mesh structure;
each of the signal lines is connected to a plurality of the cathode patterns.
In addition, the invention also provides a display device which comprises a shell and the display panel, wherein the display panel is fixedly arranged on the shell.
According to the technical scheme, the cathode layer is arranged in the display area of the display panel, so that a plurality of cathode patterns are limited in the cathode layer, the cathode patterns are arranged at intervals, and each cathode pattern is electrically connected with the signal line layer in the display panel. Therefore, the cathode layer does not cover the display area of the display panel in a whole manner, the interval area is arranged between the adjacent cathode patterns, each cathode pattern cannot cover the display panel in a whole manner, and the interval area between the cathode patterns of the display panel can be transparent, so that the transparent display effect of the display panel can be improved. In addition, each cathode pattern is supplied with power in parallel through the signal line layer, and according to the parallel isobaric principle, when each cathode pattern is supplied with power through the signal line layer, the voltages loaded on each cathode pattern are equal, so that the uniformity of the display effect of different pixel display areas corresponding to each cathode pattern can be ensured.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
FIG. 1 is a schematic structural diagram of a cathode layer of a display panel according to the present invention;
FIG. 2 is a schematic diagram of a signal line layer of a display panel according to the present invention;
FIG. 3 is a cross-sectional view of the display panel of FIG. 1 taken along line H-H' in a first embodiment;
FIG. 4 is a cross-sectional view of the display panel of FIG. 1 taken along line H-H' in a second embodiment;
FIG. 5 is a cross-sectional view of the display panel of FIG. 1 taken along line H-H' in a third embodiment;
FIG. 6 is a schematic structural diagram of a cathode pattern in the cathode layer of FIG. 1;
FIG. 7 is another schematic diagram of the cathode pattern in the cathode layer of FIG. 1;
fig. 8 is a schematic view of another structure of the cathode pattern in the cathode layer shown in fig. 1.
The reference numbers indicate:
the implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without inventive step based on the embodiments of the present invention, are within the scope of protection of the present invention.
It should be noted that all directional indicators (such as up, down, left, right, front, back \8230;) in the embodiments of the present invention are only used to explain the relative positional relationship between the components, the motion situation, etc. in a specific posture (as shown in the attached drawings), and if the specific posture is changed, the directional indicator is changed accordingly.
In the present invention, unless otherwise explicitly stated or limited, the terms "connected", "fixed", and the like are to be understood broadly, for example, "fixed" may be fixedly connected, may be detachably connected, or may be integrated; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the present invention can be understood according to specific situations by those of ordinary skill in the art.
In addition, the descriptions related to "first", "second", etc. in the present invention are only for descriptive purposes and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. The meaning of "and/or" appearing throughout is the same and is meant to encompass three juxtapositions, exemplified by "A and/or B" and including either scheme A, scheme B, or both schemes A and B. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present invention.
The present invention provides a display panel for image display, which is an electroluminescent display panel, such as an OLED display panel.
In an embodiment of the present invention, as shown in fig. 1 and fig. 2, the display panel has a display area a, and the display panel includes a cathode layer 1 and a signal line layer 2 arranged at intervals; the cathode layer 1 comprises a plurality of cathode patterns 11, and each cathode pattern 11 is distributed in the display area a at intervals; each of the cathode patterns 11 is electrically connected to the signal line layer 2 such that the cathode patterns 11 are connected in parallel through the signal line layer 2.
In this embodiment, the cathode layer 1 in the display panel is used to provide electrons matching with holes generated by the anode, when the anode and the cathode in the display panel are simultaneously applied with a voltage, the cathode outputs electrons, the anode outputs holes matching with the electrons, the electrons and the holes are combined in the light-emitting layer 5 to form electron-hole pairs, i.e. excitons, at a bound energy level, the excitons radiate and de-excite to emit photons, thereby generating visible light, and realizing image display of the display panel. A plurality of cathode patterns 11 are arranged in the cathode layer 1, each cathode pattern 11 can be formed on a film layer in the display panel by a metal mask through a one-time evaporation process, and a plurality of cathode patterns 11 distributed at intervals can be correspondingly formed by arranging a plurality of openings arranged at intervals on the metal mask. After each cathode pattern 11 is formed, a spacing area is formed between adjacent cathode patterns 11, the cathode layer 1 does not cover the whole surface of the display panel, and the display panel can pass through the spacing area between the cathode patterns 11, so that the light-transmitting display effect of the display panel is improved.
The signal line layer 2 is used for providing voltage for the cathode, the signal line layer 2 may be disposed in the display area a of the display panel or in the non-display area B outside the display area a, the signal line layer 2 and the cathode layer 1 are disposed on different layers in the display panel, for example, the cathode layer 1 may be located above the signal line layer 2. The signal line layer 2 is electrically connected to each cathode pattern 11, so that each cathode pattern 11 is connected in parallel through the signal line layer 2, and thus, when each cathode pattern 11 is supplied with power through the signal line layer 2 according to the parallel isobaric principle, the voltages applied to each cathode pattern 11 are equal, thereby ensuring the uniformity of the display effect, such as the uniformity of the display brightness and the color, of each pixel display area a corresponding to each cathode pattern 11.
Optionally, refer to fig. 2, locate cathode layer 1 and signal line layer 2 in display area a, signal line layer 2 no longer need arrange through display panel's non-display area B, thereby can cancel the setting of non-display area B on the display panel, keep display panel's display area a, with this frame that can greatly narrow display panel, reduce display panel's volume, weight and manufacturing cost, realize the design that display panel is lighter-weight, also be favorable to promoting the screen that adopts this display panel's display device to account for simultaneously and compare, improve corresponding display device's visual impression. With continued reference to fig. 2, to realize the arrangement of the cathode layer 1 into the display area a, the signal lines 21 in the signal line layer 2 may be arranged in a staggered manner to form a mesh structure, and each signal line 21 is connected to a plurality of cathode patterns 11. Therefore, on one hand, the parallel electrical relationship can be formed between the cathode patterns 11 connected with the same signal line 21, the voltage loading on the cathode patterns 11 connected with any signal line 21 is consistent, and the uniformity of the display effect of the pixel display area A corresponding to each cathode pattern 11 is realized; on the other hand, the signal line layer 2 can be easily extended and arranged to cover the entire display area a of the display panel, each cathode pattern 11 can be connected to the signal line 21 nearby, the power supply distance from the signal line layer 2 to the cathode pattern 11 is shortened, the power supply response time of each cathode pattern 11 is shortened, the display efficiency of the pixel display area a corresponding to each cathode pattern 11 is improved, the extension length of the connection structure for connecting the signal line layer 2 and the cathode pattern 11 can be shortened, and the manufacturing cost of the display panel is reduced.
In an embodiment of the invention, as shown in fig. 3, a pixel definition layer 3 is disposed in the display area a of the display panel in the above embodiment, and the pixel definition layer 3 is located between the cathode layer 1 and the signal line layer 2; the pixel defining layer 3 is provided with a plurality of first via holes 3a, and a part of the structure of each cathode pattern 11 passes through one first via hole 3a to be connected with the signal line layer 2.
In the present embodiment, the pixel defining layer 3 is used for defining a pixel display area a, and a plurality of pixel display areas a are definable and defined in the pixel defining layer 3, and each pixel display area a can be controlled to be expressed by a corresponding cathode pattern 11 to display a corresponding color. The pixel definition layer 3 is provided with a plurality of first via holes 3a, the first via holes 3a are used for the cathode patterns 11 to pass through, so as to realize the connection between the cathode patterns 11 and the signal lines 21 in the signal line layer 2, and the lower openings of the first via holes 3a are adjacent to one signal line 21 in the signal line layer 2.
The cathode pattern 11 can be formed on a side of the pixel defining layer 3 opposite to the signal line layer 2 through an evaporation process, when the pixel defining layer 3 is provided with a first via hole 3a, the cathode pattern 11 covers at least a part of an inner wall of the first via hole 3a through the evaporation process, a cathode opening 11a is formed on the cathode pattern 11, and a partial structure of the cathode pattern 11 is connected with the signal line 21 at the lower opening of the first via hole 3a through the first via hole 3a, so that the connection between each cathode pattern 11 and the signal line 21 in the signal line layer 2 is realized.
In the embodiment, the first via hole 3a is formed in the pixel defining layer 3, and a part of the structure of each cathode pattern 11 passes through the first via hole 3a to be connected to one signal line 21, so that the process and cost of the related process for connecting the cathode patterns 11 and the signal lines 21 are saved, the arrangement of the cathode patterns 11 and the signal lines 21 in the display panel is compact, and the thickness of the display panel is reduced.
In an embodiment of the present invention, as shown in fig. 3, the pixel definition layer 3 in the above embodiment further has a plurality of pixel definition openings 3b, and each pixel definition opening 3b and each first via hole 3a are disposed at an interval; the orthographic projection of each cathode pattern 11 on the pixel definition layer 3 shields a pixel definition opening 3b.
In the present embodiment, the pixel defining opening 3b is used for exposing the anode and disposing the light emitting layer 5, the light emitting layer 5 is disposed in the pixel defining opening 3b and between the cathode and the anode, and the light emitting layer 5 is used for emitting visible light to realize the display of the corresponding pixel display area a on the pixel defining layer 3.
As further shown in any one of fig. 6 to 8, in the vertical light-emitting direction of the display panel, the projection of each cathode pattern 11 on the pixel defining layer 3 shields a pixel defining opening 3b and a first via hole 3a, so that the area range of the cathode pattern 11 can cover the area range of the light-emitting layer 5 in the pixel defining opening 3b, and the light-emitting layer 5 can emit light. In order to further reduce the coverage area of the cathode layer 1 on the display area a on the basis of satisfying that a cathode pattern 11 shields a pixel defining opening 3b in the vertical light-emitting direction of the display panel, the present embodiment also improves the shape and size of the cathode pattern 11. Specifically, the present embodiment designs each cathode pattern 11 to a shape matching the pixel defining opening 3b and the first via hole 3a, for example, as shown in fig. 6, when the pixel defining opening 3b and the first via hole 3a are square holes, the shape of the cathode pattern 11 is also made to two squares respectively matching and connecting the outer shapes of the pixel defining opening 3b and the first via hole 3 a; as another example, as shown in fig. 7, when the pixel defining opening 3b and the first via hole 3a are hexagonal holes, the cathode pattern 11 is also shaped into two hexagons that are respectively matched with and connected to the outer shapes of the pixel defining opening 3b and the first via hole 3 a; as another example, as shown in fig. 8, when the pixel defining opening 3b and the first via hole 3a are circular or elliptical holes, the cathode pattern 11 is also shaped into two circular or elliptical shapes that match and connect with the outer shapes of the pixel defining opening 3b and the first via hole 3a, respectively.
In addition, when the cathode pattern 11 can shield a pixel defining opening 3b and a first via hole 3a in the vertical light emitting direction of the display panel, the outer edge of the cathode pattern 11 and the pixel defining opening 3b and the first via hole 3a are kept at the shortest distance as possible, for example, each cathode pattern 11 is defined to form a shadow region by orthographic projection on the pixel defining layer 3, the shortest distance d between the edge of the shadow region and the pixel defining opening 3b is greater than or equal to 3 μm and is as close to 3 μm as possible, for example, d is greater than or equal to 3 μm and less than or equal to 6 μm, so as to avoid having higher precision requirements on the design and the related processes of the cathode pattern 11 when d is less than 3 μm, increase the difficulty of the related process processes, and when d is greater than 3 μm, the area of the cathode pattern 11 is larger to improve the transparent display effect of the display panel. The present embodiment further reduces the area of a single cathode pattern 11 in the above-mentioned manner of shape matching and size reduction in the manufacturing process, so that when each cathode pattern 11 is designed similarly, the coverage area of the cathode layer 1 on the display area a is greatly reduced, and the transparent display effect of the display panel is further improved.
In an embodiment of the invention, as shown in fig. 3, an insulating layer 4 is further disposed in the display area a in the above embodiment, wherein the cathode layer 1, the pixel defining layer 3 and the insulating layer 4 are sequentially stacked; the signal line layer 2 is disposed in the insulating layer 4, the insulating layer 4 is provided with a plurality of channels 4a, each channel 4a is communicated with a first via hole 3a, and a part of the structure of each cathode pattern 11 is connected with the signal line layer 2 through a first via hole 3a and a channel 4a.
In this embodiment, the cathode pattern 11 may be formed on a side of the pixel defining layer 3 opposite to the signal line layer 2 through an evaporation process, when the pixel defining layer 3 has a first via hole 3a and the insulating layer 4 has a channel 4a, the cathode pattern 11 covers at least a portion of an inner wall of the first via hole 3a and the channel 4a through the evaporation process, a cathode opening 11a is formed on the cathode pattern 11, and a portion of the cathode pattern 11 is connected to the signal line layer 2 at a lower opening of the channel 4a through the first via hole 3a and the channel 4a. Therefore, by arranging the cathode layer 1 in the insulating layer 4, each cathode pattern 11 is connected with the signal line layer 2 through the first via hole 3a and the channel 4a, and the insulating isolation between the signal line 21 and other metal layers in the display panel is realized by using the insulating layer 4, so that the stable and reliable power supply of the signal line layer 2 to the cathode patterns 11 can be ensured; meanwhile, the signal line layer 2 can be arranged in the inherent insulating layer 4 level space in the display panel, and the signal line layer 2 does not only occupy the level space in the display panel, so that the arrangement of the signal line 21 in the display area A of the display panel is realized under the condition of not changing the thickness of the display panel, the thinning design of the display panel is facilitated, and the effect of narrowing the frame of the display panel is also achieved.
In order to balance the process difficulty and the light and thin design requirements of the display panel, when the signal line layer 2 is manufactured in the display area a of the display panel, the following embodiment scheme can be adopted in the invention:
first embodiment
As shown in fig. 3, the insulating layer 4 in the above embodiment includes a planarization layer 41 and a passivation layer 42, and the signal line layer 2 is disposed in the passivation layer 42; the planarization layer 41 is disposed between the passivation layer 42 and the pixel defining layer 3, a plurality of second via holes 41a are disposed on the planarization layer 41, a plurality of third via holes 42a are disposed on the passivation layer 42, and each second via hole 41a is communicated with one third via hole 42a to form a channel 4a in the above embodiment.
In this embodiment, by disposing the signal line layer 2 in the passivation layer 42, the signal line layer 2 is disposed as close to the pixel defining layer 3 and the cathode layer 1 as possible, the depth of the channel 4a formed by communicating the second via hole 41a with the third via hole 42a, which needs to be etched, can be reduced, the time and difficulty of the corresponding etching process are reduced, and the efficiency of manufacturing the display panel is improved, and meanwhile, by disposing the signal line layer 2 in the passivation layer 42, the signal line layer 2 can be disposed by using the inherent level space in the display panel, and the signal line layer 2 does not occupy the level space in the display panel exclusively, so that the arrangement of the signal line 21 in the display area a of the display panel is realized without changing the thickness of the display panel, which is beneficial to the thinning design of the display panel.
Second embodiment
As shown in fig. 4, the present embodiment is different from the first embodiment in that the insulating layer 4 further includes a dielectric layer 43 disposed below the passivation layer 42, wherein the dielectric layer 43 includes a first dielectric layer 431 and a second dielectric layer 432, the first dielectric layer 431 is located between the passivation layer 42 and the second dielectric layer 432, and the signal line layer 2 is no longer disposed on the passivation layer 42 but is disposed within the first dielectric layer 431; the first dielectric layer 431 is provided with a plurality of fourth vias 43a, and each fourth via 43a is communicated with a third via 42a and a second via 41a to form the channel 4a.
In the embodiment, the first dielectric layer 431 has a thicker layer thickness than the passivation layer 42, and the area of the layer space where the first dielectric layer 431 is located is wider, so that when the signal line layer 2 is disposed in the first dielectric layer 431, the signal line layer 2 can be more easily arranged, which is beneficial to reducing the difficulty of the corresponding process, and the signal line layer 2 has a structure with a more uniform thickness in the first dielectric layer 431, thereby improving and balancing the thickness of the film layer in the display panel.
Third embodiment
As shown in fig. 5, the present embodiment is different from the second embodiment in that the signal line layer 2 is no longer disposed within the first dielectric layer 431 but disposed within the second dielectric layer 432; the second dielectric layer 432 and the first dielectric layer 431 are both provided with a plurality of fourth vias 43a, and each fourth via 43a of the second dielectric layer 432 is communicated with a fourth via 43a, a third via 42a and a second via 41a of the first dielectric layer 431 to form the channel 4a.
In the embodiment, the second dielectric layer 432 has a thicker layer thickness than the first dielectric layer 431, and the area of the layer space where the second dielectric layer 432 is located is wider, so that when the signal line layer 2 is disposed in the second dielectric layer 432, the signal line layer 2 can be more easily arranged, which is beneficial to reducing the difficulty of the corresponding process, and the signal line layer 2 has a structure with a more uniform thickness in the second dielectric layer 432, thereby improving and balancing the thickness of the inner film of the display panel.
The invention also provides a display device, which comprises a shell and the display panel in the embodiment, wherein the display panel is fixedly arranged on the shell.
In this embodiment, a containing groove is formed in the housing, the display panel is mounted and fixed in the containing groove, and the housing performs isolation protection on the display panel. The specific structure of the display panel refers to the above embodiments, and since the display device adopts all technical solutions of all the above embodiments, at least all the beneficial effects brought by the technical solutions of the above embodiments are achieved, and no further description is given here.
The above description is only an alternative embodiment of the present invention, and not intended to limit the scope of the present invention, and all modifications and equivalents of the present invention, which are made by the contents of the present specification and the accompanying drawings, or directly/indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (8)
1. A display panel is provided with a display area and is characterized by comprising cathode layers and signal line layers which are arranged at intervals;
the cathode layer comprises a plurality of cathode patterns, and the cathode patterns are distributed in the display area at intervals;
each cathode pattern is electrically connected with the signal line layer, so that the cathode patterns are connected in parallel through the signal line layer;
a pixel defining layer is arranged in the display area and is positioned between the cathode layer and the signal line layer;
the pixel definition layer is provided with a plurality of first through holes and a plurality of pixel definition openings, and each pixel definition opening and each first through hole are arranged at intervals; the orthographic projection of each cathode pattern on the pixel definition layer shields one pixel definition opening, and part of the structure of each cathode pattern passes through one first through hole to be connected with the signal line layer;
and defining the orthographic projection of each cathode pattern on the pixel defining layer to form a shadow area, wherein the distance between the edge of the shadow area and the pixel defining opening is more than or equal to 3 μm and less than or equal to 6 μm.
2. The display panel according to claim 1, wherein an insulating layer is further provided in the display region, and the cathode layer, the pixel defining layer, and the insulating layer are sequentially stacked;
the signal line layer is arranged in the insulating layer, the insulating layer is provided with a plurality of channels, each channel is communicated with one first via hole, and part of the structure of each cathode pattern penetrates through one first via hole and one channel to be connected with the signal line layer.
3. The display panel according to claim 2, wherein the insulating layer includes a planarization layer and a passivation layer, the signal line layer being located in the passivation layer;
the flat layer is located between the passivation layer and the pixel definition layer, the flat layer is provided with a plurality of second through holes, the passivation layer is provided with a plurality of third through holes, and each second through hole is communicated with one third through hole to form the channel.
4. The display panel according to claim 2, wherein the insulating layer includes a planarization layer, a passivation layer, and a dielectric layer stacked in this order, the signal line layer being located within the dielectric layer;
the flat layer is located between the passivation layer and the pixel defining layer, the flat layer is provided with a plurality of second through holes, the passivation layer is provided with a plurality of third through holes, the dielectric layer is provided with a plurality of fourth through holes, and each fourth through hole is communicated with one third through hole and one second through hole to form the channel.
5. The display panel according to any one of claims 1 to 4, wherein the signal line layer is provided in the display region.
6. The display panel according to claim 5, wherein the signal line layer includes a plurality of signal lines, the signal lines being alternately arranged and forming a mesh structure;
each of the signal lines is connected to a plurality of the cathode patterns.
7. The display panel of claim 1, wherein the shape of each of the cathode patterns matches the shape of a first via, the pixel-defining opening obscured by the orthographic projection of the cathode pattern;
wherein the first via hole and the pixel defining aperture are one of a square hole, a hexagonal hole, an elliptical hole, and a circular hole.
8. A display device characterized by comprising a housing and the display panel according to any one of claims 1 to 7, the display panel being fixedly mounted to the housing.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104465711A (en) * | 2014-12-30 | 2015-03-25 | 京东方科技集团股份有限公司 | AMOLED array substrate, manufacturing method of AMOLED array substrate and displaying device |
| CN106784375A (en) * | 2016-12-27 | 2017-05-31 | 武汉华星光电技术有限公司 | OLED display unit and preparation method thereof |
| CN210349841U (en) * | 2019-09-19 | 2020-04-17 | 昆山工研院新型平板显示技术中心有限公司 | Display panel and display device |
| CN112151696A (en) * | 2020-09-28 | 2020-12-29 | 京东方科技集团股份有限公司 | Display panel and display device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6900470B2 (en) * | 2001-04-20 | 2005-05-31 | Kabushiki Kaisha Toshiba | Display device and method of manufacturing the same |
| CN103715205B (en) * | 2013-12-31 | 2016-04-13 | 京东方科技集团股份有限公司 | AMOLED array basal plate and display unit |
-
2022
- 2022-01-26 CN CN202210096515.0A patent/CN114447250B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104465711A (en) * | 2014-12-30 | 2015-03-25 | 京东方科技集团股份有限公司 | AMOLED array substrate, manufacturing method of AMOLED array substrate and displaying device |
| CN106784375A (en) * | 2016-12-27 | 2017-05-31 | 武汉华星光电技术有限公司 | OLED display unit and preparation method thereof |
| CN210349841U (en) * | 2019-09-19 | 2020-04-17 | 昆山工研院新型平板显示技术中心有限公司 | Display panel and display device |
| CN112151696A (en) * | 2020-09-28 | 2020-12-29 | 京东方科技集团股份有限公司 | Display panel and display device |
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| CN114447250A (en) | 2022-05-06 |
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