CN114447149A - Edge incidence detector and manufacturing method thereof - Google Patents
Edge incidence detector and manufacturing method thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
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- H01L21/3065—Plasma etching; Reactive-ion etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/085—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors the device being sensitive to very short wavelength, e.g. X-ray, Gamma-rays
Abstract
The invention provides an edge incidence detector and a manufacturing method thereof, the detector comprises a semiconductor layer, an isolation layer, a first electrode layer, a conducting layer and a second electrode layer, wherein the semiconductor layer comprises a first conduction type doping layer positioned on the surface layer of the back of the semiconductor layer and a plurality of second conduction type body regions positioned on the surface layer of the front of the semiconductor layer, the isolation layer is positioned on the upper surface of the semiconductor layer and comprises a plurality of grooves arranged at intervals and a first opening positioned at the bottom of the groove and exposing the body regions, the first electrode layer is positioned on the upper surface of the isolation layer and fills the grooves and is electrically contacted with the body regions through the first opening, the conducting layer is positioned on the side walls of the semiconductor layer and the isolation layer and is electrically contacted with the doping layer, and the second electrode layer is positioned on the back of the semiconductor layer and is electrically contacted with the doping layer. According to the invention, the first conductive type conducting layer in electrical contact with the semiconductor layer is arranged on the side wall of the semiconductor layer, so that the protection ring is avoided, the dead zone area is reduced, and the X-ray collection efficiency is improved.
Description
Technical Field
The invention belongs to the field of X-ray detectors, and relates to an edge incident detector and a manufacturing method thereof.
Background
The photon counting X-ray detector can analyze each incident photon as an independent event, can count X-ray energy partitions with wide energy spectrums and judge the energy intervals to which the X-ray energy partitions belong, so that the photon counting X-ray detector has energy spectrum resolution capability and has excellent performance when being applied to medical imaging equipment such as a Computed Tomography (CT).
Because of the low atomic number of silicon, when detecting high-energy X-rays in Computed Tomography (CT), the silicon detector needs to be vertically placed so that X-rays enter from the side to increase the absorption depth of the X-rays, i.e., deep silicon detection.
In order to maximize the sensitive area of the detector, the detector works in a fully depleted state, and a high voltage of at least 200V is required for a silicon substrate with the thickness of 500 mu m, so that the electric field at the surface is increased, and the breakdown of the device is easily caused; if the lateral depletion region extends into the region of the lattice damage introduced by the slicing, the leakage current of the device will increase.
At present, a plurality of suspended guard rings are generally arranged around a pixel of an edge-incident silicon strip detector to expand a surface electric field, increase breakdown voltage, collect peripheral leakage current by using a first guard ring, and reduce leakage current of a pixel region. As shown in fig. 1 and fig. 2, the schematic diagram of a top view of a multi-guard ring detector structure and a cross-sectional structure of the multi-guard ring detector includes a guard ring 01, a contact hole 02, a pixel 03, a substrate 031, a body region 032, a doping layer 033, a front electrode 034, a back electrode 035, and an isolation layer 036. The more the number of the guard rings is, the more obvious the effect on improving the breakdown voltage is. The guard ring typically has an overall width of 1.5 to 3 times the thickness of the substrate. However, the guard rings may form a dead region of the detector, which in turn causes X-photons incident on the region to be not collected, making X-ray collection less efficient.
Therefore, there is an urgent need to find an edge incident detector that improves X-ray collection efficiency, reduces the dead area of the detector, and avoids using a large area of the protection ring.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide an edge incident detector and a method for manufacturing the same, which are used to solve the problems of large dead area and low X-ray collection efficiency caused by applying a protection ring to the prior art detector.
To achieve the above and other related objects, the present invention provides a method for manufacturing an edge incident detector, comprising the steps of:
providing a first conductive type detector wafer, and forming a first conductive type doping layer on the back surface of the wafer, wherein the wafer comprises at least one detector forming area;
providing a supporting substrate, bonding the wafer to the bearing substrate, wherein the back surface of the wafer faces the bearing substrate, and thinning the wafer from the front surface of the wafer to a preset thickness;
forming an isolation layer on the front surface of the wafer, forming a plurality of grooves arranged at intervals in the isolation layer, and forming a second conductive type body region in the wafer through the grooves;
forming a groove penetrating through the isolation layer and the wafer on the edge of the detector forming area, wherein the supporting substrate is exposed at the bottom of the groove, a first conductive type conducting layer is formed on the side wall of the groove, and the conducting layer is in electric contact with the doping layer;
forming a first opening at the bottom of the groove to expose the body region;
and forming a first electrode layer which is electrically contacted with the body region through the first opening, removing the bearing substrate, and forming a second electrode layer which is electrically contacted with the doped layer on the back surface of the wafer to form the detector.
Optionally, after thinning, the thickness of the wafer ranges from 150 μm to 500 μm.
Optionally, the thickness of the isolation layer is in the range of
Optionally, the distance range from the bottom of the groove to the front surface of the wafer is
Optionally, a step of annealing the activated impurities is further included after the body region is formed.
Optionally, forming the trench further comprises:
forming a hard mask layer covering the isolation layer and filling the groove on the upper surface of the isolation layer, and patterning the hard mask layer;
and etching the isolation layer and the wafer based on the hard mask layer to form the groove which penetrates through the isolation layer and the wafer and exposes the support substrate from the bottom, and removing the hard mask layer.
Optionally, the width of the trench ranges from 15 μm to 25 μm.
Optionally, the method of forming the trench comprises deep reactive ion etching.
Optionally, forming the conductive layer further comprises:
forming a conductive material layer on the inner wall of the groove, the upper surface of the isolation layer and the groove;
and removing the conductive material layer on the upper surface of the isolation layer and in the groove to form the conductive layer on the inner wall of the groove.
Optionally, after the first electrode layer is formed, a passivation layer is formed on the upper surface of the first electrode layer.
The present invention also provides an edge incident detector, comprising:
the semiconductor layer comprises a first conductive type doping layer positioned on the surface layer of the back surface of the semiconductor layer and a plurality of second conductive type body regions positioned on the surface layer of the front surface of the semiconductor layer;
the isolation layer is positioned on the upper surface of the semiconductor layer and comprises a plurality of grooves arranged at intervals and first openings which are positioned at the bottoms of the grooves and expose the body regions;
the first electrode layer is positioned on the upper surface of the isolation layer, fills the groove and is electrically contacted with the body region through the first opening;
the conducting layer is positioned on the side surfaces of the semiconductor layer and the isolating layer and is electrically contacted with the doping layer;
and the second electrode layer is positioned on the back surface of the semiconductor layer and is electrically contacted with the doped layer.
Optionally, the first conductivity type includes one of an N type or a P type, the second conductivity type includes one of an N type or a P type, and the first conductivity type is opposite to the second conductivity type.
Optionally, the upper surface of the first electrode layer is further provided with a passivation layer.
Optionally, the width of the first opening is smaller than the width of the groove bottom.
As described above, the edge incident detector and the manufacturing method thereof of the present invention form the trench with the bottom exposing the supporting substrate at the edge of the detector forming region by using the deep reactive ion etching method, thereby avoiding introducing lattice damage during blade slicing, which in turn causes excessive leakage current, omitting introducing a large leakage current prevention guard ring at the edge of the detector, reducing the area of a dead zone, increasing the fill factor (ratio of photosensitive area to whole pixel area) of the sensitive region of the detector, and in turn increasing the collection efficiency of X-rays, forming the first conductive type conductive layer electrically contacting with the doping layer on the sidewall of the trench, and the conductive layer on the side wall of the groove is used as the extension of ohmic contact of the back plate, so that the sensitive detector edge is obtained. In addition, the second electrode of the detector can be led to the front side of the wafer through the conductive layer, so that the detector is convenient to package, and the industrial utilization value is high.
Drawings
FIG. 1 shows a top view of a multi-guard ring edge incident detector.
FIG. 2 is a schematic cross-sectional view of a multi-guard ring edge incident detector.
FIG. 3 is a flow chart of a method of making an edge incident detector of the present invention.
Fig. 4 is a schematic cross-sectional view of the doped layer formed by the method for fabricating the edge incident detector according to the present invention.
Fig. 5 is a schematic cross-sectional view of a bonded supporting substrate of the method for fabricating an edge incident detector according to the present invention.
Fig. 6 is a schematic cross-sectional view of a thinned front surface of a wafer according to the method for fabricating an edge incident detector of the present invention.
FIG. 7 is a schematic cross-sectional view of an isolation layer formed according to the method for fabricating an edge incident detector of the present invention.
FIG. 8 is a schematic cross-sectional view of the edge incident detector after forming the groove according to the method of the present invention.
FIG. 9 is a schematic cross-sectional view of the method for fabricating an edge-incident detector according to the present invention after forming the body region.
Fig. 10 is a schematic cross-sectional view of the trench formed by the method for fabricating an edge incident detector according to the present invention.
FIG. 11 is a schematic cross-sectional view of a conductive material layer formed by the method of fabricating an edge incident detector according to the present invention.
FIG. 12 is a schematic cross-sectional view showing the conductive layer formed according to the method for fabricating the edge incident detector of the present invention.
Fig. 13 is a schematic cross-sectional view of the first electrode layer formed by the method of manufacturing the edge incident detector according to the present invention.
FIG. 14 is a schematic cross-sectional view of the second electrode layer formed according to the method for fabricating the edge incident detector of the present invention.
Description of the element reference numerals
01 guard ring
02 contact hole
03 pixel point
031 substrate
032 body region
033 doping layer
034 front electrode
035 back electrode
036 isolating layer
1 wafer
10 detector formation region
11 doped layer
12 body region
13 groove
2 support substrate
3 isolating layer
31 groove
32 opening
4 layer of conductive material
41 conductive layer
5 first electrode layer
6 second electrode layer
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 3 to 14. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
Example one
The present embodiment provides a method for manufacturing an edge incident detector, as shown in fig. 3, which is a flowchart of a manufacturing method for forming the edge incident detector, and includes the following steps:
s1: providing a first conductive type detector wafer, and forming a first conductive type doping layer on the back surface of the wafer, wherein the wafer comprises at least one detector forming area;
s2: providing a supporting substrate, bonding the wafer to the bearing substrate, wherein the back surface of the wafer faces the bearing substrate, and thinning the wafer from the front surface of the wafer to a preset thickness;
s3: forming an isolation layer on the front surface of the wafer, forming a plurality of grooves arranged at intervals in the isolation layer, and forming a second conductive type body region in the wafer through the grooves;
s4: forming a groove penetrating through the isolation layer and the wafer on the edge of the detector forming area, wherein the supporting substrate is exposed at the bottom of the groove, a first conductive type conducting layer is formed on the side wall of the groove, and the conducting layer is in electric contact with the doping layer;
s5: forming a first opening at the bottom of the groove to expose the body region;
s6: and forming a first electrode layer which is electrically contacted with the body region through the first opening, removing the bearing substrate, and forming a second electrode layer which is electrically contacted with the doped layer on the back surface of the wafer to form the detector.
Referring to fig. 4 to 6, the steps S1 and S2 are executed: providing a first conductive type detector wafer 1, and forming a first conductive type doping layer 11 on the back surface of the wafer 1, wherein the wafer 1 comprises at least one detector forming region; providing a supporting substrate 2, bonding the wafer 1 to the bearing substrate 2, wherein the back surface of the wafer 1 faces the bearing substrate 1, and thinning the wafer 1 from the front surface of the wafer 1 to a preset thickness.
Specifically, the wafer 1 is a first conductivity type semiconductor wafer with high resistivity. In this embodiment, the first conductivity type is N-type, an N-type silicon wafer with high resistivity is selected as the wafer 1, and the wafer 1 includes one detector forming region.
Specifically, as shown in fig. 4, in order to form the doped layer 11, the doped layer 11 is formed on the back surface of the wafer 1 by ion implantation or other suitable methods. In this embodiment, a phosphorous ion source is adopted, and ions are implanted from the back side of the wafer 1 by using an ion implantation method, the phosphorous ion source includes phosphorous to obtain the doped layer 11, and the thickness of the doped layer 11 is determined according to actual conditions and is not limited.
Specifically, the material of the support substrate 2 includes one of glass, ceramic, and semiconductor, and may be other suitable materials. In this embodiment, a semiconductor wafer is used as the support substrate 2.
Specifically, as shown in fig. 5, a cross-sectional structure of the wafer 1 bonded to the supporting substrate 2 is schematically illustrated, and the method for bonding the wafer 1 to the supporting substrate 2 includes pasting, electrostatic bonding, direct bonding, or other suitable methods.
Specifically, the method for thinning the wafer 1 includes chemical mechanical polishing or other suitable methods.
As an example, as shown in fig. 6, a schematic cross-sectional structure of the thinned wafer 1 is shown, and after the thinning, the thickness of the wafer 1 ranges from 150 μm to 500 μm.
Referring to fig. 7 to 9, the step S3 is executed: forming an isolation layer 3 on the front surface of the wafer 1, forming a plurality of grooves 31 arranged at intervals in the isolation layer 3, and forming a second conductive type body region 12 in the wafer 1 through the grooves 31.
Specifically, the method for forming the isolation layer 3 includes a thermal oxidation method, chemical vapor deposition, physical vapor deposition, or other suitable methods.
As an example, as shown in fig. 7, in order to show the cross-sectional structure after forming the isolation layer 3, the thickness of the isolation layer 3 is within a range of
Specifically, the material of the isolation layer 3 includes silicon dioxide, silicon nitride, or other suitable materials. In this embodiment, a silicon dioxide layer is used as the isolation layer 3.
Specifically, the method for forming the groove 31 includes dry etching, wet etching or other suitable methods.
As an example, as shown in fig. 8, in order to show the cross-sectional structure after the formation of the groove 31, the distance range from the bottom of the groove 31 to the front surface of the wafer 1 is
Preferably, the bottom of the groove 31 is spaced from the front surface of the wafer 1 by a distance of
Specifically, as shown in fig. 9, in order to form the cross-sectional structure after the body region 12, the body region 12 is formed by ion implantation or other suitable methods. In this embodiment, the second conductivity type is P-type, and the body region 12 is formed by ion implantation using a boron ion source, which may include B2H6，BF2The thin isolation layer at the bottom of the groove 31 serves as a masking layer during ion implantation, so that a channel effect generated during ion implantation is avoided, and the depth of the body region 12 is not uniform.
Illustratively, the step of annealing the activated impurities is included after forming the body region 12. In this embodiment, more impurity particles are activated by annealing, so that the impurity particles are heated and diffused, the impurity particles are prevented from being accumulated on the surface of the detector formation region, and defects in the detector formation region due to ion implantation are repaired.
Referring to fig. 10 to 12 again, the steps S4 and S5 are executed: forming a trench 13 penetrating through the isolation layer 3 and the wafer 1 at an edge of the detector formation region 10, wherein the support substrate 2 is exposed at a bottom of the trench 13, and a first conductive type conductive layer 41 is formed on a sidewall of the trench 13, and the conductive layer 41 is in electrical contact with the doped layer 11; a first opening 32 is formed at the bottom of the recess 31 to expose the body region 12.
As an example, as shown in fig. 10, in order to schematically illustrate a cross-sectional structure after the trench 13 is formed, the forming of the trench 13 further includes the following steps:
forming a hard mask layer covering the isolation layer 3 and filling the groove 31 on the upper surface of the isolation layer 3, and patterning the hard mask layer;
and etching the isolation layer 3 and the wafer 1 based on the hard mask layer to form the groove 13 which penetrates through the isolation layer 3 and the wafer 1 and exposes the support substrate 2 from the bottom, and removing the hard mask layer.
As an example, the width of the trench 13 ranges from 15 μm to 25 μm, and preferably, the width of the trench 13 is 20 μm.
As an example, the method of forming the trench 13 includes deep reactive ion etching or other suitable methods.
As an example, forming the conductive layer 41 further includes the steps of:
forming a conductive material layer 4 on the inner wall of the trench 13, the upper surface of the isolation layer 3 and the groove 31;
removing the conductive material layer 4 on the upper surface of the isolation layer 3 and in the groove 31 to form the conductive layer 41 on the inner wall of the trench 13.
Specifically, as shown in fig. 11, for a cross-sectional structural schematic view presented after the conductive material layer 4 is formed, a material of the conductive material layer 4 includes first conductive type doped polysilicon or other suitable conductive materials, wherein a thickness of the conductive material layer 4 is determined according to an actual situation, which is not limited herein.
Specifically, the method for forming the conductive material layer 4 includes chemical vapor deposition, physical vapor deposition, or other suitable methods. In this embodiment, the conductive material layer 4 is formed by a chemical vapor deposition method, and a first conductive type impurity is doped into a reaction gas during the deposition process, so that the conductive type of the conductive material layer 4 is the first conductive type.
Specifically, as shown in fig. 12, in order to form a schematic cross-sectional structure of the conductive layer 41, the method for removing the upper surface of the isolation layer 3 and the conductive material layer 4 in the groove 31 includes at least one of dry etching, wet etching, and chemical mechanical polishing, or other suitable methods.
Specifically, the conductivity type of the conductive material layer 4 on the inner wall of the trench 13 may also be the first conductivity type by using a sidewall tilt angle ion implantation method.
Specifically, the method for forming the first opening 32 includes dry etching, wet etching or other suitable methods.
Referring to fig. 13 to 14, the step S6 is executed: forming a first electrode layer 5 in electrical contact with the body region 12 through the first opening 32, removing the carrier substrate 2, and forming a second electrode layer 6 in electrical contact with the doped layer 11 on the back side of the wafer 1 to form the detector.
Specifically, before forming the first electrode layer 5, a first electrode conductive material layer (not shown) covering the upper surface of the isolation layer 3 and filling the groove 31 and the first opening 32 is formed, and the first electrode layer material layer is patterned to form the first electrode layer 5.
Specifically, the method for forming the first electrode conductive material layer includes physical vapor deposition, chemical vapor deposition, electroplating, electroless plating, or other suitable methods.
Specifically, as shown in fig. 13, in order to show the schematic cross-sectional structure after the first electrode layer 5 is formed, the material of the first electrode layer 5 includes one of copper, aluminum, nickel, gold, silver, and titanium, and may be other suitable conductive materials.
For example, after the first electrode layer 5 is formed, a passivation layer (not shown) is formed on the upper surface of the first electrode layer 5.
Specifically, the method for forming the passivation layer includes one of chemical vapor deposition, physical vapor deposition, atomic layer deposition and chemical passivation, and may be other suitable methods. In this embodiment, the passivation layer is formed on the upper surfaces of the isolation layer 3 and the first electrode layer 5 by a chemical vapor deposition method, and the passivation layer is patterned to form a second opening (not shown) exposing the first electrode layer 5 in the passivation layer, so as to lead out the first electrode layer 5.
Specifically, the supporting substrate 2 is removed, and the portions of the detector formation region 10 that are separated from the trenches 13 are also removed.
Specifically, the method for removing the support substrate 2 includes chemical mechanical polishing, smart cut, or other suitable methods.
Specifically, as shown in fig. 14, in order to form the cross-sectional structure of the second electrode layer 6, the method for forming the second electrode layer 6 includes physical vapor deposition, chemical vapor deposition, electroplating, electroless plating, or other suitable methods.
Specifically, the material of the second electrode layer 6 includes one of copper, aluminum, nickel, gold, silver, and titanium, and may be other suitable conductive materials.
In the manufacturing method of the edge incidence detector of the embodiment, after the body region 12 is formed, the groove 13 penetrating through the isolation layer 3 and the wafer 1 and exposing the support substrate 2 at the bottom is formed at the edge of the detector forming region 10 by using a deep reactive ion etching method, so that the lattice defect of the wafer 1 caused by blade cutting is prevented, then the large leakage current caused by the lattice defect introduced by blade cutting is reduced, the conductive layer 41 is formed on the inner wall of the groove 13, and the conductive type of the conductive layer 41 is the same as the conductive type of the doped layer 11 and the wafer 1, so that the conductive layer, the wafer 1 and the doped layer 11 form good electrical contact, and the leakage current caused by the lattice defect introduced by using the deep reactive ion etching method is further reduced.
Example two
The present embodiment provides an edge incident detector, as shown in fig. 14, which is a schematic cross-sectional structure diagram of the edge incident detector, and includes a semiconductor layer, an isolation layer 3, a first electrode layer 5, a conductive layer 41 and a second electrode layer 6, wherein the semiconductor layer includes a first conductive type doping layer 11 located on a back surface layer of the semiconductor layer and a plurality of second conductive type body regions 12 located on a front surface layer of the semiconductor layer, the isolation layer 3 is located on an upper surface of the semiconductor layer and includes a plurality of grooves 31 arranged at intervals and first openings 32 located at bottoms of the grooves 31 and exposing the body regions 12, the first electrode layer 5 is located on the upper surface of the isolation layer 3 and fills the grooves 31 and is electrically contacted with the body regions 12 through the first openings 32, the conductive layer 41 is located on sidewalls of the semiconductor layer and the isolation layer 3, and is in electrical contact with the doped layer 11, and the second electrode layer 6 is located on the back surface of the semiconductor layer and is in electrical contact with the doped layer 11.
As an example, the first conductivity type includes one of an N-type or a P-type, the second conductivity type includes one of an N-type or a P-type, and the first conductivity type is opposite to the second conductivity type. In this embodiment, the first conductive type is an N-type, and the second conductive type is a P-type.
Specifically, the thickness range of the semiconductor layer is 150 μm to 500 μm, wherein the semiconductor layer is obtained by thinning a detector forming region of the wafer in the first embodiment.
Specifically, the doping layer 11 is used to form an ohmic contact between the semiconductor layer and the second electrode layer 6. A reverse bias voltage is applied between the second electrode layer 6 and the first electrode layer 5 to form a fully depleted layer (with extremely low electron or hole concentration) in the entire semiconductor layer, thereby forming a sensitive region of the detector.
As an example, the upper surface of the first electrode layer 5 is further provided with a passivation layer to improve the corrosion resistance of the first electrode layer 5.
As an example, the width of the first opening 32 is smaller than the width of the bottom of the groove 31.
In particular, the body region 12, the recess 31, the opening 32 and the first electrode layer 5 constitute pixelated readout electrodes, each readout electrode being connected to an independent readout electronics system for reading out the collected X-ray signals.
Specifically, the conductive layer 41 is arranged at the edge of the detector, and the conductive layer 41 can sensitize the edge of the detector, so that the breakdown voltage of the detector is enhanced, and a guard ring for collecting peripheral leakage current is not required to be arranged.
Specifically, since the conductive layer 41 is in electrical contact with the doped layer 11 and the semiconductor layer, that is, the conductive layer 41 can be regarded as an extension of the ohmic contact of the second electrode 6, the second electrode layer 6 on the back surface of the semiconductor layer can be led to the front surface of the semiconductor layer through the conductive layer 41 on the sidewall of the detector, so as to package the detector.
Specifically, the first electrode layer 5 is used to electrically connect a first electrode of the detector, and the second electrode layer 6 is used to electrically connect a second electrode of the detector.
The edge incidence detector of this embodiment omits by the side wall of the detector set up with semiconductor layer and doped layer 11 electric contact conducting layer 41 set up a plurality of unsettled guard rings at the edge of detector, has reduced the area in detector dead zone, has increased the fill factor in sensitive zone, has promoted the collection efficiency of X ray, has strengthened the breakdown voltage of detector, just conducting layer 41 is the extension of second electrode layer 6, can pass through conducting layer 41 will second electrode 6 leads to the front of semiconductor layer, so that the encapsulation of detector.
In summary, the edge incident detector and the manufacturing method thereof of the invention form the groove on the edge of the detector wafer by using the deep reactive ion etching method, thereby avoiding excessive lattice damage on the edge of the wafer caused by cutting with the blade, further avoiding increase of leakage current caused by excessive lattice damage, forming the conductive layer in electrical contact with the wafer and the doping layer on the side wall of the groove, reducing the leakage current caused by defects caused by etching, enhancing the breakdown voltage of the detector, omitting introducing a large protection ring for preventing leakage current from flowing through the edge of the detector, reducing the area of a dead zone, improving the filling factor of a sensitive zone of the detector, further reducing the area of a dead zone when the detector is spliced, and improving the collection efficiency of X-rays. Meanwhile, the conducting layer on the side wall of the detector is in electrical contact with the wafer and the doping layer, the conducting layer is an extension of ohmic contact of the second electrode layer, and the second electrode of the detector can be led to the front side of the detector through the conducting layer, so that the detector can be conveniently packaged. Therefore, the present invention effectively overcomes various disadvantages of the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (14)
1. A method of making an edge-incident detector, comprising the steps of:
providing a first conductive type detector wafer, and forming a first conductive type doping layer on the back surface of the wafer, wherein the wafer comprises at least one detector forming area;
providing a supporting substrate, bonding the wafer to the bearing substrate, enabling the back surface of the wafer to face the bearing substrate, and thinning the wafer from the front surface of the wafer to a preset thickness;
forming an isolation layer on the front surface of the wafer, forming a plurality of grooves arranged at intervals in the isolation layer, and forming a second conductive type body region in the wafer through the grooves;
forming a groove penetrating through the isolation layer and the wafer on the edge of the detector forming area, wherein the supporting substrate is exposed at the bottom of the groove, a first conductive type conducting layer is formed on the side wall of the groove, and the conducting layer is in electric contact with the doping layer;
forming a first opening at the bottom of the groove to expose the body region;
and forming a first electrode layer which is electrically contacted with the body region through the first opening, removing the bearing substrate, and forming a second electrode layer which is electrically contacted with the doped layer on the back surface of the wafer to form the detector.
2. The method of fabricating an edge incidence detector according to claim 1, wherein: and after thinning, the thickness range of the wafer is 150-500 μm.
3. The method of fabricating an edge incidence detector according to claim 1, wherein: the thickness range of the isolating layer is
4. The method of fabricating an edge incidence detector according to claim 1, wherein: the distance range of the bottom of the groove to the front surface of the wafer is
5. The method of fabricating an edge incidence detector according to claim 1, wherein: the step of annealing the activated impurities is also included after the body region is formed.
6. The method of fabricating an edge incidence detector according to claim 1, wherein forming the trench further comprises the steps of:
forming a hard mask layer covering the isolation layer and filling the groove on the upper surface of the isolation layer, and patterning the hard mask layer;
and etching the isolation layer and the wafer based on the hard mask layer to form the groove which penetrates through the isolation layer and the wafer and exposes the support substrate from the bottom, and removing the hard mask layer.
7. The method of fabricating an edge incidence detector according to claim 1, wherein: the width range of the groove is 15-25 mu m.
8. The method of fabricating an edge incidence detector according to claim 1, wherein: the method of forming the trench includes deep reactive ion etching.
9. The method of claim 1, wherein forming the conductive layer further comprises:
forming a conductive material layer on the inner wall of the groove, the upper surface of the isolation layer and the groove;
and removing the conductive material layer on the upper surface of the isolation layer and in the groove to form the conductive layer on the inner wall of the groove.
10. The method of fabricating an edge incidence detector according to claim 1, wherein: and forming a passivation layer on the upper surface of the first electrode layer after the first electrode layer is formed.
11. An edge incident detector, comprising:
the semiconductor layer comprises a first conductive type doping layer positioned on the surface layer of the back surface of the semiconductor layer and a plurality of second conductive type body regions positioned on the surface layer of the front surface of the semiconductor layer;
the isolation layer is positioned on the upper surface of the semiconductor layer and comprises a plurality of grooves arranged at intervals and first openings which are positioned at the bottoms of the grooves and expose the body regions;
the first electrode layer is positioned on the upper surface of the isolation layer, fills the groove and is electrically contacted with the body region through the first opening;
the conducting layer is positioned on the side surfaces of the semiconductor layer and the isolating layer and is electrically contacted with the doping layer;
and the second electrode layer is positioned on the back surface of the semiconductor layer and is electrically contacted with the doped layer.
12. The edge incidence detector of claim 11, wherein: the first conductivity type includes one of an N-type or a P-type, the second conductivity type includes one of an N-type or a P-type, and the first conductivity type is opposite to a conductivity type of the second conductivity type.
13. The edge incidence detector of claim 11, wherein: and the upper surface of the first electrode layer is also provided with a passivation layer.
14. The edge incidence detector of claim 11, wherein: the width of the first opening is smaller than the width of the bottom of the groove.
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| CN114927535A (en) * | 2022-05-20 | 2022-08-19 | 无锡华芯微探科技有限公司 | X-ray detector with double three-dimensional fully-surrounded protection rings and preparation method |
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| CN103972323A (en) * | 2013-01-31 | 2014-08-06 | 同方威视技术股份有限公司 | Radiation detector |
| US20180329082A1 (en) * | 2017-05-15 | 2018-11-15 | Prismatic Sensors Ab | Detector for x-ray imaging |
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| CN114927535A (en) * | 2022-05-20 | 2022-08-19 | 无锡华芯微探科技有限公司 | X-ray detector with double three-dimensional fully-surrounded protection rings and preparation method |
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