CN114446898A - Semiconductor device with a plurality of semiconductor chips - Google Patents

Semiconductor device with a plurality of semiconductor chips Download PDF

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Publication number
CN114446898A
CN114446898A CN202011232472.1A CN202011232472A CN114446898A CN 114446898 A CN114446898 A CN 114446898A CN 202011232472 A CN202011232472 A CN 202011232472A CN 114446898 A CN114446898 A CN 114446898A
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CN
China
Prior art keywords
metal wiring
seal ring
semiconductor device
capacitor
vertical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202011232472.1A
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Chinese (zh)
Inventor
柳圣浩
张欣
杨涛
赵劼
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Institute of Microelectronics of CAS
Zhenxin Beijing Semiconductor Co Ltd
Original Assignee
Institute of Microelectronics of CAS
Zhenxin Beijing Semiconductor Co Ltd
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Publication date
Application filed by Institute of Microelectronics of CAS, Zhenxin Beijing Semiconductor Co Ltd filed Critical Institute of Microelectronics of CAS
Priority to CN202011232472.1A priority Critical patent/CN114446898A/en
Publication of CN114446898A publication Critical patent/CN114446898A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/642—Capacitive arrangements

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The application relates to the technical field of semiconductors, concretely relates to semiconductor device, include: the semiconductor device comprises a semiconductor substrate, wherein a chip area and a cutting line area are formed on the semiconductor substrate; a first seal ring disposed between the chip region and the scribe line region, the first seal ring disposed around the chip region; the vertical natural capacitor is formed in the first sealing ring and integrated in the sealing ring, so that the integration level of the chip is higher, the space is saved, and the miniaturization of the chip is achieved.

Description

Semiconductor device with a plurality of semiconductor chips
Technical Field
The application relates to the technical field of semiconductors, in particular to a semiconductor device.
Background
In an integrated circuit of a semiconductor chip, a seal-ring (seal-ring) has a great influence on the reliability of the chip, and a conventional semiconductor chip includes an integrated circuit region and a seal-ring disposed at the periphery of the semiconductor chip. The integrated circuit region may include various electronic devices, such as passive devices and active devices formed on a substrate. The seal ring is interposed between the Scribe Line (SL) and the integrated circuit Region (circuit Region) of the wafer. When the dicing process is performed along the scribe lines, the seal ring can block unwanted stress spreading and cracking from the scribe lines to the chips caused by the dicing process. Moreover, the chip semiconductor device also has the capability of resisting gas-liquid erosion and can block the permeation and damage of water vapor or other chemical pollution sources.
Generally, in a conventional semiconductor chip, a voltage input terminal Vdd must be connected to an external voltage source Vcc, and a voltage stabilizing capacitor C1 is additionally connected to stabilize the input voltage. Therefore, the conventional semiconductor chip needs to be additionally connected with a voltage stabilizing capacitor in application, which causes additional cost, and increases the complexity of the external circuit of the semiconductor chip, so that the semiconductor chip cannot be miniaturized.
Disclosure of Invention
The present application addresses, at least to some extent, the above-mentioned technical problems in the related art. Therefore, the present application provides a semiconductor device to solve the problem of low device integration.
In order to achieve the above object, a first aspect of the present application provides a semiconductor device comprising:
the semiconductor device comprises a semiconductor substrate, wherein a chip area and a cutting line area are formed on the semiconductor substrate;
a first seal ring disposed between the chip region and the scribe line region
The first sealing ring is arranged around the chip area;
wherein a vertical native capacitor is formed within the first seal ring.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the application. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
FIG. 1 illustrates a cross-sectional view of first and second seal rings in one embodiment of the present application;
FIG. 2 illustrates a top view of the first and second seal rings in one embodiment of the present application.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.
The conventional semiconductor chip needs to be additionally connected with a voltage stabilizing capacitor in application, which causes extra cost, and simultaneously increases the complexity of an external circuit of the semiconductor chip, so that the semiconductor chip cannot be miniaturized. In order to solve the above problems, the first seal ring proposed in this embodiment is disposed at the periphery of the chip area and has the functions of a conventional seal ring, such as preventing static electricity from affecting the ic area on the semiconductor chip, and preventing the mechanical cutting tool from damaging the ic area and preventing moisture or other polluting and corrosive factors from entering the ic area. The first sealing ring that this embodiment provided not only provides the function that traditional sealing ring had, and still borrow structural improvement and then form a condenser, and need not external condenser again and can reach the effect of steady voltage, and in addition, the condenser is integrated in the sealing ring for the integrated level of chip is higher, has practiced thrift the space, has reached the miniaturization of chip.
Referring to fig. 1-2, a first aspect of the present application provides a semiconductor device 100, wherein the semiconductor device 100 has a chip region 101, a seal ring region 102 surrounding the chip region 101, and a scribe line region 103 surrounding the seal ring region 102, wherein the chip region 101 provides for the formation of various devices, such as transistors, resistors, and other well-known semiconductor devices, the seal ring region 102 provides for the formation of a seal ring structure thereabove, and the scribe line region 103 provides for performing a scribe process to form individual chips from a semiconductor wafer.
The semiconductor device 100 includes: the semiconductor device includes a semiconductor substrate 10, a first seal ring 11, and a second seal ring 12, wherein the semiconductor substrate 10 has an isolation structure formed therein for isolating and surrounding the first source/drain region 103 and the second source/drain region 104.
It should be noted that, in this embodiment, the first seal ring 11 and the second seal ring 12 are formed on the semiconductor substrate 10 at the same time for example, and it should be noted that, in other embodiments of the present invention, the first seal ring 11 may be separately provided, which is not limited in this embodiment.
An insulating layer is formed on the semiconductor substrate 10 and corresponds to the chip region 101, the seal ring region 102, and the scribe line region 103. The insulating layer may have a single or multi-layer structure as an interlayer dielectric (ILD) layer or an inter-metal dielectric (IMD) layer, and may include an oxide, a nitride, an oxynitride or a combination thereof or may include a low dielectric (low k) material such as fluorosilicate glass (FSG), carbon doped oxide (carbon doped oxide), methyl silicate (MS Q), Hydrogen Silicate (HSQ), or fluorine tetra-ethyl-silicate (FTEOS). The insulating layer may be formed by Chemical Vapor Deposition (CVD), low pressure CVD, plasma enhanced CVD, high density plasma CVD, or other conventional deposition techniques.
With continued reference to fig. 1, a first seal ring 11 is formed on the first source/drain region 103, surrounding the chip region 101, embedded in the insulating layer, and corresponding to the seal ring region 102. The first seal ring 11 may include a plurality of metal wiring layers 111 (e.g., copper layers) disposed one on another and electrically connected to each other (i.e., the metal wiring layers 111 are located at different levels within an insulating layer to separate the metal wiring layers 111 from each other), and a plurality of vertical via connectors (via bars) 112 disposed between the metal wiring layers 111 located at different levels within the insulating layer, and the vertical via connectors 112 may be made of copper (which may also be implemented using other metals) and electrically connected to the respective metal wiring layers 111.
Specifically, the first seal ring 11 may include five metal wiring layers 111, and herein, the metal wiring layers 111 may be defined as M1, M2, M3, M4, M5, from bottom to Top, and M5 may also be referred to as a Top metal wiring layer (Top metal). The M1 is electrically connected to the first source/drain region 103 and the adjacent metal wiring layer 111 through the vertical via connector 112, and the first seal ring 11 can be fabricated during the formation of the wiring layer and the contact portion in the chip region 101, and can be fabricated by using a dual damascene process. In an embodiment, the width of the first seal ring 101 is about 3 microns.
It is worth mentioning that a plurality of Vertical Natural Capacitors (VNCAPs) 200 are formed in the first seal ring 11, and specifically, one Vertical Natural Capacitor (VNCAP)200 is formed in each metal wiring layer of M1, M2, M3 in the first seal ring 11, and the Vertical Natural Capacitors (VNCAPs) 200 formed in M1, M2, M3 are connected in series.
Specifically, three metal wirings are formed in M1, M2 and M3 in the first seal ring 11, and an insulating dielectric layer is filled between adjacent metal wirings, wherein two metal wirings at two sides are electrically connected with M4 and M5 to serve as a cathode plate 20 of the vertical native capacitor 200 for connecting the system low voltage Vss, and one metal wiring in the middle is connected with M4 and M5 in an insulating manner to serve as an anode plate 21 of the vertical native capacitor 200 for connecting an external Pad (Pad).
It should be noted that, in the present embodiment, only a part of the metal wiring layer in the first seal ring 11 is formed into the Vertical Natural Capacitor (VNCAP)200, but of course, one Vertical Natural Capacitor (VNCAP)200 is formed in each of the metal wiring layers M1, M2, M3, and M4 in the first seal ring 11, and the principle is the same as above.
In addition, in this embodiment, only five metal wiring layers are included in the first seal ring 11 for explanation, and the metal wiring layers in the first seal ring 11 may be other 3, 4, 6, 7 layers, and the like, which is not limited herein.
It should be noted that 2 or 4 or even more metal wires may be formed on one or more metal wiring layers 111 in the first seal ring 11, so as to form one or more Vertical Natural Capacitors (VNCAP)200 in each metal wiring layer 111, for example, when one metal wiring layer 111 in the first seal ring 11 includes 2 metal wires, one of the metal wires is electrically connected to another metal wiring layer to serve as a cathode plate 20 of the vertical natural capacitor 200, and the other metal wire is connected to another metal wiring layer in an insulated manner to serve as an anode plate 21 of the vertical natural capacitor 200, at this time, a Vertical Natural Capacitor (VNCAP)200 is formed in the metal wiring layer 111. When one of the metal wiring layers 111 of the first seal ring 11 includes 4 metal wirings, two of the metal wirings are electrically connected to the other metal wiring layer to serve as a pair of cathode plates 20 of the vertical native capacitor 200, and the other two metal wirings are insulated from the other metal wiring layer to serve as another pair of anode plates 21 of the vertical native capacitor 200, 2 vertical native capacitors 200 are formed in the metal wiring layer 111.
It is understood that if at least 2 metal wires are formed in each metal wire layer 111, at least one metal wire is electrically connected to the cathode plate of the vertical native capacitor 200, and at least one metal wire is insulated from the anode plate 21 of the vertical native capacitor 200, so that at least one vertical native capacitor 200 is formed in each metal wire layer 111, and a set of vertical native capacitors 200 connected in series up and down is formed in the first seal ring 11.
The second seal ring structure 12 is formed on the second source/drain region 104, embedded in the insulating layer, corresponding to the seal ring region 102, and disposed around the inside or outside of the first seal ring 11, specifically, in the present embodiment, the second seal ring 12 is disposed around the outside of the first seal ring 11. The second seal ring 12 may include: the stacked plurality of metal wiring layers 111 and the plurality of via connections 112 disposed between the metal wiring layers 111, like the first seal ring 11, the second seal ring 12 may include 5 metal wiring layers 111 stacked, and the metal wiring layers 111 of the second seal ring 12 are flush with the metal wiring layers 111 of the first seal ring 11.
It is worth mentioning that, with reference to fig. 2, the metal wiring layer 111 is comb-shaped.
The first seal ring 11 and the second seal ring 12 can be simultaneously manufactured by the same process. In an embodiment, the width of the first seal ring 11 is equal to the width of the second seal ring 12. For example, the width of the second seal ring 12 is 3 μm. Furthermore, the first seal ring 11 and the second seal ring 12 are separated by a distance of about 2 microns and are separated from the chip region 101 by a distance of about 6 microns.
It should be noted that, the present embodiment is described as performing electrical connection through the vertical via connection component 112, but the present embodiment is not limited thereto, and the electrical connection between adjacent metal wiring layers and between the metal wiring layer and the source/drain region may also be performed through vias, even without using vias.
It should be noted that the second seal ring 12 may also have the same structure as the first seal ring 11, that is, the internal structure of the second seal ring 12 is changed to form a Vertical Natural Capacitor (VNCAP)200 therein.
It should be noted that, in the present embodiment, only 5 metal layers are included in the first seal ring 11 and the second seal ring 12 for illustration, but the application should not be limited thereto, and a person skilled in the art may flexibly select the number of the metal layers as needed.
Compared with the prior art, the vertical natural capacitor is integrated in the first sealing ring 11, so that the integration level of the chip is higher, the space is saved, and the miniaturization of the chip is achieved.
The semiconductor device in the present embodiment may be a volatile memory device such as a DRAM device, an SRAM device, or a nonvolatile memory device such as a Flash device, a PRAM device, an MRAM device, an RRAM device, or the like.
Further, the chip having the above semiconductor device may be used in various electronic apparatuses, and in particular, the electronic apparatuses may be a smart phone, a computer, a tablet computer, a wearable smart device, an artificial smart device, a mobile power supply, and the like.
In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. Further, although the embodiments are described separately above, this does not mean that the measures in the respective embodiments cannot be used advantageously in combination.
The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.

Claims (10)

1. A semiconductor device, comprising:
the semiconductor device comprises a semiconductor substrate, wherein a chip area and a cutting line area are formed on the semiconductor substrate;
a first seal ring disposed between the chip region and the scribe line region, the first seal ring disposed around the chip region;
wherein a vertical native capacitor is formed within the first seal ring.
2. The semiconductor device according to claim 1, wherein the first seal ring includes a plurality of metal wiring layers provided in a stack, wherein the vertical natural capacitor is formed in at least one of the metal wiring layers.
3. The semiconductor device according to claim 2, wherein the vertical natural capacitor is formed in one number in a manner that: the metal wiring layer is composed of two metal wirings, wherein one metal wiring is electrically connected with the other metal wiring layer and is used as one polar plate of the vertical natural capacitor, and the other metal wiring is insulated and connected with the other metal wiring layer and is used as the other polar plate of the vertical natural capacitor.
4. The semiconductor device according to claim 2, wherein the vertical natural capacitor is formed in one number in a manner that: the metal wiring layer is composed of three metal wirings, wherein two metal wirings are electrically connected with other metal wiring layers and used as one electrode plate of the vertical natural capacitor, and the other metal wiring is insulated and connected with other metal wiring layers and used as the other electrode plate of the vertical natural capacitor.
5. The semiconductor device according to claim 2, wherein the number of the vertical natural capacitors is two in a manner that: the metal wiring layer is composed of four metal wirings, two of which are electrically connected to the other metal wiring layer and serve as a pair of plates of the vertical natural capacitor, and the other two of which are insulated from the other metal wiring layer and serve as the other pair of plates of the vertical natural capacitor.
6. The semiconductor device according to any one of claims 2 to 5, wherein the first seal ring includes five metal wiring layers, and the vertical natural capacitor is formed in three consecutive metal wiring layers.
7. The semiconductor device according to any one of claims 3 to 5, wherein the vertical natural capacitor in the first seal ring is electrically connected to another metal wiring layer.
8. The semiconductor device according to claim 7, wherein the electrically connected metal wiring serves as a cathode plate of the vertical native capacitor for connection of a system low voltage, and the insulatively connected metal wiring serves as an anode plate of the vertical native capacitor for connection of an external pad.
9. The semiconductor device according to claim 2, wherein a source/drain region is formed in the semiconductor substrate, wherein the first seal ring is provided over the source/drain region, and wherein the metal wiring layer is electrically connected to the source/drain region.
10. The semiconductor device according to claim 2, further comprising:
a second seal ring disposed around the first seal ring, the second seal ring
The structure comprises a plurality of metal wiring layers which are arranged in a laminated mode and are electrically connected with each other, wherein only the first sealing ring can be independent independently, or the second sealing ring is formed in the same mode after the first sealing ring is formed.
CN202011232472.1A 2020-11-06 2020-11-06 Semiconductor device with a plurality of semiconductor chips Pending CN114446898A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202011232472.1A CN114446898A (en) 2020-11-06 2020-11-06 Semiconductor device with a plurality of semiconductor chips

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202011232472.1A CN114446898A (en) 2020-11-06 2020-11-06 Semiconductor device with a plurality of semiconductor chips

Publications (1)

Publication Number Publication Date
CN114446898A true CN114446898A (en) 2022-05-06

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CN202011232472.1A Pending CN114446898A (en) 2020-11-06 2020-11-06 Semiconductor device with a plurality of semiconductor chips

Country Status (1)

Country Link
CN (1) CN114446898A (en)

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