CN114443527B - PCIe-to-MDIO drive realization method and device based on work queue - Google Patents
PCIe-to-MDIO drive realization method and device based on work queue Download PDFInfo
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Abstract
The invention provides a method and a device for implementing PCIe-to-MDIO drive based on a work queue, belonging to the technical field of switch management, wherein the method comprises the following steps: the MSI interrupt is configured for the CPU in advance; a user starts each MDIO controller in the FPGA, sets each MDIO controller to acquire data in a corresponding physical layer chip through a reading function, and sets MSI interrupt enabling; when the data in all the physical layer chips are read, the FPGA triggers MSI interruption through a PCIe bus; and the CPU responds to the MSI interrupt and reads data in an MDIO controller of the FPGA through a work queue. The invention realizes the drive of the kernel thread accessing the physical layer chip register based on the work queue, the CPU does not need to poll the FPGA state mark completion bit, reduces the CPU utilization rate, supports the concurrent access of multiple physical layer chips, and fully utilizes the advantages of CPU multithreading and the clock-free characteristic of the kernel.
Description
Technical Field
The invention belongs to the technical field of switch management, and particularly relates to a method and a device for implementing PCIe-to-MDIO drive based on a work queue.
Background
The white box switch generally integrates an MDIO bus controller in the switch chip, when the switch chip needs to plug in the physical layer chip to be connected to the front panel port, the MDIO bus is used for managing and configuring the physical layer chip, and after the CPU loads a software development packet of the switch chip, the CPU can use an API (application program interface) related to MDIO driving to access a register in the physical layer chip. However, in the field of data centers, more and more exchange chips without built-in MDIO controllers appear, at this time, a CPU can indirectly access to a physical chip through an FPGA device hung under a PCIe link, FPGA firmware can realize conversion from the PCIe protocol to the MDIO protocol, and corresponding multipath MDIO bus controllers can be instantiated according to the number of physical layer chips which need to be accessed by the exchange chips through the FPGA, so that the read-write performance of the physical layer chips when the traditional exchange chips without built-in MDIO controllers is greatly improved. At this time, the linux kernel driver usually adopts a polling mode to poll the status completion flag bit when reading and writing the physical layer register, and completes the read and write operation of the register when the status completion flag bit is set. In this way, the CPU is connected to the FPGA through the PCIe bus, the switch is externally hung with a plurality of physical layer chips, the FPGA uses firmware to instantiate MDIO bus controllers with the same number as the physical layer chips, and each MDIO controller is connected to the physical layer chips through two links of MDC and MDIO.
The user opens the instantiated MDIO bus controller node through a program, sends a physical layer chip address through a reading function to read information of the physical layer chip, the physical layer chip responds to the reading function to return instantiated MDIO bus controller node data to the instantiated MDIO bus controller node, the instantiated MDIO bus controller is marked in the FGPA through a state marking setting mode to acquire data, and the CPU judges whether an FPGA flag bit is set through the reading function polling and reads the data when the FPGA flag bit is set. The method that the exchange chip has no built-in MDIO bus controller and reads and writes the physical layer chip register through polling has the following defects: the speed of the CPU is far higher than that of the MDIO bus equipment, the CPU can spend a great deal of time waiting for the FPGA state to finish the marking bit, other kernel tasks can not be scheduled to finish, and the waste of CPU resources is caused; when the exchange chip transmits a large amount of data through the MDIO bus and the physical layer chip, the CPU utilization rate is high, so that the CPU which is in an idle state cannot exert the advantage of the clock-free characteristic of the kernel.
This is a deficiency of the prior art, and therefore, it is necessary to provide a method and apparatus for implementing PCIe to MDIO driving based on a work queue.
Disclosure of Invention
Aiming at the defect that the CPU utilization rate of a physical layer chip register is higher in a polling mode when the exchange chip has no built-in MDIO bus controller in the prior art, the invention provides a PCIe-to-MDIO driving realization method and device based on a work queue, so as to solve the technical problems.
In a first aspect, the present invention provides a method for implementing PCIe to MDIO driver based on a work queue, including the following steps:
s1, configuring MSI interruption for a CPU in advance;
s2, a user starts each MDIO controller in the FPGA, sets each MDIO controller to acquire data in a corresponding physical layer chip through a reading function, and sets MSI interrupt enabling;
s3, when the data in all physical layer chips are read, the FPGA triggers MSI interrupt through a PCIe bus;
s4, the CPU responds to MSI interruption, and reads data in an MDIO controller of the FPGA through a work queue.
Further, the specific steps of step S1 are as follows:
s11, configuring MSI interruption for a CPU in advance;
s12, configuring an interrupt inlet and an interrupt outlet for MSI interrupt. The MSI interrupt is an interrupt supported by a PCIe bus, and the FPGA sends the MSI interrupt to the CPU through PCIe.
Further, the specific steps of step S2 are as follows:
s21, a user opens each MDIO controller under the FPGA root directory through an application program, and invokes a file reading function in a kernel mode through an IO controller system;
s22, the file reading function in the kernel mode sends a physical chip address and a register address to be read to a physical layer chip, initializes the completion amount of kernel signals, and enables the reading operation to correspond to MSI interrupt in a mode of setting an interrupt control register. The MDIO controller is realized by the FPGA through firmware instantiation, after the FPGA opens the MDIO controller, a file reading function is called through an IO controller system, a physical chip address to be read and a register address thereof are transmitted, the completion amount of a kernel signal is used for indicating whether data read into the FPGA is read, and an interrupt controller register is used for indicating whether MSI interrupt is enabled or not, and the interrupt of the CPU can be validated under the enabling state.
Further, the specific steps of step S3 are as follows:
s31, returning data to the corresponding MDIO controllers of the FPGA by the chips of each physical layer;
s32, the FPGA judges whether the data in all physical layer chips are read completely;
if yes, go to step S33;
if not, returning to the step S31;
s33, the FPGA sends an MSI interrupt trigger signal to the CPU through the PCIe bus. The physical layer chips are read in parallel and return data in parallel, and normally, the data should be returned simultaneously, and the judgment of the FPGA ensures that the read data is returned without omission.
Further, the specific steps of step S4 are as follows:
s41, the CPU receives an MSI interrupt trigger signal and enters MSI interrupt through an interrupt inlet;
s42, MSI interruption sets the data read by the CPU through the work queue into the lower part of MSI interruption content, and exits the MSI interruption through an MSI interruption outlet;
s43, the kernel thread binding the work queue reads the physical layer chip data acquired by the FPGA through the PCIe bus, and the application program main program is informed of the completion amount of the juxtaposition signal;
s44, after receiving the returned data, the user confirms the result, and the access of the exemplified MDIO controller in the FPGA is finished, so that the drive of converting PCIe into MDIO is realized. MSI interrupt places the reading of the physical layer chip data in the FPGA into a work queue, and the work queue reads the data through the bound kernel thread without waiting for polling by a CPU, so that the CPU utilization rate is reduced; the work queue in the linux is an implementation of interrupting the lower half, the interruption comprises an upper half and a lower half, the functions of the upper half are correspondingly summarized, and the functions of the lower half are processed in a complex process.
In a second aspect, the present invention provides a PCIe to MDIO driver implementation device based on a work queue, including:
the MSI interrupt configuration module is used for configuring MSI interrupt for the CPU in advance;
the MDIO acquires a physical layer chip data module, which is used for a user to start each MDIO controller in the FPGA, setting each MDIO controller to acquire data in a corresponding physical layer chip through a reading function, and setting MSI interrupt enabling;
the MSI interrupt triggering module is used for triggering MSI interrupt by the FPGA through the PCIe bus when the data in all the physical layer chips are read;
and the MSI interrupt response module is used for responding to the MSI interrupt by the CPU and reading data in the MDIO controller of the FPGA through the work queue.
Further, the MSI interrupt configuration module includes:
a configuration unit in MSI, configured to configure MSI interrupt for CPU in advance;
and the interrupt entrance configuration unit is used for configuring an interrupt entrance and an interrupt exit for MSI interrupt. The MSI interrupt is an interrupt supported by a PCIe bus, and the FPGA sends the MSI interrupt to the CPU through PCIe.
Further, the MDIO obtaining physical layer chip data module includes:
the MDIO controller node login unit is used for enabling a user to open each MDIO controller under the FPGA root directory through an application program and calling a file reading function in a kernel mode through an IO controller system;
and the physical layer chip data reading unit is used for transmitting a physical chip address and a register address to be read to the physical layer chip by the kernel state file reading function, initializing the kernel signal completion amount and enabling the reading operation to correspond to MSI interrupt by setting an interrupt control register. The MDIO controller is realized by the FPGA through firmware instantiation, after the FPGA opens the MDIO controller, a file reading function is called through an IO controller system, a physical chip address to be read and a register address thereof are transmitted, the completion amount of a kernel signal is used for indicating whether data read into the FPGA is read, and an interrupt controller register is used for indicating whether MSI interrupt is enabled or not, and the interrupt of the CPU can be validated under the enabling state.
Further, the MSI interrupt trigger module includes:
the physical layer chip return unit is used for returning data to the corresponding MDIO controller of the FPGA by each physical layer chip;
the data reading completion judging unit is used for judging whether the data in all the physical layer chips are completely read by the FPGA;
and the interrupt trigger unit is used for sending an MSI interrupt trigger signal to the CPU by the FPGA through the PCIe bus when all the physical layer chip data are read. The physical layer chips are read in parallel and return data in parallel, and normally, the data should be returned simultaneously, and the judgment of the FPGA ensures that the read data is returned without omission.
Further, the MSI interrupt response module includes:
the interrupt entering unit is used for receiving the MSI interrupt trigger signal by the CPU and entering the MSI interrupt through the interrupt inlet;
the work queue reading task placement unit is used for setting the data in the CPU through the work queue reading MDIO controller as the lower half content of the MSI interrupt by MSI interrupt, and exiting the MSI interrupt through an MSI interrupt outlet;
the work queue starting and reading unit is used for reading the physical layer chip data acquired by the FPGA through the PCIe bus by the kernel thread binding the work queue and notifying the application program main program of the completion amount of the position setting signal;
and the drive realizing unit is used for determining the result after the user receives the returned data, instantiating the end of the access of the MDIO controller in the FPGA, and realizing the drive of converting PCIe into MDIO. MSI interrupt places the reading of physical layer chip data in FPGA into work queue, and work queue reads data through bound kernel thread without waiting for polling by CPU, which reduces CPU utilization rate.
The invention has the beneficial effects that:
according to the method and the device for implementing PCIe-to-MDIO drive based on the work queue, the drive of accessing the physical layer chip register by the kernel thread based on the work queue is implemented in the MSI interrupt mode, the CPU does not need to poll the FPGA state mark completion bit, the CPU utilization rate is reduced, concurrent access of registers in a multi-physical layer chip scene is supported, and the advantages of multithreading of the CPU and clock-free characteristic of the kernel are fully utilized.
In addition, the invention has reliable design principle, simple structure and very wide application prospect.
It can be seen that the present invention has outstanding substantial features and significant advances over the prior art, as well as the benefits of its implementation.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the description of the embodiments or the prior art will be briefly described below, and it will be obvious to those skilled in the art that other drawings can be obtained from these drawings without inventive effort.
Fig. 1 is a schematic flow chart of an embodiment 1 of a PCIe to MDIO driver implementation method based on a work queue of the present invention.
Fig. 2 is a schematic flow chart of an embodiment 2 of a PCIe to MDIO driver implementation method based on a work queue according to the present invention.
Fig. 3 is a schematic diagram of a PCIe to MDIO driver implementation device based on a work queue according to the present invention.
In the figure, a 1-MSI interrupt configuration module; 1.1-configuration units in MSI; 1.2-interrupt gateway configuration unit; 2-MDIO acquires a physical layer chip data module; 2.1-MDIO controller node logging unit; 2.2-physical layer chip data reading unit; a 3-MSI interrupt triggering module; 3.1-physical layer chip return unit; 3.2-a data reading completion judging unit; 3.3-interrupt trigger unit; a 4-MSI interrupt response module; 4.1-interrupt entry unit; 4.2-a work queue read task placement unit; 4.3-the work queue starts the reading unit; 4.4-drive implementation unit.
Detailed Description
In order to make the technical solution of the present invention better understood by those skilled in the art, the technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
MDIO is a short name of Management Data Input/Output, and manages data input and Output.
API, abbreviated as Application Programming Interface, application program interface.
PCIe, an acronym for Peripheral Component Interconnect Express, high-speed serial computer expansion bus standard.
FPGA is a short for Field Programmable Gate Array, field programmable gate array.
The polling mode is a mode of deciding how to provide peripheral equipment service by a CPU, and is also called program-controlled input/output, and is performed by polling.
MSI interrupt is one of three interrupt types supported by PCIe, and the three interrupt types are INtx interrupt, MSI interrupt and MSI-X interrupt respectively. MSI, abbreviated as message signal interrupt, is a PCI device that triggers a CPU interrupt by writing a specific message to a specific address. The specific message refers to a write memory transport layer packet in the PCIe bus, and the specific address is typically stored in an MSI capability structure.
Example 1:
as shown in fig. 1, the invention provides a PCIe to MDIO driver implementation method based on a work queue, including the following steps:
s1, configuring MSI interruption for a CPU in advance;
s2, a user starts each MDIO controller in the FPGA, sets each MDIO controller to acquire data in a corresponding physical layer chip through a reading function, and sets MSI interrupt enabling;
s3, when the data in all physical layer chips are read, the FPGA triggers MSI interrupt through a PCIe bus;
s4, the CPU responds to MSI interruption, and reads data in an MDIO controller of the FPGA through a work queue.
According to the PCIe-to-MDIO driving implementation method based on the work queue, the driving of accessing the physical layer chip register by the kernel thread based on the work queue is realized in an MSI interrupt mode, a CPU does not need to poll an FPGA state marking completion bit, the CPU utilization rate is reduced, concurrent access of registers in a multi-physical layer chip scene is supported, and the advantages of multithreading and clock-free characteristics of the kernel of the CPU are fully utilized.
Example 2:
as shown in fig. 2, the invention provides a PCIe to MDIO driver implementation method based on a work queue, including the following steps:
s1, configuring MSI interruption for a CPU in advance; the method comprises the following specific steps:
s11, configuring MSI interruption for a CPU in advance;
s12, configuring an interrupt inlet and an interrupt outlet for MSI interrupt; MSI is an interrupt supported by a PCIe bus, and the FPGA sends the MSI interrupt to the CPU through PCIe;
s2, a user starts each MDIO controller in the FPGA, sets each MDIO controller to acquire data in a corresponding physical layer chip through a reading function, and sets MSI interrupt enabling; the method comprises the following specific steps:
s21, a user opens each MDIO controller under the FPGA root directory through an application program, and invokes a file reading function in a kernel mode through an IO controller system;
s22, a file reading function in a kernel mode sends a physical chip address and a register address to be read to a physical layer chip, initializes the completion amount of kernel signals, and enables the reading operation to correspond to MSI interrupt in a mode of setting an interrupt control register; the MDIO controller is realized by the FPGA through firmware instantiation, after the FPGA opens the MDIO controller, a file reading function is called through an IO controller system, a physical chip address to be read and a register address thereof are transmitted, the completion amount of a kernel signal is used for indicating whether data read into the FPGA is read away, and an interrupt controller register is used for indicating whether MSI interrupt is enabled or not, and the interrupt of the CPU can only take effect under the enabling state;
s3, when the data in all physical layer chips are read, the FPGA triggers MSI interrupt through a PCIe bus; the method comprises the following specific steps:
s31, returning data to the corresponding MDIO controllers of the FPGA by the chips of each physical layer;
s32, the FPGA judges whether the data in all physical layer chips are read completely;
if yes, go to step S33;
if not, returning to the step S31;
s33, the FPGA sends an MSI interrupt trigger signal to the CPU through the PCIe bus; the physical layer chips are read in parallel and return data in parallel, and normally return data simultaneously, and the judgment of the FPGA ensures that the read data are returned without omission;
s4, the CPU responds to MSI interruption, and reads data in an MDIO controller of the FPGA through a work queue; the method comprises the following specific steps:
s41, the CPU receives an MSI interrupt trigger signal and enters MSI interrupt through an interrupt inlet;
s42, MSI interruption sets the data read by the CPU through the work queue into the lower part of MSI interruption content, and exits the MSI interruption through an MSI interruption outlet;
s43, the kernel thread binding the work queue reads the physical layer chip data acquired by the FPGA through the PCIe bus, and the application program main program is informed of the completion amount of the juxtaposition signal;
s44, after receiving the returned data, the user confirms the result, and the access of the exemplified MDIO controller in the FPGA is finished, so that the drive of converting PCIe into MDIO is realized; MSI interrupt places the reading of physical layer chip data in FPGA into work queue, and work queue reads data through bound kernel thread without waiting for polling by CPU, which reduces CPU utilization rate.
In the above embodiment 2, after the MSI interrupt is preconfigured, the user opens the/dev/MDIO of each MDIO controller under the root directory of the FPGA through the application program, and calls the read function to the file_operations of the kernel mode through the IO controller system;
the kernel mode mdio_read function sends a physical layer chip address and a register address to be read to the physical layer chip, initializes the kernel signal completion amount and enables an interrupt control register of a read operation;
the physical layer chip returns data to the MDIO controller, and the FPGA triggers MSI interrupt to the CPU;
the CPU puts the task into a work queue at the lower half part of the registered MSI interrupt service routine and exits the interrupt service routine;
the kernel thread binding the work queue finishes the reading process of the physical layer chip register result, and the completion amount of the bit signal informs the main program of the application program;
after receiving the drive return data, the user confirms the result and the MDIO controller access is finished.
Example 3:
as shown in fig. 3, the present invention provides a PCIe to MDIO driver implementation device based on a work queue, including:
the MSI interrupt configuration module 1 is used for configuring MSI interrupt for the CPU in advance;
the MDIO acquires a physical layer chip data module 2, which is used for a user to start each MDIO controller in the FPGA, setting each MDIO controller to acquire data in a corresponding physical layer chip through a reading function, and setting MSI interrupt enabling;
the MSI interrupt triggering module 3 is used for triggering MSI interrupt by the FPGA through a PCIe bus when the data in all the physical layer chips are read;
and the MSI interrupt response module 4 is used for responding to the MSI interrupt by the CPU and reading data in the MDIO controller of the FPGA through the work queue.
According to the PCIe-to-MDIO drive realization device based on the work queue, through an MSI interrupt mode, the drive of accessing the physical layer chip register by the kernel thread based on the work queue is realized, the CPU does not need to poll the FPGA state mark completion bit, the CPU utilization rate is reduced, the concurrent access of the register under the multi-physical layer chip scene is supported, and the advantages of multithreading of the CPU and no clock characteristic of the kernel are fully utilized.
Example 4:
as shown in fig. 3, the present invention provides a PCIe to MDIO driver implementation device based on a work queue, including:
the MSI interrupt configuration module 1 is used for configuring MSI interrupt for the CPU in advance; the MSI interrupt configuration module 1 includes:
a configuration unit 1.1 in the MSI, configured to configure an MSI interrupt for the CPU in advance;
an interrupt gateway configuration unit 1.2 for configuring an interrupt entry and an interrupt exit for MSI interrupt; MSI is an interrupt supported by a PCIe bus, and the FPGA sends the MSI interrupt to the CPU through PCIe;
the MDIO acquires a physical layer chip data module 2, which is used for a user to start each MDIO controller in the FPGA, setting each MDIO controller to acquire data in a corresponding physical layer chip through a reading function, and setting MSI interrupt enabling; the MDIO acquisition physical layer chip data module 2 includes:
the MDIO controller node login unit 2.1 is used for opening each MDIO controller under the FPGA root directory by a user through an application program and calling a file reading function in a kernel mode through an IO controller system;
the physical layer chip data reading unit 2.2 sends a physical chip address and a register address to be read to the physical layer chip by a file reading function in a kernel mode, initializes the completion amount of kernel signals and enables the MSI interrupt corresponding to the reading operation in a mode of setting an interrupt control register; the MDIO controller is realized by the FPGA through firmware instantiation, after the FPGA opens the MDIO controller, a file reading function is called through an IO controller system, a physical chip address to be read and a register address thereof are transmitted, the completion amount of a kernel signal is used for indicating whether data read into the FPGA is read away, and an interrupt controller register is used for indicating whether MSI interrupt is enabled or not, and the interrupt of the CPU can only take effect under the enabling state;
the MSI interrupt triggering module 3 is used for triggering MSI interrupt by the FPGA through a PCIe bus when the data in all the physical layer chips are read; the MSI interrupt trigger module 3 includes:
the physical layer chip return unit 3.1 is used for returning data to the corresponding MDIO controller of the FPGA by each physical layer chip;
a data reading completion judging unit 3.2, configured to judge whether the data in all the physical layer chips are completely read by the FPGA;
the interrupt trigger unit 3.3 is used for sending an MSI interrupt trigger signal to the CPU by the FPGA through the PCIe bus when all the physical layer chip data are read; the physical layer chips are read in parallel and return data in parallel, and normally return data simultaneously, and the judgment of the FPGA ensures that the read data are returned without omission;
the MSI interrupt response module 4 is used for responding to MSI interrupt by the CPU and reading data in an MDIO controller of the FPGA through the work queue; the MSI interrupt response module 4 includes:
an interrupt entry unit 4.1, configured to receive an MSI interrupt trigger signal by the CPU, and enter an MSI interrupt through an interrupt entry;
the work queue reading task placement unit 4.2 is used for setting the data in the CPU reading MDIO controller through the work queue as the lower part of the MSI interrupt content by MSI interrupt, and exiting the MSI interrupt through an MSI interrupt outlet;
the work queue starting and reading unit 4.3 is used for reading the physical layer chip data acquired by the FPGA through the PCIe bus by the kernel thread binding the work queue and notifying the application program main program of the completion amount of the juxtaposition signal;
the drive realizing unit 4.4 is used for determining the result after the user receives the returned data, instantiating the end of the access of the MDIO controller in the FPGA, and realizing the drive of converting PCIe into MDIO; MSI interrupt places the reading of physical layer chip data in FPGA into work queue, and work queue reads data through bound kernel thread without waiting for polling by CPU, which reduces CPU utilization rate.
Although the present invention has been described in detail by way of preferred embodiments with reference to the accompanying drawings, the present invention is not limited thereto. Various equivalent modifications and substitutions may be made in the embodiments of the present invention by those skilled in the art without departing from the spirit and scope of the present invention, and it is intended that all such modifications and substitutions be within the scope of the present invention/be within the scope of the present invention as defined by the appended claims. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (8)
1. A PCIe-to-MDIO drive implementation method based on a work queue is characterized by comprising the following steps:
s1, configuring MSI interruption for a CPU in advance;
s2, a user starts each MDIO controller in the FPGA, sets each MDIO controller to acquire data in a corresponding physical layer chip through a reading function, and sets MSI interrupt enabling;
s3, when the data in all physical layer chips are read, the FPGA triggers MSI interrupt through a PCIe bus;
s4, the CPU responds to MSI interruption, and reads data in an MDIO controller of the FPGA through a work queue; the specific steps of the step S4 are as follows:
s41, the CPU receives an MSI interrupt trigger signal and enters MSI interrupt through an interrupt inlet;
s42, MSI interruption sets the data read by the CPU through the work queue into the lower part of MSI interruption content, and exits the MSI interruption through an MSI interruption outlet;
s43, the kernel thread binding the work queue reads the physical layer chip data acquired by the FPGA through the PCIe bus, and the application program main program is informed of the completion amount of the juxtaposition signal;
s44, after receiving the returned data, the user confirms the result, and the access of the exemplified MDIO controller in the FPGA is finished, so that the drive of converting PCIe into MDIO is realized.
2. The method for implementing PCIe to MDIO driver based on work queue according to claim 1, wherein step S1 specifically comprises the following steps:
s11, configuring MSI interruption for a CPU in advance;
s12, configuring an interrupt inlet and an interrupt outlet for MSI interrupt.
3. The method for implementing PCIe to MDIO driver based on work queue according to claim 2, wherein step S2 specifically comprises the following steps:
s21, a user opens each MDIO controller under the FPGA root directory through an application program, and invokes a file reading function in a kernel mode through an IO controller system;
s22, the file reading function in the kernel mode sends a physical chip address and a register address to be read to a physical layer chip, initializes the completion amount of kernel signals, and enables the reading operation to correspond to MSI interrupt in a mode of setting an interrupt control register.
4. The method for implementing PCIe to MDIO driver based on work queue according to claim 1, wherein step S3 comprises the specific steps of:
s31, returning data to the corresponding MDIO controllers of the FPGA by the chips of each physical layer;
s32, the FPGA judges whether the data in all physical layer chips are read completely;
if yes, go to step S33;
if not, returning to the step S31;
s33, the FPGA sends an MSI interrupt trigger signal to the CPU through the PCIe bus.
5. PCIe-to-MDIO driver realization device based on work queue, which is characterized by comprising:
an MSI interrupt configuration module (1) for configuring MSI interrupt for CPU in advance;
the MDIO acquires a physical layer chip data module (2) which is used for starting all MDIO controllers in the FPGA by a user, setting all the MDIO controllers to acquire data in a corresponding physical layer chip through a reading function, and setting MSI interrupt enabling;
the MSI interrupt triggering module (3) is used for triggering MSI interrupt by the FPGA through the PCIe bus when the data in all the physical layer chips are read;
the MSI interrupt response module (4) is used for responding to MSI interrupt by the CPU and reading data in an MDIO controller of the FPGA through the work queue; the MSI interrupt response module (4) includes:
an interrupt entry unit (4.1) for receiving the MSI interrupt trigger signal by the CPU and entering the MSI interrupt through the interrupt entry;
the work queue reading task placing unit (4.2) is used for setting the data in the CPU reading MDIO controller through the work queue as the lower part of the MSI interrupt content by MSI interrupt, and exiting the MSI interrupt through an MSI interrupt outlet;
a work queue starting and reading unit (4.3) for reading the physical layer chip data acquired by the FPGA by the kernel thread binding the work queue through a PCIe bus and notifying an application program main program of the completion amount of the juxtaposition signal;
and the drive realizing unit (4.4) is used for confirming the result after the user receives the returned data, instantiating the end of the access of the MDIO controller in the FPGA, and realizing the drive of converting PCIe into MDIO.
6. The work queue based PCIe to MDIO driver implementation device of claim 5 wherein the MSI interrupt configuration module (1) comprises:
a configuration unit (1.1) in MSI for configuring MSI interrupt for CPU in advance;
an interrupt entry configuration unit (1.2) for configuring an interrupt entry and an interrupt exit for MSI interrupts.
7. The PCIe to MDIO driver implementation device based on work queue of claim 6 wherein the MDIO get physical layer chip data module (2) comprises:
the MDIO controller node login unit (2.1) is used for opening each MDIO controller under the FPGA root directory through an application program by a user, and calling a file reading function in a kernel mode through an IO controller system;
and the physical layer chip data reading unit (2.2) is used for transmitting the physical chip address and the register address to be read to the physical layer chip by the file reading function in the kernel state, initializing the completion amount of the kernel signal and enabling the reading operation to correspond to MSI interrupt in a mode of setting an interrupt control register.
8. The PCIe to MDIO driver implementation device based on work queue of claim 7 wherein the MSI interrupt trigger module (3) comprises:
the physical layer chip return unit (3.1) is used for returning data to the corresponding MDIO controller of the FPGA by each physical layer chip;
a data reading completion judging unit (3.2) for the FPGA to judge whether the data in all the physical layer chips are completely read;
and the interrupt triggering unit (3.3) is used for sending an MSI interrupt triggering signal to the CPU by the FPGA through the PCIe bus when all the physical layer chip data are read.
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| CN105117319A (en) * | 2015-08-25 | 2015-12-02 | 烽火通信科技股份有限公司 | Method for realizing real-time monitoring of multi-channel MDIO (Management Data Input Output) devices based on FPGA |
| CN108763121A (en) * | 2018-04-28 | 2018-11-06 | 西安电子科技大学 | The interrupt operation method of TTE end system adapter PCIe controllers |
| WO2021185135A1 (en) * | 2020-03-17 | 2021-09-23 | 阿里巴巴集团控股有限公司 | Message signaled interrupt implementation method, apparatus and device |
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| CN105117319A (en) * | 2015-08-25 | 2015-12-02 | 烽火通信科技股份有限公司 | Method for realizing real-time monitoring of multi-channel MDIO (Management Data Input Output) devices based on FPGA |
| CN108763121A (en) * | 2018-04-28 | 2018-11-06 | 西安电子科技大学 | The interrupt operation method of TTE end system adapter PCIe controllers |
| WO2021185135A1 (en) * | 2020-03-17 | 2021-09-23 | 阿里巴巴集团控股有限公司 | Message signaled interrupt implementation method, apparatus and device |
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