CN114443521A - Sum device for improving transmission rate between CPU and DDR5DIMM - Google Patents
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Abstract
The invention provides a method, a system, equipment and a storage medium for improving the transmission rate between a CPU and a DDR5DIMM, wherein the method comprises the following steps: adding a cache on each of two channels of a DDR5DIMM, wherein one end of the cache is connected with a data bus of a CPU dual in-line memory module channel, and the other end of the cache is respectively connected with a Rank0 and a Rank1 of the DDR5 DIMM; in response to the CPU sending data to the DDR5DIMM, sending a chip select signal to a register clock driver in the DDR5DIMM to select a corresponding channel; transmitting data to the cache by using a frequency multiplication technology in a data bus of the CPU dual in-line memory module channel; and respectively transmitting the data to Rank0 and Rank1 of DDR5DIMM through the cache. According to the invention, the two channels of the DDR5DIMM are respectively added with the cache, so that the problems of low data transmission rate of the DDR5DIMM and limitation on further increasing of the data transmission rate of the CPU are effectively solved.
Description
Technical Field
The present invention relates to the field of data transmission, and more particularly, to a method, system, device and storage medium for increasing the transmission rate between a CPU and a DDR5 DIMM.
Background
The server is a high-end computer and has strong data operation, analysis and storage capabilities. With the continuous development of cloud computing, big data, metauniverse and other services, the potential of the server needs to be further mined, and the operation rate of the server is improved. The CPU is used as the core of the server, and the operation rate can be further improved by utilizing advanced manufacturing process, frequency doubling, over-frequency and other technologies. The CPU is closely communicated with a DDR (Double Data Rate SDRAM) DIMM (Dual Inline Memory Module), and since the storage Rate of the DDR granule has not been greatly broken through, the DDR granule cannot match with the strong operation Rate of the CPU, and gradually becomes a bottleneck for increasing the overall Rate. Although the advanced DDR5DIMM (the fifth generation double data rate synchronous dynamic random access memory dual in-line memory module) is developed and marketed, the data rate is 3200-6400 MT/s, and the maximum computing efficiency of the CPU cannot be matched and exerted.
FIG. 1 is a prior art communication scheme between a CPU and a DDR5 DIMM. As shown in fig. 1, a complete DDR5DIMM is divided into two separate channels a and B, each having 2 ranks, with the Data Bus of each Channel being 40 bits. For x 4-bit wide Memory granules, 10 DRAMs (Dynamic Random Access memories) are required for each Rank, so 40 DRAMs are required on one DDR5 DIMM. In existing designs, the data bus of the CPU DIMM Channel is directly connected to the data buses of Rank0 and Rank1 of the DDR5DIMM Channel. The CPU can increase the rate of data communication through a frequency doubling technique. However, since the data bus transfer rate of DDR5 DIMMs is limited by the memory speed of DDR5DIMM granularity, the CPU can only reduce the transfer rate and match the rate of DDR5 DIMMs. Such a design obviously does not fully utilize the maximum communication rate of the CPU.
Disclosure of Invention
In view of this, an object of the embodiments of the present invention is to provide a method, a system, a computer device, and a computer-readable storage medium for increasing a transmission rate between a CPU and a DDR5DIMM, in which a cache is added to each of two channels of a DDR5DIMM, and a frequency doubling technique is used to increase a data communication rate, so as to effectively solve the problems of low data transmission rate of the DDR5DIMM and limitation of the CPU to further increase the data transmission rate.
In view of the above, an aspect of the embodiments of the present invention provides a method for increasing the transmission rate between a CPU and a DDR5DIMM, including the following steps: adding a cache on each of two channels of a DDR5DIMM, wherein one end of the cache is connected with a data bus of a CPU dual in-line memory module channel, and the other end of the cache is respectively connected with a Rank0 and a Rank1 of the DDR5 DIMM; in response to the CPU sending data to the DDR5DIMM, sending a chip select signal to a register clock driver in the DDR5DIMM to select a corresponding channel; transmitting data to the cache by using a frequency multiplication technology in a data bus of the CPU dual in-line memory module channel; and respectively transmitting the data to Rank0 and Rank1 of DDR5DIMM through the cache.
In some embodiments, the method further comprises: in response to the CPU reading the second data in the DDR5DIMM, the Rank0 and the Rank1 of the DDR5DIMM respectively transmit the second data to the cache and send the second data to the data bus of the CPU dual in-line memory module channel through the cache.
In some embodiments, the data bus that sends the second data to the CPU dual in-line memory module channel through the cache comprises: and transmitting the second data to a data bus of the CPU dual in-line memory module channel by using a frequency multiplication technology in the cache.
In some embodiments, the Rank0 and Rank1 respectively transmitting the data to the DDR5 DIMMs through the cache comprises: and sending an operation command code, an address code and a parity check code to the register clock driver through a data bus of the CPU dual in-line memory module channel, and controlling the DRAM particles of the selected channel.
In another aspect of the embodiments of the present invention, a system for increasing a transmission rate between a CPU and a DDR5DIMM is provided, including: the device comprises a setting module, a memory module and a data bus module, wherein the setting module is configured to add a cache on each of two channels of a DDR5DIMM, one end of the cache is connected with the data bus of the CPU dual in-line memory module channel, and the other end of the cache is respectively connected with a Rank0 and a Rank1 of the DDR5 DIMM; a selection module configured to send a chip select signal to a register clock driver in the DDR5DIMM to select a corresponding channel in response to the CPU sending data to the DDR5 DIMM; the first transmission module is configured to transmit data to the cache by using a frequency multiplication technology in a data bus of the CPU dual in-line memory module channel; and the second transmission module is used for transmitting the data to Rank0 and Rank1 of DDR5DIMM respectively through the cache.
In some embodiments, the system further comprises a reading module configured to: in response to the CPU reading the second data in the DDR5DIMM, the Rank0 and the Rank1 of the DDR5DIMM respectively transmit the second data to the cache and send the second data to the data bus of the CPU dual in-line memory module channel through the cache.
In some embodiments, the reading module is further configured to: and transmitting the second data to a data bus of the CPU dual in-line memory module channel by using a frequency multiplication technology in the cache.
In some embodiments, the second transmission module is further configured to: and sending an operation command code, an address code and a parity check code to the register clock driver through a data bus of the CPU dual in-line memory module channel, and controlling the DRAM particles of the selected channel.
In another aspect of the embodiments of the present invention, there is also provided a computer device, including: at least one processor; and a memory storing computer instructions executable on the processor, the instructions when executed by the processor implementing the steps of the method as above.
In a further aspect of the embodiments of the present invention, a computer-readable storage medium is also provided, in which a computer program for implementing the above method steps is stored when the computer program is executed by a processor.
The invention has the following beneficial technical effects: by respectively adding a cache on two channels of the DDR5DIMM and improving the data communication speed through a frequency doubling technology, the problems that the data transmission speed of the DDR5DIMM is low and the CPU is limited to further improve the data transmission speed are effectively solved.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
FIG. 1 is a schematic diagram of prior art communication between a CPU and a DDR5 DIMM;
FIG. 2 is a schematic diagram of an embodiment of a method for increasing the transfer rate between a CPU and a DDR5DIMM according to the invention;
FIG. 3 is a schematic diagram of the communication between a CPU and a DDR5DIMM in an embodiment of the present invention;
FIG. 4 is a schematic diagram of an embodiment of a system for increasing the transfer rate between a CPU and a DDR5DIMM in accordance with the present invention;
FIG. 5 is a schematic diagram of a hardware configuration of an embodiment of a computer device for increasing the transmission rate between a CPU and a DDR5DIMM according to the present invention;
FIG. 6 is a schematic diagram of an embodiment of a computer storage medium for increasing the transfer rate between a CPU and a DDR5 DIMM.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.
In a first aspect of the embodiments of the present invention, an embodiment of a method for increasing a transmission rate between a CPU and a DDR5DIMM is provided. FIG. 2 is a schematic diagram of an embodiment of a method for increasing the transfer rate between a CPU and a DDR5 DIMM. As shown in fig. 2, the embodiment of the present invention includes the following steps:
s1, adding a cache on each of two channels of DDR5DIMM, wherein one end of the cache is connected with a data bus of a CPU dual in-line memory module channel, and the other end of the cache is respectively connected with Rank0 and Rank1 of DDR5 DIMM;
s2, responding to the data sent by the CPU to the DDR5DIMM, sending a chip selection signal to a register clock driver in the DDR5DIMM to select a corresponding channel;
s3, transmitting data to the cache by using a frequency multiplication technology in a data bus of the CPU dual in-line memory module channel; and
and S4, respectively transmitting the data to the Rank0 and the Rank1 of the DDR5DIMM through the cache.
FIG. 3 is a schematic diagram of the communication between a CPU and a DDR5DIMM according to an embodiment of the present invention, which is described in conjunction with FIG. 3.
And adding a cache on each of two channels of the DDR5DIMM, wherein one end of the cache is connected with a data bus of the CPU dual in-line memory module channel, and the other end of the cache is respectively connected with a Rank0 and a Rank1 of the DDR5 DIMM. One Buffer is added to each of the two channels of the DDR5 DIMM. One end of the Buffer is connected with a data bus of a CPU DIMM Channel, and the other end of the Buffer is respectively connected with a Rank0 and a Rank1 of a DDR5 DIMM.
In response to the CPU sending data to the DDR5DIMM, a chip select signal is sent to a register clock driver in the DDR5DIMM to select the corresponding channel. The CPU sends a chip select signal to a Register Clock Driver in the DDR5DIMM through CABus for selecting Channel A or Channel B.
And transmitting data to the cache by using a frequency multiplication technology in a data bus of the CPU dual in-line memory module channel. The data bus of the CPU dual in-line memory module channel transmits data by using a frequency doubling technology, namely marked as 'x 2 Speed' in figure 3; DDR5 DIMMs still use "x 1 Speed" to transfer data.
And respectively transmitting the data to Rank0 and Rank1 of DDR5DIMM through the cache.
In some embodiments, the Rank0 and Rank1 respectively transmitting the data to the DDR5 DIMMs through the cache comprises: and sending an operation command code, an address code and a parity check code to the register clock driver through a data bus of the CPU dual in-line memory module channel, and controlling the DRAM particles of the selected channel. The CPU sends instructions such as an operation command code, an address code, a parity code and the like, a Register Clock Driver (Register Clock Driver) controls the selected Channel, and data communication is realized with the CPU through a Buffer. When the CPU sends data to DDR5DIMM at "x 2 Speed", Buffer receives and buffers the data and allocates it to Rank0 and Rank1 to store the data
In some embodiments, the method further comprises: in response to the CPU reading the second data in the DDR5DIMM, the Rank0 and the Rank1 of the DDR5DIMM respectively transmit the second data to the cache and send the second data to the data bus of the CPU dual in-line memory module channel through the cache.
In some embodiments, the data bus that sends the second data to the CPU dual in-line memory module channel through the cache comprises: and transmitting the second data to a data bus of the CPU dual in-line memory module channel by using a frequency multiplication technology in the cache. When the CPU reads data in DDR5DIMM, Rank0 and Rank1 send data to Buffer at "x 1 Speed" simultaneously, and Buffer sends data to CPU at "x 2 Speed".
For example, the following steps are carried out: if the CPU needs to transfer 2 sets of data with the DDR5 DIMMs.
(1) The prior technical scheme is used: assuming that 1 second is needed for gating one Channel of DDR5DIMM, 1 second is needed for gating Rank0, 1 second is needed for CPU to transmit the 1 st group of data between x1 Speed and Rank0, 1 second is needed for gating Rank1, and 1 second is needed for CPU to transmit the 2 nd group of data between x1 Speed and Rank1, the overall calculation is as follows: a time of 5s is required.
(2) The technical scheme of the invention is as follows: assuming that 1 second is needed for gating one Channel of the DDR5DIMM, only 1 second is needed for the CPU to transmit 2 sets of data between "x 2 Speed" and Buffer, and only 1 second is needed for the Buffer to transmit 2 sets of data to Rank0 and Rank1 (the transmission rate is "x 1 Speed") simultaneously and respectively, and the overall calculation is performed: a time of 3s is required.
The comparison shows that: the embodiment of the invention can shorten the data transmission time of 2 seconds, thereby further improving the data transmission speed between the CPU and the DDR5 DIMM.
It should be particularly noted that the steps in the above-mentioned embodiments of the method for increasing the transmission rate between the CPU and the DDR5DIMM may be interleaved, replaced, added or deleted, so that these reasonable permutations and combinations of the above-mentioned method for increasing the transmission rate between the CPU and the DDR5DIMM shall also fall within the protection scope of the present invention, and shall not limit the protection scope of the present invention to the embodiments.
In view of the above, according to a second aspect of the present invention, there is provided a system for increasing the transmission rate between a CPU and a DDR5 DIMM. As shown in fig. 4, the system 200 includes the following modules: the device comprises a setting module, a memory module and a data bus module, wherein the setting module is configured to add a cache on each of two channels of a DDR5DIMM, one end of the cache is connected with the data bus of the CPU dual in-line memory module channel, and the other end of the cache is respectively connected with a Rank0 and a Rank1 of the DDR5 DIMM; a selection module configured to send a chip select signal to a register clock driver in the DDR5DIMM to select a corresponding channel in response to the CPU sending data to the DDR5 DIMM; the first transmission module is configured to transmit data to the cache by using a frequency multiplication technology in a data bus of the CPU dual in-line memory module channel; and the second transmission module is used for transmitting the data to Rank0 and Rank1 of DDR5DIMM respectively through the cache.
In some embodiments, the system further comprises a reading module configured to: in response to the CPU reading the second data in the DDR5DIMM, the Rank0 and the Rank1 of the DDR5DIMM respectively transmit the second data to the cache and send the second data to the data bus of the CPU dual in-line memory module channel through the cache.
In some embodiments, the reading module is further configured to: and transmitting the second data to a data bus of the CPU dual in-line memory module channel by using a frequency multiplication technology in the cache.
In some embodiments, the second transmission module is further configured to: and sending an operation command code, an address code and a parity check code to the register clock driver through a data bus of the CPU dual in-line memory module channel, and controlling the DRAM particles of the selected channel.
In view of the above object, a third aspect of the embodiments of the present invention provides a computer device, including: at least one processor; and a memory storing computer instructions executable on the processor, the instructions being executable by the processor to perform the steps of: s1, adding a cache on each of two channels of DDR5DIMM, wherein one end of the cache is connected with a data bus of a CPU dual in-line memory module channel, and the other end of the cache is respectively connected with Rank0 and Rank1 of DDR5 DIMM; s2, responding to the data sent by the CPU to the DDR5DIMM, sending a chip selection signal to a register clock driver in the DDR5DIMM to select a corresponding channel; s3, transmitting data to the cache by using a frequency multiplication technology in a data bus of the CPU dual in-line memory module channel; and S4, respectively transmitting the data to the Rank0 and the Rank1 of the DDR5DIMM through the buffer.
In some embodiments, the steps further comprise: in response to the CPU reading the second data in the DDR5DIMM, the Rank0 and the Rank1 of the DDR5DIMM respectively transmit the second data to the cache and send the second data to the data bus of the CPU dual in-line memory module channel through the cache.
In some embodiments, the data bus that sends the second data to the CPU dual in-line memory module channel through the cache comprises: and transmitting the second data to a data bus of the CPU dual in-line memory module channel by using a frequency multiplication technology in the cache.
In some embodiments, the Rank0 and Rank1 respectively transmitting the data to the DDR5 DIMMs through the cache comprises: and sending an operation command code, an address code and a parity check code to the register clock driver through a data bus of the CPU dual in-line memory module channel, and controlling the DRAM particles of the selected channel.
Fig. 5 is a schematic diagram of a hardware structure of an embodiment of the computer device for increasing the transmission rate between the CPU and the DDR5 DIMMs according to the present invention.
Taking the device shown in fig. 5 as an example, the device includes a processor 301 and a memory 302.
The processor 301 and the memory 302 may be connected by a bus or other means, such as the bus connection in fig. 5.
The memory 302 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the memory data area may store data created according to use of a method of increasing a transfer rate between the CPU and the DDR5 DIMMs, or the like. Further, the memory 302 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some embodiments, memory 302 may optionally include memory located remotely from processor 301, which may be connected to local modules over a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
One or more methods of increasing transfer rates between a CPU and a DDR5DIMM corresponding computer instructions 303 are stored in the memory 302 that, when executed by the processor 301, perform the method of increasing transfer rates between a CPU and a DDR5DIMM in any of the method embodiments described above.
Any embodiment of a computer device that implements the above method of increasing the transfer rate between a CPU and a DDR5DIMM may achieve the same or similar effects as any corresponding embodiment of the above method.
The present invention also provides a computer readable storage medium storing a computer program that when executed by a processor performs a method of increasing a transmission rate between a CPU and a DDR5 DIMM.
FIG. 6 is a schematic diagram of one embodiment of a computer storage medium for increasing the transfer rate between a CPU and a DDR5DIMM according to the invention. Taking the computer storage medium as shown in fig. 6 as an example, the computer readable storage medium 401 stores a computer program 402 which, when executed by a processor, performs the method as described above.
Finally, it should be noted that, as one of ordinary skill in the art can appreciate that all or part of the flow of the method of the above embodiments can be implemented by instructing relevant hardware through a computer program, and the program of the method for increasing the transmission rate between the CPU and the DDR5DIMM can be stored in a computer readable storage medium, and when executed, the program can include the flow of the above embodiments of the method. The storage medium of the program may be a magnetic disk, an optical disk, a Read Only Memory (ROM), a Random Access Memory (RAM), or the like. The embodiments of the computer program may achieve the same or similar effects as any of the above-described method embodiments.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
Claims (10)
1. A method for increasing the transfer rate between a CPU and a DDR5DIMM, comprising the steps of:
adding a cache on each of two channels of a DDR5DIMM, wherein one end of the cache is connected with a data bus of a CPU dual in-line memory module channel, and the other end of the cache is respectively connected with a Rank0 and a Rank1 of the DDR5 DIMM;
in response to the CPU sending data to the DDR5DIMM, sending a chip select signal to a register clock driver in the DDR5DIMM to select a corresponding channel;
transmitting data to the cache by using a frequency multiplication technology in a data bus of the CPU dual in-line memory module channel; and
and respectively transmitting the data to Rank0 and Rank1 of DDR5DIMM through the cache.
2. The method of claim 1, further comprising:
in response to the CPU reading the second data in the DDR5DIMM, the Rank0 and the Rank1 of the DDR5DIMM respectively transmit the second data to the cache and send the second data to the data bus of the CPU dual in-line memory module channel through the cache.
3. The method of claim 2, wherein sending the second data to a data bus of the CPU dual in-line memory module channel through the cache comprises:
and transmitting the second data to a data bus of the CPU dual in-line memory module channel by using a frequency multiplication technology in the cache.
4. The method of claim 1, wherein the transmitting the data through the cache to Rank0 and Rank1 of a DDR5DIMM, respectively, comprises:
and sending an operation command code, an address code and a parity check code to the register clock driver through a data bus of the CPU dual in-line memory module channel, and controlling the DRAM particles of the selected channel.
5. A system for increasing the transfer rate between a CPU and a DDR5DIMM, comprising:
the device comprises a setting module, a memory module and a data bus module, wherein the setting module is configured to add a cache on each of two channels of a DDR5DIMM, one end of the cache is connected with the data bus of the CPU dual in-line memory module channel, and the other end of the cache is respectively connected with a Rank0 and a Rank1 of the DDR5 DIMM;
a selection module configured to send a chip select signal to a register clock driver in the DDR5DIMM to select a corresponding channel in response to the CPU sending data to the DDR5 DIMM;
the first transmission module is configured to transmit data to the cache by using a frequency multiplication technology in a data bus of the CPU dual in-line memory module channel; and
and the second transmission module is configured to transmit the data to Rank0 and Rank1 of the DDR5DIMM respectively through the cache.
6. The system of claim 5, further comprising a reading module configured to:
in response to the CPU reading the second data in the DDR5DIMM, the Rank0 and the Rank1 of the DDR5DIMM respectively transmit the second data to the cache and send the second data to the data bus of the CPU dual in-line memory module channel through the cache.
7. The system of claim 6, wherein the reading module is further configured to:
and transmitting the second data to a data bus of the CPU dual in-line memory module channel by using a frequency multiplication technology in the cache.
8. The system of claim 5, wherein the second transmission module is further configured to:
and sending an operation command code, an address code and a parity check code to the register clock driver through a data bus of the CPU dual in-line memory module channel, and controlling the DRAM particles of the selected channel.
9. A computer device, comprising:
at least one processor; and
a memory storing computer instructions executable on the processor, the instructions when executed by the processor implementing the steps of the method of any one of claims 1 to 4.
10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 4.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023221342A1 (en) * | 2022-05-16 | 2023-11-23 | 芯动微电子科技(武汉)有限公司 | Ddr dual-in-line memory module and operation method therefor, and memory system |
| WO2024031798A1 (en) * | 2022-08-09 | 2024-02-15 | 芯动微电子科技(珠海)有限公司 | High-bandwidth ddr dual-in-line memory module, and memory system and operation method therefor |
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2021
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023221342A1 (en) * | 2022-05-16 | 2023-11-23 | 芯动微电子科技(武汉)有限公司 | Ddr dual-in-line memory module and operation method therefor, and memory system |
| WO2024031798A1 (en) * | 2022-08-09 | 2024-02-15 | 芯动微电子科技(珠海)有限公司 | High-bandwidth ddr dual-in-line memory module, and memory system and operation method therefor |
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