CN114443397A - Memory abnormality detection method and device, storage medium and electronic device - Google Patents

Abstract

The embodiment of the invention provides a method and a device for detecting the abnormity of a memory, a storage medium and an electronic device, wherein the method comprises the following steps: under the condition that a Central Processing Unit (CPU) is started, acquiring data transmitted on a Linear Predictive Coding (LPC) bus of a bus controller in the CPU; under the condition that abnormal data are determined, recording the number of times of abnormal data existing in a register in the complex programmable logic device CPLD in a preset period, wherein the register is used for storing data transmitted on the LPC bus; and detecting whether the memory in the CPU is abnormal or not based on the number of times of existence of the abnormal data. By the method and the device, the problem of detecting the memory fault in the related technology is solved, and the effect of accurately detecting whether the memory has the fault is achieved.

Description

Memory abnormality detection method and device, storage medium and electronic device

Technical Field

The embodiment of the invention relates to the field of communication, in particular to a memory abnormity detection method and device, a storage medium and an electronic device.

Background

In the prior art, a Central Processing Unit (CPU) is used to monitor a peripheral configuration circuit. The CPU generates a detection result type coding signal under normal starting. Under the condition of no memory insertion, a Basic Input/Output System (BIOS for short) cannot be started, and if the CPU is abnormally started, the memory fault detection cannot be performed.

Disclosure of Invention

The embodiment of the invention provides a memory abnormity detection method and device, a storage medium and an electronic device, which are used for at least solving the problem of memory fault detection in the related technology.

According to an embodiment of the present invention, there is provided an abnormality detection method including: under the condition that a Central Processing Unit (CPU) is started, acquiring data transmitted on a Linear Predictive Coding (LPC) bus of a bus controller in the CPU; under the condition that abnormal data are determined, recording the number of times of existence of the abnormal data in a register in a Complex Programmable Logic Device (CPLD) in a preset period, wherein the register is used for storing the data transmitted on the LPC bus; and detecting whether the memory in the CPU is abnormal or not based on the number of times of existence of the abnormal data.

According to another embodiment of the present invention, there is provided an abnormality detection apparatus for a memory, including: the first acquisition module is used for acquiring data transmitted on an LPC bus of a bus controller in a Central Processing Unit (CPU) under the condition that the CPU is started; the first recording module is used for recording the number of times of the abnormal data in a register in a Complex Programmable Logic Device (CPLD) in a preset period under the condition that the abnormal data is determined, wherein the register is used for storing the data transmitted on the LPC bus; and the first detection module is used for detecting whether the memory in the CPU is abnormal or not based on the number of times of existence of the abnormal data.

In an exemplary embodiment, the first obtaining module includes: and the first acquisition unit is used for acquiring the transmitted starting data of the CPU at a preset address in the LPC bus under the condition that the CPU is started.

In an exemplary embodiment, the first recording module includes: a first determining unit, configured to determine that abnormal data occurs when data transmitted at a preset address in the LPC bus does not include startup data of the CPU; the first starting unit is used for starting monitoring a register, wherein the register is used for storing data transmitted on a preset address in the LPC bus; and the first statistic unit is used for counting the times of abnormal data in the register in the preset period.

In an exemplary embodiment, the first recording module includes: a second determining unit, configured to determine that the abnormal data occurs when data transmitted at a preset address in the LPC bus is preset data; a second starting unit, configured to start monitoring on the register, where the register is used to store data transmitted at a preset address in the LPC bus; and the second statistical unit is used for counting the times of the abnormal data in the register in the preset period.

In an exemplary embodiment, the first detecting module includes: and the third determining unit is used for determining that the memory in the CPU is abnormal and sending out alarm information under the condition that the number of times of existence of the abnormal data is greater than a preset threshold value.

According to a further embodiment of the present invention, there is also provided a computer-readable storage medium having a computer program stored thereon, wherein the computer program is arranged to perform the steps of any of the above method embodiments when executed.

According to yet another embodiment of the present invention, there is also provided an electronic device, including a memory in which a computer program is stored and a processor configured to execute the computer program to perform the steps in any of the above method embodiments.

According to the invention, under the condition that the CPU is started, the data transmitted on the LPC bus of the bus controller in the CPU is obtained; under the condition that abnormal data are determined, recording the number of times of abnormal data existing in a register in the complex programmable logic device CPLD in a preset period, wherein the register is used for storing data transmitted on the LPC bus; and detecting whether the memory in the CPU is abnormal or not based on the number of times of existence of the abnormal data. The anomaly detection of the memory is realized. Therefore, the problem of detecting the memory fault in the related technology can be solved, and the effect of accurately detecting whether the memory has the fault is achieved.

Drawings

Fig. 1 is a block diagram of a hardware structure of a mobile terminal of a method for detecting an abnormality of a memory according to an embodiment of the present invention;

FIG. 2 is a flow chart of a method for detecting memory anomalies according to an embodiment of the invention;

FIG. 3 is a schematic diagram of a system architecture according to an embodiment of the present invention;

FIG. 4 is an overall flow diagram according to an embodiment of the invention;

fig. 5 is a block diagram of an abnormality detection apparatus for a memory according to an embodiment of the present invention.

Detailed Description

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings in conjunction with the embodiments.

It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.

The method embodiments provided in the embodiments of the present application may be executed in a mobile terminal, a computer terminal, or a similar computing device. Taking an example of the operation on a mobile terminal, fig. 1 is a hardware structure block diagram of the mobile terminal of the method for detecting an abnormality of a memory according to the embodiment of the present invention. As shown in fig. 1, the mobile terminal may include one or more (only one shown in fig. 1) processors 102 (the processor 102 may include, but is not limited to, a processing device such as a microprocessor MCU or a programmable logic device FPGA), and a memory 104 for storing data, wherein the mobile terminal may further include a transmission device 106 for communication functions and an input-output device 108. It will be understood by those skilled in the art that the structure shown in fig. 1 is only an illustration, and does not limit the structure of the mobile terminal. For example, the mobile terminal may also include more or fewer components than shown in FIG. 1, or have a different configuration than shown in FIG. 1.

The memory 104 may be used to store a computer program, for example, a software program and a module of an application software, such as a computer program corresponding to the method for detecting the memory anomaly in the embodiment of the present invention, and the processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, so as to implement the method described above. The memory 104 may include high speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include memory located remotely from the processor 102, which may be connected to the mobile terminal over a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The transmission device 106 is used for receiving or transmitting data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider of the mobile terminal. In one example, the transmission device 106 includes a Network adapter (NIC), which can be connected to other Network devices through a base station so as to communicate with the internet. In one example, the transmission device 106 may be a Radio Frequency (RF) module, which is used for communicating with the internet in a wireless manner.

In this embodiment, a method for detecting an abnormality of a memory is provided, and fig. 2 is a flowchart of a method for detecting an abnormality of a memory according to an embodiment of the present invention, as shown in fig. 2, the flowchart includes the following steps:

step S202, under the condition that a Central Processing Unit (CPU) is started, data transmitted on a LPC bus of a bus controller in the CPU are obtained;

step S204, under the condition that abnormal data are determined, recording the number of times of abnormal data existing in a register in the complex programmable logic device CPLD in a preset period, wherein the register is used for storing data transmitted on the LPC bus;

in step S206, it is detected whether the memory in the CPU is abnormal based on the number of times the abnormal data exists.

The execution subject of the above steps may be a CPLD, etc., but is not limited thereto.

In this embodiment, the data flow is monitored by an external circuit without requiring the CPU to be fully booted. The non-memory detection alarm can be realized without the judgment of a BIOS program.

Through the steps, under the condition that the central processing unit CPU is started, data transmitted on a LPC bus of a bus controller in the CPU are obtained; under the condition that abnormal data are determined, recording the number of times of the abnormal data in a preset period of a register in the complex programmable logic device CPLD, wherein the register is used for storing data transmitted on the LPC bus; and detecting whether the memory in the CPU is abnormal or not based on the number of times of existence of the abnormal data. The anomaly detection of the memory is realized. Therefore, the problem of detecting the memory fault in the related technology can be solved, and the effect of accurately detecting whether the memory has the fault is achieved.

In an exemplary embodiment, in the case of a central processing unit CPU startup, acquiring data transmitted on a bus controller LPC bus in the CPU includes:

and S11, acquiring the transmitted CPU starting data at the preset address in the LPC bus under the condition that the CPU is started.

In this embodiment, for example, during the startup of the CPU, when there is a normal memory, 80Port data during the startup of the CPU is output at the address 80 of the LPC bus.

In an exemplary embodiment, in the case that it is determined that abnormal data occurs, the recording of the number of times of occurrence of abnormal data in a register in the complex programmable logic device CPLD within a preset period includes:

s21, determining abnormal data when the data transmitted on the preset address in the LPC bus does not include the starting data of the CPU;

s22, starting the monitoring of a register, wherein the register is used for storing data transmitted on a preset address in an LPC bus;

and S23, counting the times of abnormal data in the register in a preset period.

In this embodiment, for example, the CPLD monitors data at 80 addresses of the (read only) LPC bus in real time, collects each data, stores each data in a register, determines whether the data is the preset stop data, and determines whether a corresponding action is triggered.

In an exemplary embodiment, in the case that it is determined that abnormal data occurs, the recording of the number of times of occurrence of abnormal data in a register in the complex programmable logic device CPLD within a preset period includes:

s31, determining abnormal data when the data transmitted on the preset address in the LPC bus is preset data;

s32, starting the monitoring of a register, wherein the register is used for storing data transmitted on a preset address in an LPC bus;

and S33, counting the times of abnormal data in the register in a preset period.

For example, if the acquired data is the preset stop data, the judgment mechanism is triggered, that is, the register is read once at regular intervals, whether the value is the preset stop data is judged, and if the value is the preset stop data, the counter is incremented by one.

In one exemplary embodiment, detecting the memory in the CPU that is abnormal based on the amount of abnormal data includes:

and S41, determining that the memory in the CPU is abnormal and sending out warning information under the condition that the number of times of the abnormal data is greater than a preset threshold value.

For example, an alarm message is issued by a buzzer device.

The invention is illustrated below with reference to specific examples:

in the embodiment, a CPLD or a logic control unit is adopted to directly analyze an LPC bus protocol, and the condition of no internal memory can be judged without completely starting a CPU; meanwhile, the CPU draws the memory, so that whether the memory is normal or not can be identified. The system consists of a CPU, N memory banks, a CPLD or logic control unit and a buzzer, and is shown in figure 3.

In this embodiment, as shown in fig. 4, the flow of this embodiment includes the following steps:

s401, in the process of CPU starting, when there is normal memory, 80Port data in the process of CPU starting will be output at 80 addresses of LPC bus. When there is no memory or abnormal memory, the special 80Port data is not output, but the data stops at a fixed 80Port data.

S402, the CPLD monitors the data at the 80 addresses of the (read-only) LPC bus in real time, collects each data and stores each data in a register.

S403, determining whether the data is the preset stop data, and determining whether to trigger the corresponding action, if yes, going to S405, otherwise, going to S404.

And S404, continuing to collect.

S405, if the acquired data is preset stop data, triggering a judgment mechanism, namely reading the register at regular intervals, and judging whether the value is the preset stop data.

S406, if yes, the counter is increased by one.

S407, if the count of the counter exceeds a preset value, the buzzer buzzes and alarms; if the acquired data is non-preset stop data, the judgment action is not triggered.

In summary, in the embodiment, the external circuit monitors the data stream to realize the no-memory detection alarm. Without requiring the CPU to be fully booted. The judgment of a BIOS program is not needed, the method is relatively fast, and the method can be adapted to more platforms.

Through the above description of the embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but the former is a better implementation mode in many cases. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which is stored in a storage medium (e.g., ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal device (e.g., a mobile phone, a computer, a server, or a network device) to execute the method according to the embodiments of the present invention.

In this embodiment, a device for detecting an abnormality of a memory is further provided, where the device is used to implement the foregoing embodiments and preferred embodiments, and details of which have been already described are omitted. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. Although the means described in the embodiments below are preferably implemented in software, an implementation in hardware, or a combination of software and hardware is also possible and contemplated.

Fig. 5 is a block diagram of an abnormality detection apparatus for a memory according to an embodiment of the present invention, and as shown in fig. 5, the apparatus includes:

a first obtaining module 52, configured to obtain data transmitted on an LPC bus of a bus controller in the CPU when the CPU is started;

the first recording module 54 is configured to record, when it is determined that abnormal data occurs, the number of times that abnormal data exists in a register of the complex programmable logic device CPLD in a preset period, where the register is used to store data transmitted on the LPC bus;

the first detecting module 56 is configured to detect whether an abnormality occurs in the memory of the CPU based on the number of times the abnormal data exists.

In an exemplary embodiment, the first obtaining module includes:

and the first acquisition unit is used for acquiring the transmitted starting data of the CPU at a preset address in the LPC bus under the condition that the CPU is started.

In an exemplary embodiment, the first recording module includes:

a first determining unit, configured to determine that abnormal data occurs when data transmitted at a preset address in the LPC bus does not include start-up data of the CPU;

the first starting unit is used for starting monitoring a register, wherein the register is used for storing data transmitted on a preset address in the LPC bus;

and the first statistic unit is used for counting the times of abnormal data in the register in the preset period.

In an exemplary embodiment, the first recording module includes:

a second determining unit, configured to determine that the abnormal data occurs when data transmitted at a preset address in the LPC bus is preset data;

a second starting unit, configured to start monitoring on the register, where the register is used to store data transmitted at a preset address in the LPC bus;

and the second statistical unit is used for counting the times of the abnormal data in the register in the preset period.

In an exemplary embodiment, the first detecting module includes:

and the third determining unit is used for determining that the memory in the CPU is abnormal and sending out alarm information under the condition that the number of times of existence of the abnormal data is greater than a preset threshold value.

It should be noted that, the above modules may be implemented by software or hardware, and for the latter, the following may be implemented, but not limited to: the modules are all positioned in the same processor; alternatively, the modules are respectively located in different processors in any combination.

Embodiments of the present invention also provide a computer-readable storage medium having a computer program stored thereon, wherein the computer program is arranged to perform the steps of any of the above-mentioned method embodiments when executed.

In the present embodiment, the above-described computer-readable storage medium may be configured to store a computer program for executing the above steps.

In an exemplary embodiment, the computer readable storage medium may include, but is not limited to: various media capable of storing computer programs, such as a usb disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic disk, or an optical disk.

Embodiments of the present invention also provide an electronic device comprising a memory having a computer program stored therein and a processor arranged to run the computer program to perform the steps of any of the above method embodiments.

In an exemplary embodiment, the electronic apparatus may further include a transmission device and an input/output device, wherein the transmission device is connected to the processor, and the input/output device is connected to the processor.

In an exemplary embodiment, the processor may be configured to execute the above steps by a computer program.

For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary embodiments, and details of this embodiment are not repeated herein.

It will be apparent to those skilled in the art that the various modules or steps of the invention described above may be implemented using a general purpose computing device, they may be centralized on a single computing device or distributed across a network of computing devices, and they may be implemented using program code executable by the computing devices, such that they may be stored in a memory device and executed by the computing device, and in some cases, the steps shown or described may be performed in an order different than that described herein, or they may be separately fabricated into various integrated circuit modules, or multiple ones of them may be fabricated into a single integrated circuit module. Thus, the present invention is not limited to any specific combination of hardware and software.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the principle of the present invention should be included in the protection scope of the present invention.

Claims (9)

1. A method for detecting memory abnormality is characterized by comprising the following steps:

under the condition that a Central Processing Unit (CPU) is started, acquiring data transmitted on a Linear Predictive Coding (LPC) bus of a bus controller in the CPU;

under the condition that abnormal data are determined, recording the number of times of existence of the abnormal data in a register in a Complex Programmable Logic Device (CPLD) in a preset period, wherein the register is used for storing the data transmitted on the LPC bus;

and detecting whether the memory in the CPU is abnormal or not based on the number of times of existence of the abnormal data.

2. The method of claim 1, wherein acquiring data transmitted on an LPC bus of a bus controller in a Central Processing Unit (CPU) in case of the CPU being started comprises:

and under the condition that a Central Processing Unit (CPU) is started, acquiring transmitted starting data of the CPU at a preset address in the LPC bus.

3. The method according to claim 1, wherein, in the event that anomalous data is determined to occur, recording the number of times said anomalous data has occurred in a register of the complex programmable logic device CPLD within a preset period comprises:

determining the abnormal data when the data transmitted on the preset address in the LPC bus does not include the starting data of the CPU;

starting monitoring the register, wherein the register is used for storing data transmitted at a preset address in the LPC bus;

and counting the times of the abnormal data in the register in the preset period.

4. The method according to claim 1, wherein, in the event that anomalous data is determined to occur, recording the number of times said anomalous data has occurred in a register of the complex programmable logic device CPLD within a preset period comprises:

determining that the abnormal data occurs under the condition that data transmitted on a preset address in the LPC bus is preset data;

starting monitoring the register, wherein the register is used for storing data transmitted at a preset address in the LPC bus;

and counting the times of the abnormal data in the register in the preset period.

5. The method according to any one of claims 1 to 4, wherein detecting the occurrence of an exception in the memory of the CPU based on the amount of the exception data comprises:

and under the condition that the number of times of existence of the abnormal data is greater than a preset threshold value, determining that the memory in the CPU is abnormal, and sending out alarm information.

6. An abnormality detection device for a memory, comprising:

the first acquisition module is used for acquiring data transmitted on a LPC bus of a bus controller in a Central Processing Unit (CPU) under the condition that the CPU is started;

the first recording module is used for recording the number of times of the abnormal data in a register in a Complex Programmable Logic Device (CPLD) in a preset period under the condition that the abnormal data is determined, wherein the register is used for storing the data transmitted on the LPC bus;

and the first detection module is used for detecting whether the memory in the CPU is abnormal or not based on the number of times of existence of the abnormal data.

7. The apparatus of claim 6, further comprising:

and the N storage devices are used for storing the data transmitted on the LPC bus, wherein N is a natural number which is greater than or equal to 1.

8. A computer-readable storage medium, in which a computer program is stored, which computer program, when being executed by a processor, carries out the method of any one of claims 1 to 5.

9. An electronic device comprising a memory and a processor, wherein the memory has stored therein a computer program, and wherein the processor is arranged to execute the computer program to perform the method of any of claims 1 to 5.

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