CN114442924B - Control method and device of irregular controller - Google Patents
Control method and device of irregular controller Download PDFInfo
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- CN114442924B CN114442924B CN202111478123.2A CN202111478123A CN114442924B CN 114442924 B CN114442924 B CN 114442924B CN 202111478123 A CN202111478123 A CN 202111478123A CN 114442924 B CN114442924 B CN 114442924B
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- 238000000034 method Methods 0.000 title claims abstract description 36
- 230000015654 memory Effects 0.000 claims abstract description 75
- 238000012545 processing Methods 0.000 claims description 33
- 230000003993 interaction Effects 0.000 abstract description 4
- 230000005855 radiation Effects 0.000 description 7
- 238000004590 computer program Methods 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
- G06F3/0619—Improving the reliability of storage systems in relation to data integrity, e.g. data losses, bit errors
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0629—Configuration or reconfiguration of storage systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
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Abstract
The invention discloses a control method and a control device of an irregular controller, which are characterized in that the reliability of MRAM storage is enhanced by applying the irregular controller in an MRAM storage, and the influence of the outside on the damage of the MRAM storage controller can be optimized by adopting the irregular controller; the main controller and the auxiliary controller are adopted to jointly monitor and manage the same MRAM storage block, and the reliability of storage can be improved by using MRAM storage in a severe environment; adding an interaction signal between the main controller and the auxiliary controller stored in the MRAM, and sending a signal to the auxiliary controller when the task executed by the main controller is normal, wherein the auxiliary controller judges whether the auxiliary main controller is required to work according to a feedback signal of the main controller; if the secondary controller does not receive signals from the main controller more than three times through the logic judgment mode, the secondary controller will be used as the main controller of the MRAM memory block to complete the next work.
Description
Technical Field
The invention relates to the technical field of irregular controllers, in particular to a control method and a control device of an irregular controller.
Background
MRAM memory has the advantages of nonvolatile property, high read-write speed and the like as a novel memory. Has radiation-resistant properties relative to conventional memories and other new types of nonvolatile memories. While memory applications are resistant to radiation conditions in strongly interfering environments, MRAM controllers are mostly composed of CMOS tubes. The controller composed of these CMOS transistors does not resist radiation well. Meanwhile, aiming at the phenomenon that the Flash storage is broken down by specified interference of laser and the like, the memory cell of the MRAM can resist the strong interference of the laser. The MRAM has a certain resistance to external sources relative to other memories. The MRAM controller is composed of CMOS transistors, however, which is vulnerable to damage to the memory controller by external disturbances.
Several generations of memory cells of MRAM are composed of metallic materials, which effectively help MRAM to resist high radiation, to operate under extreme temperature conditions, and to tamper-proof internal information. While most of the current large-scale integrated circuits of the controller are Si-based, an interference source can reflect and transmit Si incident from air, and the transmitted light is partially absorbed by Si to generate photoelectric effect and photo-thermal effect. Resulting in the memory controller being affected and not continuing to control MRAM memory operation, a two-terminal phenomenon occurs. To address the problem of memory control materials that cannot be altered, it is desirable to increase irregular memory controller operation. While also taking into account memory area issues. This requires a measure of the operation of the memory control MRAM memory module and the overall area of the memory chip of the overall MRAM. If the controller is excessively increased, the chip area is directly caused to be too large, and the advantage of the MRAM memory chip is reduced.
Disclosure of Invention
The invention aims to provide a control method and a control device for an irregular controller, wherein a main controller and an auxiliary controller are adopted to control the same MRAM storage block, and the irregular controller can optimize the influence of the outside on the damage of the MRAM storage controller.
A control method of an irregular controller, comprising:
the system is initialized and the chip is electrified;
the control module sets and outputs different state machines through the register, analyzes the command from the processing module and executes the command;
the control module comprises a main controller and an auxiliary controller, and the auxiliary controller judges whether the main controller has executed the command and sends a signal to the auxiliary controller;
if the master controller sends a signal to the slave controller, the slave controller will continuously monitor the master controller.
As a further preferred aspect, the method further comprises: if the task is overtime and the signal of the main controller is not received, the auxiliary controller directly executes the command.
As a further preferred aspect, the method further comprises: if the main controller cannot work normally, the auxiliary controller directly executes the command.
As a further preferred aspect, the method further comprises: if the auxiliary controller directly executes the command for more than three times, the auxiliary controller continuously executes the command and sends a signal to a new auxiliary controller.
As a further preferred feature, the system complete initialization includes clearing all internal state machine and configuration mode registers and configuration extension registers.
As a further preferred aspect, the control module transmits the data of the storage module to the storage control module sequentially through the sensitive amplifier and the data processing to the I/O bus.
As a further preference, the primary controller and the secondary controller receive commands from the processing module simultaneously, the primary controller receives commands and then executes the commands, and the secondary controller is only responsible for receiving commands but not executing the commands.
The control device of the irregular controller comprises the control method of the irregular controller, a control module and a processing module, wherein the control module is used for analyzing commands from the processing module and executing the commands; the control module comprises a main controller and an auxiliary controller:
the main controller is in signal connection with the processing module and is used for receiving the command of the processing module and executing the command, and sending a signal to the auxiliary controller after completing the command;
the auxiliary controller is in signal connection with the processing module and is used for receiving the command of the processing module and the signal of the main controller.
As a further preferred aspect, the secondary controller is further configured to determine whether a signal from the primary controller is received:
if the task is overtime and the signal of the main controller is not received, the auxiliary controller directly executes the command;
if the main controller cannot work normally, the auxiliary controller directly executes the command;
if the auxiliary controller directly executes the command for more than three times, the auxiliary controller continuously executes the command and sends a signal to a new auxiliary controller.
As a further preferable mode, the control module further comprises a state machine, a configuration mode register and a configuration expansion register, and after the system is initialized, the state machine, the configuration mode register and the configuration expansion register are all cleared; the configuration mode register and the configuration extension register are used for setting and outputting different state machines.
An electronic device, comprising:
a memory and one or more processors;
wherein the memory is communicatively coupled to the one or more processors, and instructions executable by the one or more processors are stored in the memory, which when executed by the one or more processors, are operable to implement the method as described in any one of the above embodiments.
A computer readable storage medium having stored thereon computer executable instructions which, when executed by a computing device, are operable to implement a method as described in any of the above embodiments.
A computer program product comprising a computer program stored on a computer readable storage medium, the computer program comprising program instructions which, when executed by a computer, are operable to implement a method as described in any one of the embodiments above.
The technical scheme has the following advantages or beneficial effects:
the control method and the device of the irregular controller can enhance the reliability of the MRAM storage by applying the irregular controller in the MRAM storage, and can optimize the influence of the outside on the damage of the MRAM storage controller by adopting the irregular controller; the main controller and the auxiliary controller are adopted to jointly monitor and manage the same MRAM storage block, and the reliability of storage can be improved by using MRAM storage in a severe environment; adding an interaction signal between the main controller and the auxiliary controller stored in the MRAM, and sending a signal to the auxiliary controller when the task executed by the main controller is normal, wherein the auxiliary controller judges whether the auxiliary main controller is required to work according to a feedback signal of the main controller; if the secondary controller does not receive signals from the main controller more than three times through the logic judgment mode, the secondary controller will be used as the main controller of the MRAM memory block to complete the next work.
Drawings
FIG. 1 is a flow chart of a method of controlling an irregular controller according to the present invention;
FIG. 2 is a schematic diagram of a control device of an irregular controller according to the present invention;
FIG. 3 is a schematic flow chart of the monitoring operation of the irregular controller of the present invention.
Detailed Description
In order that the above objects, features and advantages of the invention will be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
MRAM is used to perform MRAM internal writing operations by reversing the free layer by a magnetic field or current. The read operation obtains whether the stored data is 0 or 1 by monitoring the high and low resistance states of the memory cell. The memory cells of MRAM are based on metallic materials, which results in MRAM having a higher radiation resistance than conventional memory. The read-write principle and the memory cell material of the MRAM enable MRAM storage with high reliability and fast read-write capability. This poses a challenge to the reliability of the storage controller.
Referring to fig. 1 and 3, a control method of an irregular controller is characterized by comprising:
the system is initialized and the chip is electrified;
the control module sets and outputs different state machines through the register, analyzes the command from the processing module and executes the command;
the control module comprises a main controller and an auxiliary controller, and the auxiliary controller judges whether the main controller has executed the command and sends a signal to the auxiliary controller;
if the main controller sends a signal to the auxiliary controller, the auxiliary controller continuously monitors the main controller;
if the task is overtime and the signal of the main controller is not received, the auxiliary controller directly executes the command;
if the main controller cannot work normally, the auxiliary controller directly executes the command;
if the auxiliary controller directly executes the command for more than three times, the auxiliary controller continuously executes the command and sends a signal to a new auxiliary controller.
The main controller and the auxiliary controller simultaneously receive CPU instructions, and the auxiliary controller monitors the execution task condition of the main controller after receiving signals. If the main controller times out and feedback is not given, the auxiliary controller executes the command.
The invention adopts a logic judgment mode, and if the main controller does not execute the command to the auxiliary controller more than three times, the main controller sends a signal. The MRAM memory chip can confirm that the primary controller has been destroyed, and the secondary controller will then switch to the primary controller to complete the management of the MRAM memory blocks.
Further, in a preferred embodiment of the control method of an irregular controller of the present invention, the system performing initialization includes clearing all of the internal state machine and configuration mode register and configuration extension register.
Further, in a preferred embodiment of the control method of the irregular controller of the present invention, the control module transmits the data of the storage module to the storage control module sequentially through the sensitive amplifier and the data processing to the I/O bus.
Further, in a preferred embodiment of the control method of an irregular controller of the present invention, the main controller and the auxiliary controller receive the command of the processing module at the same time, the main controller receives the command and then executes the command, and the auxiliary controller is only responsible for receiving the command but not executing the command.
The invention monitors and manages the same MRAM memory block through the main controller and the auxiliary controller. When the MRAM memory is interfered by external radiation or laser and other interference sources, the MRAM memory cell can effectively resist damage caused by external environments. However, the memory controller of MRAM is mainly composed of CMOS, which may cause the memory controller to be affected by external interference sources and maliciously damaged. The irregular controller can optimize the phenomenon that an external source damages the memory.
The invention adopts the main controller and the auxiliary controller to monitor and control the same MRAM storage. The method can optimize the stability problem of MRAM storage, respond to CPU instruction immediately, and does not lose internal data. The irregular memory controller may enhance the reliability of MRAM storage.
Finishing the storage initialization work of the controller and the MRAM, and enabling a chip to have a stable period for a certain time after being electrified, wherein the period does not receive a command of the controller, and the initialization is controlled to clear the internal state machine, the configuration mode register and the configuration expansion register;
after initialization is completed, each controller confirms the corresponding MRAM memory block, and as the CPU and the MRAM memory unit can only execute a single task, the situation of task overlapping does not exist, the controller sets and outputs different state machines through an internal register, analyzes the command from the CPU and executes the command. The controller transmits the data of the storage unit to the storage controller by sequentially passing through the sensitive amplifier and the data processing to the I/O bus;
in order to prevent the situation that the controller cannot work, the auxiliary controller is adopted to monitor the working condition of the main controller, the main controller and the auxiliary controller can simultaneously receive the command of the CPU, the main controller can execute after receiving the command, and the auxiliary controller is only responsible for receiving the command but not executing: when the controller finishes the command, a signal is sent to the auxiliary controller, and the auxiliary controller does not need to give feedback after receiving the command;
if the task is overtime and a command of the main controller is not received, the auxiliary controller directly executes the work;
if the main controller works normally, the auxiliary controller monitors continuously; if the main controller cannot work normally, the auxiliary controller directly executes the work;
if the command of the main controller is not executed for more than three times, the MRAM memory block responsible for the main controller is responsible for the next work by the auxiliary controller, and the auxiliary controller is initialized to be changed into the main controller.
Referring to fig. 2, a control device of an irregular controller includes the control method of an irregular controller, and further includes a control module 1 and a processing module 2, where the control module 1 is configured to parse a command from the processing module 2 and execute the command; the control module 1 includes a main controller 11 and a sub controller 12:
the main controller 11 is in signal connection with the processing module 2, and is configured to receive a command from the processing module 2, execute the command, and send a signal to the auxiliary controller 12 after completing the command;
the auxiliary controller 12 is in signal connection with the processing module 2, and is configured to receive the command of the processing module 2 and the signal of the main controller 11, and when the main controller 11 completes the command, the signal is sent to the auxiliary controller 12, and at this time, the auxiliary controller 12 does not need to give feedback after receiving. If the task has timed out and a command from the main controller 11 has not been received, the sub-controller 12 will directly perform this task. .
Further, in a preferred embodiment of the control device of the irregular controller of the present invention, the auxiliary controller 12 is further configured to determine whether the signal of the main controller 11 is received:
if the task is overtime and the signal of the main controller 11 is not received, the auxiliary controller 12 directly executes the command;
if the main controller 11 cannot work normally, the auxiliary controller 12 will directly execute the command;
if the secondary controller 12 is to directly execute the command more than three times, the secondary controller 12 continues to execute the command and sends a signal to the new secondary controller.
Further, in a preferred embodiment of the control device of the irregular controller of the present invention, the control module 1 further includes a state machine, a configuration mode register and a configuration extension register, and after the system is initialized, the state machine, the configuration mode register and the configuration extension register are all cleared; the configuration mode register and the configuration extension register are used for setting and outputting different state machines.
The invention adopts the irregular memory controller to control the MRAM, and prevents a certain controller from generating problems. The MRAM memory multi-controller architecture uses QSPI protocol as the master control protocol. Because the QSPI protocol has a plurality of IOs, one IO writes, and the rest of I/O can control the reading work of three MRAM memory blocks at most. The present invention controls four or more MRAM memory blocks through such off-specification controllers. The first memory controller, the second memory controller and the third memory controller respectively master and control one MRAM memory block. And when the main control MRAM storage does not work, performing read-write management on other MRAM storage blocks. The state machine of the memory controller completes the work of receiving commands, analyzing commands, executing commands and the like for the memory array operation.
The invention adopts the main controller and the auxiliary controller to control the same MRAM memory block by using the irregular controller structure of the MRAM memory. The CPU transmits the command to be executed to the main controller and the auxiliary controller simultaneously. The main controller analyzes and executes the command after receiving the command, and the auxiliary controller only receives the command but does not execute the command. In the process of executing the command by the main controller, the auxiliary controller can confirm whether the current main controller completes the working condition of the command through the internal interaction signal of the main/auxiliary controller. If the master controller receives only the command but does not execute, the master controller will not transmit a signal to the slave controller. When the auxiliary controller overtime does not receive a signal from the main controller, the auxiliary controller completes a CPU command which is not executed by the main controller. If the secondary controller performs the operation of the primary controller more than three times, the MRAM memory may be internally verified that the primary controller is not a single exception but is corrupted. Because the MRAM is made of metal materials, the interference of laser, radiation and the like can be resisted, the influence of the outside on the damage of the MRAM storage controller can be optimized by adopting the irregular controller.
An electronic device, comprising:
a memory and one or more processors;
wherein the memory is communicatively coupled to the one or more processors, the memory having stored therein instructions executable by the one or more processors, the instructions, when executed by the one or more processors, for implementing the method as claimed in any one of the preceding claims.
In particular, the processor and the memory may be connected by a bus or otherwise, for example by a bus connection. The processor may be a central processing unit (Central Processing Unit, CPU). The processor may also be any other general purpose processor, digital signal processor (Digital Signal Processor, DSP), application specific integrated circuit (Application Specific Integrated Circuit, ASIC), field programmable gate array (Field-Programmable Gate Array, FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof.
The memory, as a non-transitory computer readable storage medium, may be used to store non-transitory software programs, non-transitory computer executable programs, and modules, such as cascading progressive networks, and the like, in embodiments of the present application. The processor executes various functional applications of the processor and data processing by running non-transitory software programs/instructions and functional modules stored in the memory.
The memory may include a memory program area and a memory data area, wherein the memory program area may store an operating system, at least one application program required for a function; the storage data area may store data created by the processor, etc. In addition, the memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid state storage device. In some embodiments, the memory optionally includes memory provided remotely from the processor, the remote memory being connectable to the processor through a network, such as through a communication interface. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
A computer readable storage medium having stored thereon computer executable instructions which, when executed by a computing device, are operable to implement a method as claimed in any one of the preceding claims.
The foregoing computer-readable storage media includes both physical volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer-readable instructions, data structures, program modules or other data. Computer-readable storage media includes, but is not limited to, U disk, removable hard disk, read-Only Memory (ROM), random access Memory (RAM, random Access Memory), erasable programmable Read-Only Memory (EPROM), electrically erasable programmable Read-Only Memory (EEPROM), flash Memory or other solid state Memory technology, CD-ROM, digital Versatile Disks (DVD), HD-DVD, blue-Ray or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium capable of storing the desired information and that can be accessed by a computer.
While the subject matter described herein is provided in the general context of operating systems and application programs that execute in conjunction with the execution of a computer system, those skilled in the art will recognize that other implementations may also be performed in combination with other types of program modules. Generally, program modules include routines, programs, components, data structures, and other types of structures that perform particular tasks or implement particular abstract data types. Those skilled in the art will appreciate that the subject matter described herein may be practiced with other computer system configurations, including hand-held devices, multiprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, mainframe computers, and the like, as well as distributed computing environments that have tasks performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules may be located in both local and remote memory storage devices.
Those of ordinary skill in the art will appreciate that the elements and method steps of the examples described in connection with the embodiments of the application herein may be implemented as electronic hardware, or as a combination of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on such understanding, the technical solution of the present application may be embodied in essence or a part contributing to the prior art or a part of the technical solution, or in the form of a software product stored in a storage medium, including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in the embodiments of the present application.
In summary, the control method and the device of the irregular controller of the invention enhance the reliability of the MRAM storage by applying the irregular controller in the MRAM storage, and the irregular controller can optimize the influence of the outside on the damage of the MRAM storage controller; the main controller and the auxiliary controller are adopted to jointly monitor and manage the same MRAM storage block, and the reliability of storage can be improved by using MRAM storage in a severe environment; adding an interaction signal between the main controller and the auxiliary controller stored in the MRAM, and sending a signal to the auxiliary controller when the task executed by the main controller is normal, wherein the auxiliary controller judges whether the auxiliary main controller is required to work according to a feedback signal of the main controller; if the secondary controller does not receive signals from the main controller more than three times through the logic judgment mode, the secondary controller will be used as the main controller of the MRAM memory block to complete the next work.
The foregoing is merely illustrative of the preferred embodiments of the present invention and is not intended to limit the embodiments and scope of the present invention, and it should be appreciated by those skilled in the art that equivalent substitutions and obvious variations may be made using the description and illustrations of the present invention, and are intended to be included in the scope of the present invention.
In the description of the present invention, it should be understood that the directions or positional relationships indicated by the terms "upper", "lower", "front", "rear", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the apparatus or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention.
Claims (10)
1. A control method of an irregular controller, characterized by comprising:
the system is initialized and the chip is electrified;
the control module sets and outputs different state machines through the register, analyzes the command from the processing module and executes the command;
the control module comprises a main controller and an auxiliary controller, wherein the auxiliary controller judges whether the main controller finishes executing the command and sends a signal to the auxiliary controller, the main controller and the auxiliary controller can simultaneously receive the command of the processing module, the main controller can execute after receiving the command, and the auxiliary controller is only responsible for receiving the command but not executing the command;
if the main controller sends a signal to the auxiliary controller, the auxiliary controller continuously monitors the main controller;
if the task is overtime and the signal of the main controller is not received, the auxiliary controller directly executes the command.
2. The method for controlling an irregular controller according to claim 1, further comprising: if the main controller cannot work normally, the auxiliary controller directly executes the command.
3. The control method of an irregular controller according to claim 1 or 2, further comprising: if the auxiliary controller directly executes the command for more than three times, the auxiliary controller continuously executes the command and sends a signal to a new auxiliary controller.
4. The method of claim 1, wherein the system complete initialization includes clearing all internal state machine and configuration mode registers and configuration extension registers.
5. The method for controlling an irregular controller according to claim 1, wherein the control module transmits the data of the memory module to the memory control module sequentially through the sensitive amplifier and the data processing to the I/O bus.
6. A control device of an irregular controller comprising a control method of an irregular controller according to any one of claims 1-5, characterized by further comprising a control module (1) and a processing module (2), said control module (1) being adapted to parse a command from said processing module (2) and to execute it; the control module (1) comprises a main controller (11) and an auxiliary controller (12):
the main controller (11) is in signal connection with the processing module (2) and is used for receiving the command of the processing module (2) and executing the command, and sending a signal to the auxiliary controller (12) after completing the command;
the auxiliary controller (12) is in signal connection with the processing module (2) and is used for receiving a command of the processing module (2) and a signal of the main controller (11);
the main controller and the auxiliary controller receive commands of the processing module at the same time, the main controller receives the commands and then executes the commands, and the auxiliary controller only takes charge of receiving the commands but does not execute the commands;
if the task is overtime and the signal of the main controller is not received, the auxiliary controller directly executes the command.
7. The control device of an irregular controller according to claim 6, wherein the secondary controller (12) is further configured to determine whether a signal of the primary controller (11) is received:
if the main controller (11) cannot work normally, the auxiliary controller (12) directly executes the command;
if the secondary controller (12) is to directly execute the command more than three times, the secondary controller (12) continues to execute the command and sends a signal to the new secondary controller.
8. The control device of an irregular controller according to claim 7, wherein the control module (1) further comprises a state machine, a configuration mode register and a configuration extension register, and the state machine, the configuration mode register and the configuration extension register are all cleared after the system is initialized; the configuration mode register and the configuration extension register are used for setting and outputting different state machines.
9. An electronic device, comprising:
a memory and one or more processors;
wherein the memory is communicatively coupled to the one or more processors, the memory having stored therein instructions executable by the one or more processors, the instructions, when executed by the one or more processors, for implementing the method of any of claims 1-5.
10. A computer readable storage medium having stored thereon computer executable instructions which, when executed by a computing device, are operable to implement a method as claimed in any one of claims 1 to 5.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202111478123.2A CN114442924B (en) | 2021-12-06 | 2021-12-06 | Control method and device of irregular controller |
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| CN202111478123.2A CN114442924B (en) | 2021-12-06 | 2021-12-06 | Control method and device of irregular controller |
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