CN114429935A - Manufacturing method of metal interconnection structure - Google Patents

Manufacturing method of metal interconnection structure Download PDF

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Publication number
CN114429935A
CN114429935A CN202011183114.6A CN202011183114A CN114429935A CN 114429935 A CN114429935 A CN 114429935A CN 202011183114 A CN202011183114 A CN 202011183114A CN 114429935 A CN114429935 A CN 114429935A
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layer
target
dielectric layer
interlayer dielectric
metal block
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CN202011183114.6A
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赵丹
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SIPLP Microelectronics Chongqing Ltd
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SIPLP Microelectronics Chongqing Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention provides a manufacturing method of a metal interconnection structure, which comprises the following steps: providing a lower interconnection layer and an interlayer dielectric layer positioned on the lower interconnection layer, wherein the interlayer dielectric layer is internally provided with a conductive column and a target; removing the interlayer dielectric layer around the target to form a hole; forming a power supply layer for electroplating on the interlayer dielectric layer, the conductive column and the target; forming a sacrificial layer on the power supply layer for electroplating and at the hole of the hole, and patterning the sacrificial layer to form a plurality of openings; aligning the mask plate used for imaging according to the position of the target; and electroplating metal in the opening to form an upper metal block. According to the embodiment of the invention, when the positions of the mask plate and the target are aligned, the holes enable the power supply layer for electroplating to form the dark ring, the target and the surrounding structure can be distinguished, the interlayer alignment accuracy can be improved, and the product integration level is improved.

Description

Manufacturing method of metal interconnection structure
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a metal interconnection structure.
Background
In recent years, with the continuous development of circuit integration technology, electronic products are increasingly developed toward miniaturization, intellectualization, high integration, high performance and high reliability. The multi-layer metal interconnection structure can improve the product integration level.
When a product needs a multilayer metal interconnection structure, the design specification of the product is limited by the alignment precision between layers. Under the condition of the same electric conduction performance requirement, the higher the interlayer alignment accuracy is, the smaller the cross-sectional area of the conductive column for interlayer conduction can be made, and the lower the interlayer alignment accuracy is, the larger the cross-sectional area of the conductive column must be made, which is not beneficial to improving the integration level of the product.
In view of the above, it is necessary to provide a new method for fabricating a metal interconnection structure to improve the interlayer alignment accuracy and thus improve the product integration.
Disclosure of Invention
The invention aims to provide a manufacturing method of a metal interconnection structure, which is used for improving the interlayer alignment precision and further improving the product integration level.
In order to achieve the above object, the present invention provides a method for manufacturing a metal interconnection structure, including:
providing a lower interconnection layer and an interlayer dielectric layer positioned on the lower interconnection layer, wherein the interlayer dielectric layer is internally provided with a conductive post and a target;
removing at least the interlayer dielectric layer around the target to form a hole;
forming a power supply layer for electroplating on the interlayer dielectric layer, the conductive column and the target; forming a sacrificial layer on the power supply layer for electroplating and at the hole of the hole, and patterning the sacrificial layer to form a plurality of openings; the graphically used mask is aligned with reference to the position of the target;
and electroplating metal in the opening to form an upper metal block.
Optionally, the interlayer dielectric layer is an organic insulating layer, and a laser burning method is adopted to remove the interlayer dielectric layer around the target.
Optionally, the material of the organic insulating layer is ABF.
Optionally, the lower interconnection layer includes a first dielectric layer, and a lower metal block and a dummy lower metal block located in the first dielectric layer; and when the interlayer dielectric layer around the target is removed, the first dielectric layer around the pseudo lower-layer metal block bearing the target is also removed.
Optionally, the dummy underlying metal block falls within an orthographic projection of the target on the underlying interconnect layer.
Optionally, the size range of the boundary of the dummy lower metal block from the boundary of the orthographic projection of the target on the lower interconnection layer is: 10-30 μm.
Optionally, in a radial direction of the hole, a size range of an orthographic projection boundary of the target on the lower interconnection layer to an orthographic projection boundary of an interlayer dielectric layer around the target on the lower interconnection layer is: 100-200 μm.
Alternatively, the power supply layer for electroplating is formed by a physical vapor deposition method or a chemical vapor deposition method.
Optionally, the material of the conductive pillar and the target is copper or aluminum.
Optionally, the material of the sacrificial layer is photoresist.
Optionally, the target has a plurality of targets located at respective corners of the lower interconnect layer.
Optionally, the lower interconnection layer is located on the molding compound layer and the front surface of the bare chip, the front surface of the bare chip exposes the bonding pad, and the lower interconnection layer is a rewiring layer.
Optionally, the lower interconnect layer is located on a front side of a plurality of the dies.
The reason why the interlayer alignment precision is low in the related art is analyzed by the inventor: the upper surface of the interlayer dielectric layer, the upper surface of the conductive column and the upper surface of the target are flush, after the power supply layer and the sacrificial layer for electroplating are sequentially formed on the interlayer dielectric layer, the conductive column and the target, and when the sacrificial layer is patterned to form an opening, because the whole surface of the power supply layer for electroplating reflects light, the mask plate for patterning cannot be aligned with the position of the target, the position of the opening deviates from a preset position, and therefore an upper metal block filled in the opening also deviates from the preset position. If the cross-sectional area of the conductive pillar is smaller, the upper layer metal block cannot be electrically connected with the lower layer metal block. To avoid this problem, the cross-sectional area of the conductive post needs to be increased.
Based on the above analysis, the present invention removes the interlayer dielectric layer around the target to form a hole before forming the power supply layer for electroplating. The thickness of the power supply layer for electroplating is thin, the hole cannot be filled, when the sacrificial layer formed on the power supply layer for electroplating and at the hole of the hole is patterned, the patterned mask plate adopts an optical alignment method, the power supply layer for electroplating at the hole is not reflective, and the mask plate can be accurately aligned with the position of a target, so that the opening position can be accurately positioned at a preset position, the upper metal block filled in the opening can also be accurately positioned at the preset position, and the cross-sectional area of the conductive column can be reduced.
Compared with the prior art, the invention has the beneficial effects that: when the positions of the mask plate and the target are aligned, the holes enable the power supply layer for electroplating to form a dark ring, the target and the surrounding structure can be distinguished, and the interlayer alignment accuracy can be improved, so that the product integration level is improved.
Drawings
FIG. 1 is a flow chart of a method of fabricating a metal interconnect structure according to a first embodiment of the present invention;
fig. 2, 3, 6 to 10 are intermediate schematic views corresponding to the flow in fig. 1;
FIGS. 4 and 5 are schematic diagrams of comparative structures;
FIGS. 11 and 12 are schematic intermediate structures corresponding to a method for fabricating a metal interconnect structure according to a second embodiment of the present invention;
FIGS. 13 and 14 are schematic views of comparative structures;
fig. 15 to 17 are schematic intermediate structures corresponding to the method for manufacturing a metal interconnect structure according to the third embodiment of the present invention.
To facilitate an understanding of the invention, all reference numerals appearing in the invention are listed below:
lower interconnect layer 21 first dielectric layer 211
Lower metal block 212 pseudo lower metal block 213
Interlayer dielectric layer 22 conductive pillar 221
Target 222 bare chip 11
Front side 11a of the die and back side 11b of the die
Pad 111 plastic packaging layer 12
Back side of plastic encapsulation layer 12b front side of plastic encapsulation layer 12a
Power supply layer 23 for plating hole 22a
Opening 24a of sacrificial layer 24
Upper metal block 25 support plate 2
Mask 3
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
FIG. 1 is a flow chart of a method of fabricating a metal interconnect structure according to a first embodiment of the present invention; fig. 2, 3, 6 to 10 are intermediate schematic views corresponding to the flow in fig. 1. Fig. 4 and 5 are schematic diagrams of comparative structures.
First, referring to step S1 in fig. 1 and fig. 2, a lower interconnection layer 21 and an interlayer dielectric layer 22 on the lower interconnection layer 21 are provided, wherein the interlayer dielectric layer 22 has the conductive pillars 221 and the targets 222 therein.
In this embodiment, referring to fig. 2, the lower interconnection layer 21 is located on the molding compound layer 12 and the front surface 11a of the die 11, and the pad 111 is exposed on the front surface 11a of the die 11. In other words, the lower interconnect Layer 21 is a Redistribution Layer (RDL).
The lower interconnection layer 21 includes a first dielectric layer 211, and a lower metal block 212 and a dummy lower metal block 213 located in the first dielectric layer 211.
The lower metal block 212 is selectively connected to the plurality of pads 111 to realize a circuit layout of the pads 111. The dummy lower metal blocks 213 are located at the same level as the lower metal blocks 212, but without electrical connection design requirements.
In this embodiment, the first dielectric layer 211 and the interlayer dielectric layer 22 are made of the same material, and are both ABF (Ajinomoto build file). Specifically, the lower metal block 212, the dummy lower metal block 213, the conductive pillar 221 and the target 222 may be formed on the molding layer 12 and the front surface 11a of the die 11 sequentially by an electroplating process; then, an ABF dry film is pasted on the conductive pillar 221, the target 222, the lower metal block 212, the dummy lower metal block 213, and the surfaces of the plastic package layer 12 exposed by the lower metal block 212 and the dummy lower metal block 213; the ABF dry film is polished until the conductive pillar 221 and the target 222 are exposed. The ABF dry film is a photosensitive material.
In other embodiments, the materials of the first dielectric layer 211 and the interlayer dielectric layer 22 may also be polyimide, epoxy resin, PBO (Polybenzoxazole), organic polymer film, organic polymer composite, or other organic materials with similar insulating properties.
In some embodiments, the material of the first dielectric layer 211 and the interlayer dielectric layer 22 may also be an inorganic insulating material such as silicon dioxide or silicon nitride.
In some embodiments, the materials of the first dielectric layer 211 and the interlayer dielectric layer 22 may be different.
In some embodiments, the first dielectric layer 211 is formed in a different process than the interlevel dielectric layer 22.
The material of the lower metal block 212 and the dummy lower metal block 213 is a conductive metal such as copper or aluminum.
The conductive pillars 221 are located on the lower metal blocks 212, and are used for selectively connecting with the lower metal blocks 212.
Because the dummy underlying metal block 213 has no electrical connection design requirements, the carried target 222 also has no electrical connection design requirements, and only performs an alignment function. The targets 222 are preferably provided in plural numbers at respective corners of the lower interconnection layer 21.
In this embodiment, referring to fig. 2, the orthographic projection of the target 222 on the lower interconnect layer 21 falls within the dummy lower metal block 213.
The die 11 may be formed for dicing a wafer. The wafer includes a wafer front side provided with a pad 111 and an insulating layer (not shown) protecting the pad 111, and a wafer back side. After the wafer dicing, a die 11 is formed, and accordingly, the die 11 includes a front surface 11a and a back surface 11b, and the front surface 11a is provided with a bonding pad 111 and an insulating layer electrically insulating the adjacent bonding pad 111.
The wafer may be thinned from the back side prior to dicing to reduce the thickness of the die 11.
The material of the molding layer 12 may be epoxy resin, polyimide resin, benzocyclobutene resin, polybenzoxazole resin, polybutylene terephthalate, polycarbonate, polyethylene terephthalate, polyethylene, polypropylene, polyolefin, polyurethane, polyolefin, polyethersulfone, polyamide, polyurethane, ethylene-vinyl acetate copolymer, polyvinyl alcohol, or the like. The material of the molding layer 12 may also be various polymers or a composite material of resin and polymer.
The molding layer 12 may include a front surface 12a and a back surface 12b opposite to each other.
In this embodiment, the back surface 12b of the plastic package layer 12 is flush with the front surface 11a of the bare chip 11, and the front surface 12a of the plastic package layer 12 may be provided with the support plate 2 to support the plastic package structure of the bare chip 11 in the subsequent process.
The support plate 2 is a rigid plate and may comprise a plastic plate, a glass plate, a ceramic plate, a metal plate, or the like.
An adhesive layer may be disposed between the front surface 12a of the molding layer 12 and the support plate 2, so as to fix the two.
The adhesive layer may be made of a material that is easily peeled off to peel off the support plate 2, and for example, a thermal release material that can be made to lose adhesiveness by heating or a UV release material that can be made to lose adhesiveness by ultraviolet irradiation may be used.
In some embodiments, the lower interconnect layer 21 may be located on a semiconductor substrate. A semiconductor substrate, such as a silicon substrate, has several devices, such as transistors, formed therein. In other words, the lower interconnect layer 21 is a metal interconnect structure in the die 11, and is not used for a package structure.
Next, referring to step S2 in fig. 1 and fig. 3, at least the interlayer dielectric layer 22 around the target 222 is removed to form the hole 22 a.
When the material of the interlayer dielectric layer 22 is an organic high molecular polymer insulating material, the removal is performed by a laser burning method.
When the material of the interlayer dielectric layer 22 is an inorganic insulating material, the removal is performed by dry etching or wet etching.
In this embodiment, since the materials of the first dielectric layer 211 and the interlayer dielectric layer 22 are the same, when the interlayer dielectric layer 22 is removed, the first dielectric layer 211 around the dummy lower metal block 213 is also removed, so as to increase the depth of the hole 22 a.
In some embodiments, when the material of the first dielectric layer 211 is different from that of the interlayer dielectric layer 22, only the interlayer dielectric layer 22 around the target 222 may be removed.
In the radial direction of the hole 22a, the size D1 of the orthographic projection boundary of the target 222 on the lower interconnection layer 21 from the orthographic projection boundary of the interlayer dielectric layer 22 on the lower interconnection layer 21 around the target 222 may be in the range of: 100-200 μm. This is because:
referring to fig. 4, if the range of the dimension D1 is too large, the removal amount of the interlayer dielectric layer 22 and the first dielectric layer 211 is too large, and the interlayer dielectric layer 22/the first dielectric layer 211 may remain around the target 222 and/or the dummy lower metal block 213 due to insufficient laser energy or insufficient etching time.
Referring to fig. 5, if the range of dimension D1 is too small, misalignment of the reticle used to form the hole 22a may cause the target 222 and/or the dummy underlying metal block 213 to stick to the surrounding interlayer dielectric layer 22/first dielectric layer 211.
Thereafter, referring to step S3 in fig. 1 and fig. 6, the power supply layer 23 for electroplating is formed on the interlayer dielectric layer 22, the conductive pillar 221, and the target 222; referring to fig. 7 and 8, a sacrificial layer 24 is formed on the plating power supply layer 23 and at the opening of the hole 22a, and the sacrificial layer 24 is patterned to form a plurality of openings 24 a; the patterned reticle 3 is aligned with reference to the position of the target 222.
The step S3 may include the following steps S31 to S34.
Step S31: the plating power supply layer 23 is formed.
In step S31, referring to fig. 6, the material of the power supply layer 23 for electroplating may be copper or aluminum, and may be formed by a physical vapor deposition method or a chemical vapor deposition method. The plating power supply layer 23 is thin and thus formed on the bottom wall and/or the side wall of the hole 22a during deposition, but does not fill the hole 22 a.
Step S32: a sacrificial layer 24 is formed.
In this embodiment, referring to fig. 7, the material of the sacrificial layer 24 may be a photoresist layer. In one alternative, the photoresist layer formed may be a photosensitive film. The photosensitive film can be peeled off from the tape and applied to the plating power supply layer 23 and the opening of the hole 22 a. In other alternatives, the photoresist layer may be formed by first applying a liquid photoresist and then curing the liquid photoresist by heating.
In some embodiments, the material of the sacrificial layer 24 may be an inorganic insulating material such as silicon nitride, silicon dioxide, or the like. At this time, a photoresist layer is formed on the sacrificial layer 24. In one alternative, the photoresist layer formed may be a photosensitive film.
Step S33: with continued reference to fig. 7, reticle 3 of patterned sacrificial layer 24 is aligned with reference to the position of target 222.
Because the hole 22a has a height difference between the inside and the outside, and the hole 22a is not filled with the plating power supply layer 23, when the mask 3 is optically aligned, the plating power supply layer 23 in the hole 22a is not reflective, a dark ring can be formed, and the target 222 and the surrounding structure can be distinguished. In this way, the reticle 3 can be accurately aligned with the position of the target 222. The deeper the depth of the hole 22a, the darker the dark ring color.
Referring to fig. 4, if the range of the dimension D1 is too large, the interlayer dielectric layer 22/the first dielectric layer 211 may remain around the target 222 and/or the dummy underlying metal block 213, and when the reticle 3 is optically aligned, the remaining interlayer dielectric layer 22/the first dielectric layer 211 may reflect light, which affects the position recognition of the target 222.
Referring to fig. 5, if the range of the dimension D1 is too small, the target 222 and/or the dummy lower metal block 213 may adhere to the surrounding interlayer dielectric layer 22/first dielectric layer 211, and the power supply layer 23 for electroplating is not broken, and there is no dark ring at the non-broken position, which may affect the position recognition of the target 222.
Step S34: referring to fig. 8, the photoresist layer is exposed and developed to form a patterned photoresist layer.
When the sacrificial layer 24 is made of an inorganic insulating material such as silicon nitride or silicon dioxide, the opening 24a is formed by etching the sacrificial layer 24 using the patterned photoresist layer as a mask.
Since the reticle 3 used for patterning the sacrificial layer 24 can be precisely aligned with the position of the target 222, the position of the opening 24a can be precisely located at a predetermined position.
Next, referring to step S4 in fig. 1 and fig. 9, the upper metal block 25 is formed by electroplating metal in the opening 24 a.
The electroplating may comprise electrolytic plating or electroless plating. In the electrolytic plating, a member to be plated is used as a cathode, and an electrolytic solution is electrolyzed to form a layer of metal on the member to be plated. Electroless plating is a method of forming a metal layer by reducing and precipitating metal ions in a solution on an article to be plated.
The material of the metal to be plated may be copper or aluminum, etc.
After the electroplating, the upper metal block 25 may be polished by a polishing process, such as chemical mechanical polishing.
Referring to fig. 10, after electroplating, the sacrificial layer 24 may be removed.
When the material of the sacrificial layer 24 is a photoresist layer, an ashing method is used for removal.
When the material of the sacrificial layer 24 is an inorganic insulating material such as silicon nitride, silicon dioxide, etc., the material is removed by wet etching using an etching solution. For example, silicon nitride is removed with hot phosphoric acid and silicon dioxide is removed with hydrofluoric acid.
With continued reference to fig. 10, after the removal of the sacrifice layer 24, the exposed plating power supply layer 23 may be removed by dry etching or wet etching.
Thereafter, the support plate 2 may be removed. The support plate 2 may be removed by conventional methods such as laser lift-off and UV irradiation.
Fig. 11 and fig. 12 are intermediate structural diagrams corresponding to a method for manufacturing a metal interconnection structure according to a second embodiment of the invention. Fig. 13 and 14 are schematic diagrams of comparative structures. Referring to fig. 11 and 12, the method for fabricating the metal interconnect structure in this embodiment is substantially the same as the method for fabricating the metal interconnect structure in the first embodiment shown in fig. 1, except that: in step S1, of the provided lower interconnect layer 21 and the target 222, the dummy lower metal block 213 falls within the orthographic projection of the target 222 on the lower interconnect layer 21. Has the advantages that: referring to fig. 13, when the first dielectric layer 211 and the interlayer dielectric layer 22 need to be removed simultaneously to form the deeper hole 22a, the situation that the dummy lower layer metal block 213 is exposed after the interlayer dielectric layer 22 is removed and the first dielectric layer 211 cannot be removed does not occur.
Referring to fig. 12, the boundary of the dummy lower metal block 213 preferably ranges from the dimension D2 of the boundary of the orthographic projection of the target 222 on the lower interconnect layer 21: 10-30 μm. This is because:
if the range of dimension D2 is too small, the problem of fig. 13 may occur when the target 222 and the dummy underlying metal block 213 are misaligned;
if the range of the dimension D2 is too large, referring to fig. 14, the first dielectric layer 211 around the dummy lower metal block 213 is blocked by the target 222, the first dielectric layer 211 remains around the dummy lower metal block 213, and when the reticle 3 is optically aligned, the remaining first dielectric layer 211 reflects light, which affects the position recognition of the target 222.
Fig. 15 to 17 are intermediate structural diagrams corresponding to a method for manufacturing a metal interconnection structure according to a third embodiment of the present invention, wherein fig. 16 is a cross-sectional view along line AA in fig. 15. Referring to fig. 15 to 17, the method for fabricating the metal interconnect structure in this embodiment is substantially the same as the method for fabricating the metal interconnect structure in the first and second embodiments, except that: in step S1, the lower interconnection layer 21 is provided on the molding layer 12 and the front surfaces 11a of the dies 11.
It is understood that fabricating the redistribution layer for a plurality of dies 11 in the same process can improve the fabrication efficiency compared to fabricating the redistribution layer separately for each die 11.
Referring to fig. 17, after the structure of the back surface 12b of the molding compound layer is manufactured, the structure may be cut along the cutting lines to form a plurality of chip package structures.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (11)

1. A method for manufacturing a metal interconnection structure is characterized by comprising the following steps:
providing a lower interconnection layer and an interlayer dielectric layer positioned on the lower interconnection layer, wherein the interlayer dielectric layer is internally provided with a conductive post and a target;
removing at least the interlayer dielectric layer around the target to form a hole;
forming a power supply layer for electroplating on the interlayer dielectric layer, the conductive column and the target; forming a sacrificial layer on the power supply layer for electroplating and at the hole of the hole, and patterning the sacrificial layer to form a plurality of openings; the graphically used mask is aligned with reference to the position of the target;
and electroplating metal in the opening to form an upper metal block.
2. The method for manufacturing a metal interconnection structure according to claim 1, wherein the interlayer dielectric layer is an organic insulating layer, and a laser firing method is adopted to remove the interlayer dielectric layer around the target.
3. The method for manufacturing a metal interconnection structure, according to claim 2, wherein the material of the organic insulating layer is ABF.
4. The method of claim 1, wherein the lower interconnect layer comprises a first dielectric layer, and a lower metal block and a dummy lower metal block located in the first dielectric layer; and when the interlayer dielectric layer around the target is removed, the first dielectric layer around the pseudo lower-layer metal block bearing the target is also removed.
5. The method of claim 4, wherein the dummy underlying metal block falls within an orthographic projection of the target on the underlying interconnect layer.
6. The method of claim 5, wherein the boundary of the dummy lower metal block is within a size range from a boundary of an orthographic projection of the target on the lower interconnect layer: 10-30 μm.
7. The method of claim 1, wherein in a radial direction of the hole, a size range of an orthographic projection boundary of the target on the lower interconnection layer from an orthographic projection boundary of an interlayer dielectric layer around the target on the lower interconnection layer is as follows: 100-200 μm.
8. The method for fabricating a metal interconnect structure according to claim 1, wherein the material of the conductive pillars and the target is copper or aluminum; and/or the material of the sacrificial layer is photoresist.
9. The method of claim 1, wherein the targets are located at corners of the lower interconnect layer.
10. The method of claim 1, wherein the lower interconnect layer is on the molding compound layer and a front surface of the die, the front surface of the die exposes the bonding pads, and the lower interconnect layer is a redistribution layer.
11. The method of claim 10, wherein the lower interconnect layer is on a front side of the plurality of dies.
CN202011183114.6A 2020-10-29 2020-10-29 Manufacturing method of metal interconnection structure Pending CN114429935A (en)

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