CN114429746A - Display device and electronic apparatus - Google Patents
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- CN114429746A CN114429746A CN202210054107.9A CN202210054107A CN114429746A CN 114429746 A CN114429746 A CN 114429746A CN 202210054107 A CN202210054107 A CN 202210054107A CN 114429746 A CN114429746 A CN 114429746A
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- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
- G09G3/2096—Details of the interface to the display terminal specific for a flat panel
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Abstract
The application discloses display device and electronic equipment, this display device includes time schedule controller, display panel and first interface expander circuit, through an input/output interface at time schedule controller connects a first interface expander circuit, can be with an initial logic control signal respectively through the first output of first interface expander circuit, the second output divide into two tunnel outputs to display panel, can provide two tunnel logic control signals for display panel, that is to say, an input/output interface of time schedule controller can divide an initial logic control signal into two different logic control signals through first interface expander circuit, and provide to display panel, time schedule controller can satisfy the different display demands of display panel with less quantity of input/output interface.
Description
Technical Field
The application relates to the technical field of display, in particular to a display device and electronic equipment.
Background
In the related display technology, the input/output interface of the timing controller directly outputs the corresponding logic control signal to the display panel to meet the normal display requirement of the display panel. As various display specifications have evolved, the types and/or numbers of logic control signals required have increased. However, one input/output interface of the timing controller can only provide one logic control signal, that is, each time one logic control signal is added, one input/output interface of the timing controller is correspondingly required to be added.
However, since the number of input/output interfaces that can be carried by the timing controller itself is limited, it is necessary to provide a display device having an interface expansion function.
It should be noted that the above description of the background art is only for the convenience of clear and complete understanding of the technical solutions of the present application. The technical solutions referred to above are therefore not considered to be known to the person skilled in the art, merely because they appear in the background of the present application.
Disclosure of Invention
The application provides a display device and an electronic device, which are used for relieving the technical problem of less input and output interfaces.
In a first aspect, the present application provides a display device, which includes a timing controller, a display panel, and a first interface expansion circuit, wherein a first input/output interface of the timing controller is used for transmitting an initial logic control signal; the first trigger end of the first interface expansion circuit is electrically connected with the first input/output interface of the time schedule controller, the first output end of the first interface expansion circuit is electrically connected with the display panel, and the second output end of the first interface expansion circuit is electrically connected with the display panel.
In some embodiments, the first interface extension circuit includes a first trigger circuit, a first level shift circuit, and a first potential determination circuit, where a trigger end of the first trigger circuit serves as a first trigger end of the first interface extension circuit, and an output end of the first trigger circuit serves as a first output end of the first interface extension circuit; the input end of the first level conversion circuit is electrically connected with the output end of the first trigger circuit; the control end of the first potential determining circuit is electrically connected with the output end of the first level conversion circuit, and the output end of the first potential determining circuit is electrically connected with the output end of the first level conversion circuit and serves as the second output end of the first interface expansion circuit.
In some embodiments, the first output terminal of the first interface expansion circuit is configured to output a first logic control signal, the first logic control signal has a first potential and a second potential, and the first potential is higher than the second potential; the second output end of the first interface expansion circuit is used for outputting a second logic control signal, the second logic control signal has a third potential and a fourth potential, and the third potential is higher than the fourth potential; and the third potential is different from the first potential.
In some of these embodiments, the phase of the first logic control signal is the same as the phase of the second logic control signal.
In some embodiments, the display device further includes a second interface expansion circuit, a second trigger of the second interface expansion circuit is electrically connected to the first input/output interface of the timing controller, a third output of the second interface expansion circuit is electrically connected to the display panel, a fourth output of the second interface expansion circuit is electrically connected to the display panel, and a fifth output of the second interface expansion circuit is electrically connected to the display panel.
In some embodiments, the second interface expansion circuit includes a second trigger circuit, a phase adjustment circuit, a second level shift circuit, and a second potential determination circuit, where a trigger end of the second trigger circuit serves as a second trigger end of the second interface expansion circuit, and an output end of the second trigger circuit serves as a third output end of the second interface expansion circuit; the trigger end of the phase adjusting circuit is electrically connected with the trigger end of the second trigger circuit, the input end of the phase adjusting circuit is electrically connected with the output end of the second trigger circuit, and the output end of the phase adjusting circuit is used as the fourth output end of the second interface expansion circuit; the input end of the second level conversion circuit is electrically connected with the output end of the phase adjustment circuit, and the output end of the second level conversion circuit is used as the fifth output end of the second interface expansion circuit; the input end of the second potential determining circuit is electrically connected with the output end of the second level switching circuit, and the output end of the second potential determining circuit is electrically connected with the input end of the second trigger circuit.
In some embodiments, the third output terminal of the second interface expansion circuit is configured to output a third logic control signal, the fourth output terminal of the second interface expansion circuit is configured to output a fourth logic control signal, and the fifth output terminal of the second interface expansion circuit is configured to output a fifth logic control signal; the phase of the third logic control signal is different from that of the fourth logic control signal, and the pulse amplitude of the third logic control signal is the same as that of the fourth logic control signal; the phase of the fourth logic control signal is the same as the phase of the fifth logic control signal, and the pulse amplitude of the fourth logic control signal is different from the pulse amplitude of the fifth logic control signal.
In some embodiments, the second interface expansion circuit includes a second trigger circuit, a phase adjustment circuit, a second level shift circuit, and a second potential determination circuit, where a trigger end of the second trigger circuit serves as a second trigger end of the second interface expansion circuit, and an output end of the second trigger circuit serves as a third output end of the second interface expansion circuit; the input end of the second level conversion circuit is electrically connected with the output end of the second trigger circuit, and the output end of the second level conversion circuit is used as the fourth output end of the second interface expansion circuit; the trigger end of the phase adjusting circuit is electrically connected with the trigger end of the second trigger circuit, the input end of the phase adjusting circuit is electrically connected with the output end of the second level conversion circuit, and the output end of the phase adjusting circuit is used as the fifth output end of the second interface expansion circuit; the input end of the second potential determining circuit is electrically connected with the output end of the phase adjusting circuit, and the output end of the second potential determining circuit is electrically connected with the input end of the second trigger circuit.
In some embodiments, the third output terminal of the second interface expansion circuit is configured to output a third logic control signal, the fourth output terminal of the second interface expansion circuit is configured to output a fourth logic control signal, and the fifth output terminal of the second interface expansion circuit is configured to output a fifth logic control signal; the phase of the third logic control signal is the same as that of the fourth logic control signal, and the pulse amplitude of the third logic control signal is different from that of the fourth logic control signal; the phase of the fourth logic control signal is different from the phase of the fifth logic control signal, and the pulse amplitude of the fourth logic control signal is the same as the pulse amplitude of the fifth logic control signal.
In a second aspect, the present application provides an electronic device including the display device in at least one of the above embodiments.
The application provides a display device and electronic equipment, through an input/output interface at time schedule controller connects a first interface expander circuit, can divide an initial logic control signal into two routes through the first output of first interface expander circuit respectively, the second output is exported to display panel, can provide two routes logic control signal for display panel, that is to say, an input/output interface of time schedule controller can divide an initial logic control signal into two routes different logic control signal through first interface expander circuit, and provide to display panel, time schedule controller can satisfy display panel's different demonstration demands with less quantity's input/output interface.
Drawings
The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a schematic view of a first structure of a display device according to an embodiment of the present disclosure.
Fig. 2 is a schematic view of a second structure of a display device according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In view of the technical problem of the display device with a small number of input/output interfaces, the present embodiment provides a display device, as shown in fig. 1 and fig. 2, which includes a timing controller 100, a display panel 200, and a first interface expansion circuit 300, wherein a first input/output interface of the timing controller 100 is used for transmitting an initial logic control signal; the first trigger terminal of the first interface expansion circuit 300 is electrically connected to the first input/output interface of the timing controller 100, the first output terminal a1 of the first interface expansion circuit 300 is electrically connected to the display panel 200, and the second output terminal a2 of the first interface expansion circuit 300 is electrically connected to the display panel 200.
It can be understood that, in the display apparatus provided in this embodiment, an input/output interface of the timing controller 100 is connected to a first interface expansion circuit 300, and an initial logic control signal can be divided into two paths through a first output terminal a1 and a second output terminal a2 of the first interface expansion circuit 300 and output to the display panel 200, so as to provide two paths of logic control signals for the display panel 200, that is, an input/output interface of the timing controller 100 can divide an initial logic control signal into two paths of different logic control signals through the first interface expansion circuit 300 and provide the two paths of different logic control signals to the display panel 200, and the timing controller 100 can meet different display requirements of the display panel 200 with a smaller number of input/output interfaces.
It should be noted that the timing controller 100 may further include a second input/output interface, a third input/output interface, a fourth input/output interface, and the like, and the number of the input/output interfaces is not particularly limited herein.
The initial logic control signal may be a clock signal, and the clock signal may be a square wave signal or a pulse signal.
In one embodiment, as shown in fig. 1 or fig. 2, the first interface expansion circuit 300 includes a first trigger circuit 310, a first level shifter circuit 320, and a first potential determining circuit 330, where a trigger terminal of the first trigger circuit 310 serves as a first trigger terminal of the first interface expansion circuit 300, and an output terminal of the first trigger circuit 310 serves as a first output terminal a1 of the first interface expansion circuit 300; the input terminal of the first level shifter 320 is electrically connected to the output terminal of the first trigger circuit 310; the control terminal of the first potential determining circuit 330 is electrically connected to the output terminal of the first level shifter 320, and the output terminal of the first potential determining circuit 330 is electrically connected to the output terminal of the first level shifter 320 and serves as the second output terminal a2 of the first interface expansion circuit 300.
It should be noted that the first trigger circuit 310 may output the potential output by the first potential determining circuit 330 according to the rising edge of the initial logic control signal. The first level shifter 320 can shift the voltage outputted from the first trigger 310 to a higher voltage or a lower voltage, which can be flexibly set according to the requirement.
In one embodiment, the first flip-flop circuit 310 may include a first flip-flop D1, a trigger terminal of the first flip-flop D1 is electrically connected to the first input/output interface of the timing controller 100, an input terminal of the first flip-flop D1 is electrically connected to the output terminal of the first potential determining circuit 330, and an output terminal of the first flip-flop D1 is electrically connected to the input terminal of the first level shifter 320.
The first flip-flop D1 may be a D flip-flop.
In one embodiment, the first trigger circuit 310 may further include a first resistor R1, one end of the first resistor R1 is electrically connected to the output terminal of the first flip-flop D1, and the other end of the first resistor R1 is grounded. It should be noted that the first resistor R1 may be used to initialize the output terminal of the first trigger circuit 310 to a low voltage.
In one embodiment, the first potential determining circuit 330 may include a first transistor M1 and a second transistor M2, one of the source/drain of the first transistor M1 is connected to the first voltage signal VDD1, the other of the source/drain of the first transistor M1 is electrically connected to one of the source/drain of the second transistor M2, the other of the source/drain of the second transistor M2 is grounded, and the gate of the first transistor M1 is electrically connected to the gate of the second transistor M2 and the output terminal of the first level shifter 320.
Both the first transistor M1 and the second transistor M2 may be field effect transistors, specifically, the first transistor M1 may also be a P-channel field effect transistor, and the second transistor M2 may also be an N-channel field effect transistor.
In one embodiment, the potential of the first voltage signal VDD1 may be the same as the pulse amplitude of the initial logic control signal, so that the first logic control signal and the initial logic control signal are guaranteed to be the same.
In one embodiment, the first output terminal a1 of the first interface expansion circuit 300 is used for outputting a first logic control signal, the first logic control signal has a first potential and a second potential, and the first potential is higher than the second potential; the second output terminal a2 of the first interface expansion circuit 300 is used for outputting a second logic control signal, where the second logic control signal has a third potential and a fourth potential, and the third potential is higher than the fourth potential; and the third potential is different from the first potential.
It is understood that, in this embodiment, the first potential and the third potential may be pulse amplitudes of the corresponding logic control signals, respectively. The third potential can be higher than the first potential, or the first potential can also be higher than the third potential, and can be flexibly set as required.
In one embodiment, the phase of the first logic control signal is the same as the phase of the second logic control signal.
In one embodiment, as shown in fig. 1 or fig. 2, the display device further includes a second interface expansion circuit 400, the second trigger terminal of the second interface expansion circuit 400 is electrically connected to the first input/output interface of the timing controller 100, the third output terminal B1 of the second interface expansion circuit 400 is electrically connected to the display panel 200, the fourth output terminal B2 of the second interface expansion circuit 400 is electrically connected to the display panel 200, and the fifth output terminal B3 of the second interface expansion circuit 400 is electrically connected to the display panel 200.
It is understood that, in the present embodiment, one input/output interface of the timing controller 100 may be extended to three, and the number of interfaces of the timing controller 100 may be further increased.
In one embodiment, as shown in fig. 1, the second interface expansion circuit 400 includes a second trigger circuit 410, a phase adjustment circuit 420, a second level shift circuit 430, and a second potential determination circuit 440, wherein a trigger terminal of the second trigger circuit 410 serves as a second trigger terminal of the second interface expansion circuit 400, and an output terminal of the second trigger circuit 410 serves as a third output terminal B1 of the second interface expansion circuit 400; the trigger end of the phase adjusting circuit 420 is electrically connected to the trigger end of the second trigger circuit 410, the input end of the phase adjusting circuit 420 is electrically connected to the output end of the second trigger circuit 410, and the output end of the phase adjusting circuit 420 serves as the fourth output end B2 of the second interface expansion circuit 400; the input end of the second level shifter 430 is electrically connected to the output end of the phase adjustment circuit 420, and the output end of the second level shifter 430 is used as the fifth output end B3 of the second interface expansion circuit 400; an input terminal of the second potential determining circuit 440 is electrically connected to an output terminal of the second level shifter circuit 430, and an output terminal of the second potential determining circuit 440 is electrically connected to an input terminal of the second trigger circuit 410.
In one embodiment, the second flip-flop circuit 410 may include a second flip-flop D2, a trigger terminal of the second flip-flop D2 is electrically connected to the first input/output interface of the timing controller 100, an input terminal of the second flip-flop D2 is electrically connected to the output terminal of the second potential determining circuit 440, and an output terminal of the second flip-flop D2 is electrically connected to the input terminal of the second level shifter 430.
The second flip-flop D2 may also be a D flip-flop.
In one embodiment, the second flip-flop circuit 410 may further include a second resistor R2, one end of the second resistor R2 is electrically connected to the output terminal of the second flip-flop D2, and the other end of the second resistor R2 is grounded. It should be noted that the second resistor R2 can be used to initialize the output terminal of the second flip-flop circuit 410 to a low voltage.
In one embodiment, the phase adjustment circuit 420 may include a third flip-flop D3, a trigger terminal of the third flip-flop D3 is electrically connected to the first input/output interface of the timing controller 100, an input terminal of the third flip-flop D3 is electrically connected to an output terminal of the second flip-flop D2, and an output terminal of the third flip-flop D3 is electrically connected to an input terminal of the second level shifter 430.
It is understood that the phase adjustment circuit 420 may perform a corresponding delay on the signal output by the second flip-flop D2 to achieve the phase adjustment thereof.
The third flip-flop D3 may be a D flip-flop.
In one embodiment, the phase adjustment circuit 420 may further include a third resistor R3, one end of the third resistor R3 is electrically connected to the output terminal of the third flip-flop D3, and the other end of the third resistor R3 is grounded. It should be noted that the third resistor R3 can be used to initialize the output terminal of the third flip-flop circuit to a low voltage.
In one embodiment, the second potential determining circuit 440 may include a third transistor M3 and a fourth transistor M4, one of the source/drain of the third transistor M3 is connected to the second voltage signal VDD2, the other of the source/drain of the third transistor M3 is electrically connected to one of the source/drain of the fourth transistor M4, the other of the source/drain of the fourth transistor M4 is grounded, and the gate of the third transistor M3 is electrically connected to the gate of the fourth transistor M4 and the output terminal of the second level shifter circuit 430.
The third transistor M3 and the fourth transistor M4 may be field effect transistors, specifically, the third transistor M3 may also be a P-channel field effect transistor, and the fourth transistor M4 may also be an N-channel field effect transistor.
The first voltage signal VDD1 and the second voltage signal VDD2 are both constant voltage signals, and the potential of the first voltage signal VDD1 is different from the potential of the second voltage signal VDD 2.
In one embodiment, the third output terminal B1 of the second interface expansion circuit 400 is used for outputting a third logic control signal, the fourth output terminal B2 of the second interface expansion circuit 400 is used for outputting a fourth logic control signal, and the fifth output terminal B3 of the second interface expansion circuit 400 is used for outputting a fifth logic control signal; the phase of the third logic control signal is different from that of the fourth logic control signal, and the pulse amplitude of the third logic control signal is the same as that of the fourth logic control signal; the phase of the fourth logic control signal is the same as the phase of the fifth logic control signal, and the pulse amplitude of the fourth logic control signal is different from the pulse amplitude of the fifth logic control signal.
It can be understood that the third logic control signal, the fourth logic control signal and the fifth logic control signal provided in this embodiment are different from each other, and can satisfy more display requirements of the display panel 200.
In one embodiment, as shown in fig. 2, the second interface expansion circuit 400 includes a second trigger circuit 410, a phase adjustment circuit 420, a second level shift circuit 430, and a second potential determination circuit 440, wherein a trigger terminal of the second trigger circuit 410 serves as a second trigger terminal of the second interface expansion circuit 400, and an output terminal of the second trigger circuit 410 serves as a third output terminal B1 of the second interface expansion circuit 400; the input end of the second level shifter circuit 430 is electrically connected to the output end of the second trigger circuit 410, and the output end of the second level shifter circuit 430 is used as the fourth output end B2 of the second interface expansion circuit 400; the trigger end of the phase adjusting circuit 420 is electrically connected to the trigger end of the second trigger circuit 410, the input end of the phase adjusting circuit 420 is electrically connected to the output end of the second level shifter circuit 430, and the output end of the phase adjusting circuit 420 serves as the fifth output end B3 of the second interface expansion circuit 400; an input terminal of the second potential determining circuit 440 is electrically connected to an output terminal of the phase adjusting circuit 420, and an output terminal of the second potential determining circuit 440 is electrically connected to an input terminal of the second triggering circuit 410.
It should be noted that, compared with fig. 1, in the present embodiment, the positions of the phase adjustment circuit 420 and the second level shift circuit 430 are exchanged, and accordingly, some connection relationships are changed, which is not described herein again, and reference may be made to fig. 2 or the aforementioned connection relationships.
In one embodiment, the third output terminal B1 of the second interface expansion circuit 400 is used for outputting a third logic control signal, the fourth output terminal B2 of the second interface expansion circuit 400 is used for outputting a fourth logic control signal, and the fifth output terminal B3 of the second interface expansion circuit 400 is used for outputting a fifth logic control signal; the phase of the third logic control signal is the same as that of the fourth logic control signal, and the pulse amplitude of the third logic control signal is different from that of the fourth logic control signal; the phase of the fourth logic control signal is different from the phase of the fifth logic control signal, and the pulse amplitude of the fourth logic control signal is the same as the pulse amplitude of the fifth logic control signal.
It should be noted that the timing controller 100 in the above embodiment may control a chip in a timing manner, and each input/output interface may be one pin or pin of the chip in the timing manner. It can be understood that the integration degree of the timing control chip is higher, and the area or volume of the display device can be further reduced.
In one embodiment, the present embodiment provides an electronic device, which includes the display device in at least one of the above embodiments.
It can be understood that, in the electronic apparatus provided in this embodiment, an input/output interface of the timing controller 100 is connected to a first interface expansion circuit 300, an initial logic control signal can be divided into two paths through a first output terminal a1 and a second output terminal a2 of the first interface expansion circuit 300 and output to the display panel 200, and two paths of logic control signals can be provided for the display panel 200, that is, an input/output interface of the timing controller 100 can divide an initial logic control signal into two paths of different logic control signals through the first interface expansion circuit 300 and provide the two paths of different logic control signals to the display panel 200, and the timing controller 100 can meet different display requirements of the display panel 200 with a smaller number of input/output interfaces.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The display device and the electronic device provided in the embodiments of the present application are described in detail above, and specific examples are applied in the description to explain the principle and the implementation of the present application, and the description of the embodiments above is only used to help understanding the technical solutions and the core ideas of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.
Claims (10)
1. A display device, comprising:
the first input/output interface of the time schedule controller is used for transmitting an initial logic control signal;
a display panel; and
the first interface expansion circuit comprises a first triggering end and a first input/output interface which are electrically connected with the time schedule controller, a first output end and a second output end, wherein the first output end of the first interface expansion circuit is electrically connected with the display panel, and the second output end of the first interface expansion circuit is electrically connected with the display panel.
2. The display device according to claim 1, wherein the first interface expansion circuit comprises:
a trigger end of the first trigger circuit is used as a first trigger end of the first interface expansion circuit, and an output end of the first trigger circuit is used as a first output end of the first interface expansion circuit;
the input end of the first level conversion circuit is electrically connected with the output end of the first trigger circuit; and
the control end of the first potential determining circuit is electrically connected with the output end of the first level conversion circuit, and the output end of the first potential determining circuit is electrically connected with the output end of the first level conversion circuit and serves as the second output end of the first interface expansion circuit.
3. The display device according to claim 2, wherein the first output terminal of the first interface expansion circuit is configured to output a first logic control signal, the first logic control signal having a first potential and a second potential, the first potential being higher than the second potential; a second output end of the first interface expansion circuit is used for outputting a second logic control signal, the second logic control signal has a third potential and a fourth potential, and the third potential is higher than the fourth potential; and the third potential is different from the first potential.
4. The display device according to claim 3, wherein a phase of the first logic control signal is the same as a phase of the second logic control signal.
5. The display device according to claim 1, wherein the display device further comprises a second interface expansion circuit, a second trigger terminal of the second interface expansion circuit is electrically connected to the first input/output interface of the timing controller, a third output terminal of the second interface expansion circuit is electrically connected to the display panel, a fourth output terminal of the second interface expansion circuit is electrically connected to the display panel, and a fifth output terminal of the second interface expansion circuit is electrically connected to the display panel.
6. The display device according to claim 5, wherein the second interface expansion circuit comprises:
a trigger end of the second trigger circuit is used as a second trigger end of the second interface expansion circuit, and an output end of the second trigger circuit is used as a third output end of the second interface expansion circuit;
a trigger end of the phase adjusting circuit is electrically connected with a trigger end of the second trigger circuit, an input end of the phase adjusting circuit is electrically connected with an output end of the second trigger circuit, and an output end of the phase adjusting circuit is used as a fourth output end of the second interface expansion circuit;
the input end of the second level conversion circuit is electrically connected with the output end of the phase adjustment circuit, and the output end of the second level conversion circuit is used as the fifth output end of the second interface expansion circuit; and
and the input end of the second potential determining circuit is electrically connected with the output end of the second level switching circuit, and the output end of the second potential determining circuit is electrically connected with the input end of the second trigger circuit.
7. The display device according to claim 6, wherein a third output terminal of the second interface expansion circuit is configured to output a third logic control signal, a fourth output terminal of the second interface expansion circuit is configured to output a fourth logic control signal, and a fifth output terminal of the second interface expansion circuit is configured to output a fifth logic control signal; the phase of the third logic control signal is different from that of the fourth logic control signal, and the pulse amplitude of the third logic control signal is the same as that of the fourth logic control signal; the phase of the fourth logic control signal is the same as the phase of the fifth logic control signal, and the pulse amplitude of the fourth logic control signal is different from the pulse amplitude of the fifth logic control signal.
8. The display device according to claim 5, wherein the second interface expansion circuit comprises:
a trigger end of the second trigger circuit is used as a second trigger end of the second interface expansion circuit, and an output end of the second trigger circuit is used as a third output end of the second interface expansion circuit;
the input end of the second level conversion circuit is electrically connected with the output end of the second trigger circuit, and the output end of the second level conversion circuit is used as the fourth output end of the second interface expansion circuit;
a trigger end of the phase adjusting circuit is electrically connected to a trigger end of the second trigger circuit, an input end of the phase adjusting circuit is electrically connected to an output end of the second level shifter circuit, and an output end of the phase adjusting circuit is used as a fifth output end of the second interface expansion circuit;
and the input end of the second potential determining circuit is electrically connected with the output end of the phase adjusting circuit, and the output end of the second potential determining circuit is electrically connected with the input end of the second trigger circuit.
9. The display device according to claim 8, wherein a third output terminal of the second interface expansion circuit is configured to output a third logic control signal, a fourth output terminal of the second interface expansion circuit is configured to output a fourth logic control signal, and a fifth output terminal of the second interface expansion circuit is configured to output a fifth logic control signal; the phase of the third logic control signal is the same as that of the fourth logic control signal, and the pulse amplitude of the third logic control signal is different from that of the fourth logic control signal; the phase of the fourth logic control signal is different from the phase of the fifth logic control signal, and the pulse amplitude of the fourth logic control signal is the same as the pulse amplitude of the fifth logic control signal.
10. An electronic apparatus characterized by comprising the display device according to any one of claims 1 to 9.
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| CN202210054107.9A CN114429746B (en) | 2022-01-18 | 2022-01-18 | Display device and electronic apparatus |
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| CN202210054107.9A CN114429746B (en) | 2022-01-18 | 2022-01-18 | Display device and electronic apparatus |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN208208297U (en) * | 2018-05-31 | 2018-12-07 | 昆山龙腾光电有限公司 | A kind of Interface Expanding circuit and display device |
| CN109064982A (en) * | 2018-08-06 | 2018-12-21 | 深圳市华星光电技术有限公司 | GOA circuit driving system and GOA circuit drive method and display device |
| CN109166547A (en) * | 2018-09-30 | 2019-01-08 | 惠科股份有限公司 | Driving circuit of display device, display device and display panel |
| CN113178174A (en) * | 2021-03-22 | 2021-07-27 | 重庆惠科金渝光电科技有限公司 | Grid driving module, grid control signal generation method and display device |
| US20210335161A1 (en) * | 2018-11-09 | 2021-10-28 | HKC Corporation Limited | Driving circuit of display apparatus |
-
2022
- 2022-01-18 CN CN202210054107.9A patent/CN114429746B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN208208297U (en) * | 2018-05-31 | 2018-12-07 | 昆山龙腾光电有限公司 | A kind of Interface Expanding circuit and display device |
| CN109064982A (en) * | 2018-08-06 | 2018-12-21 | 深圳市华星光电技术有限公司 | GOA circuit driving system and GOA circuit drive method and display device |
| CN109166547A (en) * | 2018-09-30 | 2019-01-08 | 惠科股份有限公司 | Driving circuit of display device, display device and display panel |
| US20210335161A1 (en) * | 2018-11-09 | 2021-10-28 | HKC Corporation Limited | Driving circuit of display apparatus |
| CN113178174A (en) * | 2021-03-22 | 2021-07-27 | 重庆惠科金渝光电科技有限公司 | Grid driving module, grid control signal generation method and display device |
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| CN114429746B (en) | 2024-03-15 |
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