CN114422305A - Time domain parallel Volterra equalizer facing broadband satellite access, equalization method and terminal - Google Patents

Time domain parallel Volterra equalizer facing broadband satellite access, equalization method and terminal Download PDF

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CN114422305A
CN114422305A CN202111641777.2A CN202111641777A CN114422305A CN 114422305 A CN114422305 A CN 114422305A CN 202111641777 A CN202111641777 A CN 202111641777A CN 114422305 A CN114422305 A CN 114422305A
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register
tap coefficient
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CN114422305B (en
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宫丰奎
张师笑
李果
张南
惠腾飞
许鹏飞
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Xidian University
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B7/00—Radio transmission systems, i.e. using radiation field
    • H04B7/14—Relay systems
    • H04B7/15—Active relay systems
    • H04B7/185—Space-based or airborne stations; Stations for satellite systems
    • H04B7/18578—Satellite systems for providing broadband data service to individual earth stations
    • H04B7/1858—Arrangements for data transmission on the physical system, i.e. for data bit transmission between network components
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0202—Channel estimation
    • H04L25/024—Channel estimation channel estimation algorithms
    • H04L25/025—Channel estimation channel estimation algorithms using least-mean-square [LMS] method
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L2025/03433—Arrangements for removing intersymbol interference characterised by equaliser structure
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
    • H04L25/03006—Arrangements for removing intersymbol interference
    • H04L2025/03433—Arrangements for removing intersymbol interference characterised by equaliser structure
    • H04L2025/03439—Fixed structures
    • H04L2025/03445—Time domain

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Abstract

The invention belongs to the technical field of satellite communication, and discloses a time domain parallel Volterra equalizer, an equalizing method and a terminal for broadband satellite access, which comprise the following steps: shifting and registering input data, outputting the data to a tap coefficient updating module, and caching the data of the current register when the pilot frequency is effective; updating serial tap coefficients according to the cached register data; and delaying the input data register, and filtering according to the updated tap coefficient to obtain equalized output data. The invention realizes the time domain equalizer structure based on the LMS algorithm serial updating tap and parallel filtering, and the tap updating is carried out only when the pilot frequency data arrives; compared with a serial Volterra equalizer, only a data filtering part is changed, and the realization complexity is low and the structure is simple; two paths of parallel balance are realized on the single symbol rate, and the working clock frequency of the module is improved; the tap coefficient is updated in real time through hard decision, the data still works after being converged, and the channel change can be tracked in real time.

Description

Time domain parallel Volterra equalizer facing broadband satellite access, equalization method and terminal
Technical Field
The invention belongs to the technical field of satellite communication, and particularly relates to a time domain parallel Volterra equalizer oriented to broadband satellite access, an equalization method and a terminal.
Background
Currently, in order to realize High-quality wireless communication, High-throughput Satellite (HTS) is rapidly developed with its large transmission bandwidth and High communication capacity.
On the satellite transponder, the signal passes through an Input MultipleXer (IMUX), is amplified by a power amplifier (TWTA), and finally passes through an Output MultipleXer (OMUX). During signal transmission, due to the bandwidth limitation of the IMUX and OMUX filters and the large bandwidth characteristic of high-throughput satellites, severe intersymbol interference (ISI) is experienced, and linear distortion is introduced. While TWTAs operate near the saturation point, they introduce nonlinear distortion. The memory effect caused by the filter in the satellite channel and the nonlinear distortion caused by the power amplifier introduce intersymbol interference and interchannel interference, which requires the receiving end to use the equalization technique to compensate, and reduces and avoids the system transmission performance reduction caused by the deterioration of the channel condition.
The document of "FPGA Implementation of A Channel equalized based on LMS Algorithm" (First International Conference on periodic Computing, Signal Processing and Applications,2010) proposes an 8-tap LMS adaptive equalization FPGA serial Implementation method, which has low Implementation complexity and can resist certain linear and nonlinear distortions, but the supported symbol rate is low, and the application scenario has limitations and cannot be applied to data transmission with large bandwidth and high clock rate in a high-throughput satellite system.
A15-tap volterra equalization FPGA parallel implementation method is provided in a High-speed LMS Equalizer for Spread Spectrum System Based on FPGA, the method realizes volterra equalization of three paths of parallel data, can compensate for non-ideal group delay characteristics and amplitude-frequency characteristics in a channel, and the FPGA implementation only has 0.5dB performance loss compared with simulation. However, the algorithm realized by the realization method is high in complexity, and the single-path clock rate only supports 49.273MHz at most, and still does not meet the requirement of high clock frequency in a high-throughput satellite system.
In summary, the existing volterra equalization FPGA implementation method is limited in clock rate, and cannot solve the problems of high transmission rate and high implementation complexity while supporting high-throughput satellite data equalization. Therefore, it is highly desirable to design a time domain parallel Volterra equalization method with low complexity.
The difficulty in solving the above problems and defects is: high-throughput satellite systems require high transmission bandwidth, that is, to improve the symbol rate supported by the FPGA module, the volterra equalizers need to be implemented in parallel. A common parallelization method is to convert the signal into the frequency domain for processing, which has high implementation complexity.
The significance of solving the problems and the defects is as follows: the FPGA parallel method for realizing the LMS adaptive algorithm in the time domain has low algorithm complexity and uses less FPGA resources; and two paths of parallel realization are carried out, and compared with a serial volterra equalizer, the supported symbol rate is doubled.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides a time domain parallel Volterra equalizer, an equalization method and a terminal for broadband satellite access, and particularly relates to a low-complexity time domain parallel Volterra equalizer, an equalization method and a terminal for broadband satellite access based on an LMS adaptive algorithm.
The invention is realized in such a way, and provides a time domain parallel Volterra equalization method, which comprises the following steps:
firstly, shifting and registering input data, outputting the data to a tap coefficient updating module, and caching the data of a current register when pilot frequency is effective;
updating serial tap coefficients according to the cached register data based on an LMS algorithm;
and step three, delaying the input data register, and performing parallel filtering according to the updated tap coefficient to obtain equalized output data.
The method carries out data processing in a vector form when carrying out data filtering and tap updating, wherein the first step is mainly used for generating and buffering input data vectors, the second step is used for carrying out serial tap coefficient updating and is a core part of the method, and the third step is a data output module for carrying out parallel processing on data.
Further, the step one of shifting and registering the input data and outputting the data to the tap coefficient updating module, and caching the data of the current register when the pilot frequency is valid includes:
(1) sending input data to two parallel shift registers with the length of M +1, and transmitting the input data to a tap coefficient updating module;
(2) and (3) inputting the register data into a pilot frequency cache unit, judging whether the pilot frequency enable is valid, if so, continuing to input the data, and if so, executing the step (2).
Further, the shifting and registering the input data in the first step, and outputting the data to the tap coefficient updating module, where caching the data of the current register when the pilot frequency is valid specifically includes:
simultaneously writing the [ M +1:2] and [ M:1] data in the parallel shift register into a cache RAM, setting a first flag1, and negating a flag1 when pilot frequency enabling is effective;
when the first flag bit flag1 is valid, the read address of the cache RAM is increased, and [ M +1:2] data is read; when the flag bit flag1 is invalid, the [ M:1] data is read, and parallel writing and serial reading are completed.
Further, the serial tap coefficient updating according to the cached register data based on the LMS algorithm in the second step includes:
(1) serially reading out the cached data of the shift register and multiplying the data of the shift register by the data of the current tap register;
(2) carrying out hard decision on the result of multiplication and accumulation in the step (1) to obtain a current error value;
(3) and (2) sending the cached data of the shift register in the step (1) into a delay unit, multiplying the data by the current error value and the step factor, accumulating the data to a tap coefficient register, updating the tap coefficient, outputting the updated tap coefficient to a parallel data filtering module, and executing the step (1) at the same time.
The calculation formula for multiplying the shift register data by the tap register is as follows:
y(n)＝W(n)HX(n)；
the calculation formula of the hard decision is as follows:
e(n)＝d(n)-y(n)；
the tap coefficient updating mode is based on an LMS adaptive algorithm, and the calculation formula is as follows:
W(n+1)＝W(n)+μX(n)e*(n)；
wherein, x (n) is the input signal vector at n time, w (n) is the tap weight vector of the adaptive filter at n time, the length of w (n) is M, and μ is the step factor.
Further, delaying the input data register in the third step, and performing parallel filtering according to the updated tap coefficient to obtain equalized output data includes:
(1) performing serial-parallel conversion on the tap coefficients in the step two, and outputting two paths of parallel tap coefficients;
(2) and (3) delaying the data in the parallel shift register of the step one, and respectively entering the two paths of delayed data and the parallel tap coefficients of the step (1) into two multiplication accumulation modules to obtain two paths of parallel output data.
Further, delaying the input data register in the third step, and performing parallel filtering according to the updated tap coefficient to obtain equalized output data specifically includes:
the serial-parallel conversion module is provided with a second flag bit flag2, and when the effective enabling output by the tap updating module comes, the flag2 is negated; when the second flag bit flag2 is valid, the write address of the cache RAM is increased, and the tap coefficient register is written into the high bit of the write port of the RAM; when the second flag bit flag2 is invalid, the tap coefficient register is written into the RAM write port bit; and reading out the parallel data from the cache RAM, and reading out the address for two times to effectively enable the address to complete serial writing and parallel reading.
The parallel shift register is delayed, and the delay length N is determined by the delay of updating the tap coefficient once; the [ M +1:2] and [ M:1] data in the parallel shift register are multiplied and accumulated by two paths of parallel tap coefficients respectively, and 2M complex multipliers are needed in total.
Another object of the present invention is to provide a time domain parallel Volterra equalizer applying the time domain parallel Volterra equalizing method, wherein the time domain parallel Volterra equalizer includes a tap data updating module and a parallel data filtering module.
The tap data updating module comprises a tap coefficient register, a hard decision device, a delay unit and a pilot frequency buffer unit; the parallel data filtering module comprises a parallel shift register, a delay unit, a serial-parallel conversion module and a multiplication accumulation module;
the parallel shift register is connected with the pilot frequency cache unit, the output data of the parallel shift register is transmitted to the pilot frequency cache unit, and the data of the current register is cached when the pilot frequency is enabled to be effective;
and the tap coefficient register is connected with the serial-parallel conversion module, and the updated tap coefficient enters the serial-parallel conversion module to perform parallel filtering on data.
Wherein the tap data update module comprises:
the tap coefficient register is used for updating the tap coefficient when a new error value comes;
the hard decision device is used for obtaining an error value between the current data and the standard constellation point;
the delay unit is used for delaying the register data when the pilot frequency is effective and multiplying the delayed register data by the error value after hard decision to obtain the numerical value of the tap coefficient needing to be accumulated;
and the pilot frequency buffer unit is used for buffering the shift register when the pilot frequency enable comes.
The parallel data filtering module comprises a parallel shift register, a delay unit, a serial-parallel conversion module and a multiplication accumulation module;
the parallel data filtering module includes:
the parallel shift register is used for inputting two paths of parallel data into a shift register with the length of N, wherein N is the length of a tap coefficient plus 1;
the delay unit is used for delaying the parallel shift register and keeping consistent with the updated tap coefficient;
the serial-parallel conversion module is used for converting the data in the tap coefficient register into two paths of parallel outputs;
and the multiplication and accumulation module is used for multiplying and accumulating the delayed parallel shift register data and the parallel tap coefficients to obtain two paths of parallel output data.
It is a further object of the invention to provide a computer device comprising a memory and a processor, the memory storing a computer program which, when executed by the processor, causes the processor to perform the steps of:
inputting data into a parallel shift register with the length of M +1 for shift register, outputting the data to a tap coefficient updating module, and caching the data of the current register when the pilot frequency is effective; updating serial tap coefficients according to the cached register data based on an LMS algorithm; and delaying the input data register, and performing parallel filtering according to the updated tap coefficient to obtain equalized output data.
It is another object of the present invention to provide a computer-readable storage medium storing a computer program which, when executed by a processor, causes the processor to perform the steps of:
inputting data into a parallel shift register with the length of M +1 for shift register, outputting the data to a tap coefficient updating module, and caching the data of the current register when the pilot frequency is effective; updating serial tap coefficients according to the cached register data based on an LMS algorithm; and delaying the input data register, and performing parallel filtering according to the updated tap coefficient to obtain equalized output data.
Another object of the present invention is to provide an information data processing terminal, wherein the information data processing terminal is configured to implement the time-domain parallel Volterra equalizer.
By combining all the technical schemes, the invention has the advantages and positive effects that: the invention realizes two paths of time domain parallel equalizers on single symbol rate, wherein the symbol rate supported on one path is only half of the original symbol rate, and the symbol rate of the highest 400Msps can be supported. Of the FSW series of spectral and signal analyzers manufactured by rod-schwarz, the most recent analyzer FSW85 supported the highest demodulated symbol rate of 500 Msps. The high-throughput satellite system has the characteristics of large bandwidth and high throughput, so that a transceiving system is required to use higher clock frequency, the traditional serial equalizer is difficult to meet the time sequence requirement under the high clock frequency, and a parallel equalization processing structure is required.
The invention realizes the structure of a time domain equalizer based on LMS algorithm serial updating tap and parallel filtering, and the tap updating is carried out only when pilot frequency (including frame header) data arrives; compared with a serial Volterra equalizer, only a data filtering part is changed, and the serial Volterra equalizer is low in implementation complexity and simple in structure.
The invention realizes two-path parallel equalization on single symbol rate and improves the working clock frequency of the module. The tap coefficient updating module adopts an LMS adaptive algorithm, reads pilot frequency data in the parallel shift register in series, updates the tap coefficient in real time through hard decision, still works after data convergence, and can track channel change in real time. The invention multiplexes the multiplication accumulation module for two times in the parallel data filtering module, realizes two-path parallel processing, only increases the resource consumption of M complex multipliers compared with a serial Volterra equalizer, and has low operation complexity. The equalizer provided by the invention can effectively compensate the nonlinear distortion in the nonlinear channel of the high-flux satellite and improve the working frequency of the module.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments of the present invention will be briefly described below, and it is obvious that the drawings described below are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a flowchart of a time domain parallel Volterra equalization method according to an embodiment of the present invention.
Fig. 2 is a flow chart of the implementation of the two-way parallel time domain equalization according to the present invention.
Fig. 3 is a diagram of an implementation structure of a two-way parallel time domain equalizer FPGA according to an embodiment of the present invention.
Fig. 4 is a structure diagram of an FPGA implementing parallel-to-serial conversion on parallel shift register data according to an embodiment of the present invention.
Fig. 5(a) is a structure diagram of an FPGA implementation of the multiply-accumulate module 1 according to the embodiment of the present invention.
Fig. 5(b) is a structure diagram of an FPGA implementation of the multiply-accumulate module 2 according to the embodiment of the present invention.
Fig. 6(a) is a simulated constellation diagram (QPSK) before time domain equalization according to an embodiment of the present invention.
Fig. 6(b) is a simulated constellation (QPSK) after time domain equalization according to an embodiment of the present invention.
Fig. 7(a) is a simulated constellation (8PSK) before time domain equalization according to an embodiment of the present invention.
Fig. 7(b) is a simulated constellation (8PSK) after time domain equalization according to an embodiment of the present invention.
Fig. 8(a) is a simulated constellation (16APSK) before time domain equalization according to an embodiment of the present invention.
Fig. 8(b) is a simulated constellation (16APSK) after time domain equalization according to an embodiment of the present invention.
Fig. 9 is a diagram illustrating a conventional tap update structure based on an LMS adaptive algorithm according to an embodiment of the present invention.
Fig. 10 is a schematic diagram of wr _ en and rd _ en updates provided by the embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail with reference to the following embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Aiming at the problems in the prior art, the invention provides a time domain parallel Volterra equalizer facing broadband satellite access, an equalization method and a terminal, and the invention is described in detail below with reference to the attached drawings.
As shown in fig. 1, the time domain parallel Volterra equalization method provided by the embodiment of the present invention includes the following steps:
s101, shifting and registering input data, outputting the data to a tap coefficient updating module, and caching data of a current register when pilot frequency is effective;
s102, updating serial tap coefficients according to the cached register data based on an LMS algorithm;
and S103, delaying the input data register, and performing parallel filtering according to the updated tap coefficient to obtain equalized output data.
The technical solution of the present invention is further described below with reference to specific examples.
Example 1
The channel in the high-throughput satellite communication system is often a nonlinear channel, and the nonlinearity of the channel causes amplitude distortion and phase rotation of a signal, which increases the bit error rate of a receiving end. The Volterra equalizer can be used as a nonlinear equalizer, can well fit nonlinear channel characteristics, and can compensate the nonlinearity of a channel.
The Volterra equalization method adopted by the invention is realized based on an LMS adaptive algorithm, the traditional LMS adaptive algorithm refers to fig. 9, at the time of n, an input signal x (n) passes through a filter adjusted at the time of n-1 to obtain an output signal y (n), the output signal y (n) is compared with an expected signal d (n) to obtain an error signal e (n), and then the filtering parameters of the filter at the time of n +1 are adjusted, so that the output signal tends to an ideal signal in the whole process.
The output signal y (n) and tap coefficient W (n) are represented as:
Figure RE-GDA0003574096000000091
where x (n) is the input signal vector at time n, w (n) is the tap weight vector of the adaptive filter at time n, and μ is defined herein as the step factor. The invention adopts an LMS adaptive algorithm to update the tap coefficient, wherein mu is set to be 0.01, the length of W (n) is M, the invention only adopts a linear tap, and M is set to be 9. Referring to fig. 2, a flow chart of a Volterra equalizer based on an LMS algorithm provided by the present invention includes:
s1: inputting data into a parallel shift register with the length of M +1, and caching the data in the current register when the pilot frequency is effective;
s2: updating tap coefficients based on an LMS algorithm;
s3: and according to the updated tap coefficient, carrying out parallel filtering on the delayed data of the shift register.
The S1 includes:
s11: sending input data to two parallel shift registers with the length of M +1, and transmitting the input data to a tap coefficient updating module;
s12: inputting the register data into a pilot buffer unit, judging whether the pilot enable is valid, if not, continuing to input the data, and if so, executing S12.
Specifically, the [ M +1:2] and [ M:1] data in the parallel shift register are written into the cache RAM at the same time, a first flag1 is set, and the flag1 is inverted when the pilot enable is valid. When the first flag bit flag1 is valid, the read address of the cache RAM is increased, and [ M +1:2] data is read; when the flag bit flag1 is invalid, reading [ M:1] data; thus, parallel writing and serial reading are completed.
The S2 includes:
s21: serially reading out the cached shift register data, and multiplying the data by the current tap register data;
s22: carrying out hard decision on the multiplied and accumulated result of S21 to obtain a current error value;
s23: and sending the cached data of the shift register of the S21 to a delay unit, multiplying the data by the current error value and the step factor, accumulating the data to a tap coefficient register, updating the tap coefficient, outputting the updated tap coefficient to a parallel data filtering module, and executing S21.
S21, multiplying the shift register data by the tap register, and calculating as:
y(n)＝W(n)HX(n)
in the hard decision of S22, the calculation formula is:
e(n)＝d(n)-y(n)
s23, the tap coefficient updating mode is based on the LMS adaptive algorithm, and the calculation formula is as follows:
W(n+1)＝W(n)+μX(n)e*(n)
the definitions and values of the symbols in the formula are the same as those defined above. Because the loop updating needs a certain time delay, the new data reading of the shift register is carried out after the last updating is finished, and thus, the loop updating is finished by utilizing the pilot frequency non-effective part.
The S3 includes:
s31: performing serial-parallel conversion on the tap coefficients of S23, and outputting two paths of parallel tap coefficients;
s32: and delaying the data in the parallel shift register of S11, and respectively entering the two paths of delayed data and the parallel tap coefficients of S31 into two multiplication accumulation modules to obtain two paths of parallel output data.
Specifically, at S31, the serial-to-parallel conversion module sets a second flag2, and when the valid enable of the tap update module output comes, the flag2 is negated. When the second flag bit flag2 is valid, the write address of the cache RAM is increased, and the tap coefficient register is written into the high bit of the write port of the RAM; when the second flag2 is inactive, the tap coefficient register is written into the RAM write port status. And reading out the parallel data from the cache RAM, and reading out the address for two times to effectively enable the address. Thus, serial writing and parallel reading are completed.
And S32, delaying the parallel shift register, wherein the delay length N is determined by the delay of updating the tap coefficient once. The [ M +1:2] and [ M:1] data in the parallel shift register are multiplied and accumulated by two paths of parallel tap coefficients respectively, and 2M complex multipliers are needed in total.
Example 2
As shown in fig. 3, the invention provides a low-complexity time-domain two-way parallel Volterra equalizer FPGA implementation method based on an LMS algorithm, and the low-complexity time-domain two-way parallel Volterra equalizer FPGA implementation method includes a tap coefficient updating module and a parallel data filtering module, which are implemented by hardware through an FPGA.
In the invention, the tap coefficient updating module comprises a tap coefficient register, a hard decision device, a delay unit D1, a pilot frequency buffer unit, multipliers T1, T2 and an adder A1. And the data of the parallel shift register is cached when the pilot frequency is enabled to be effective, and the length of the read array is the length M of the tap coefficient. The buffer array X (n) is multiplied by the conjugate of the tap coefficient W (n) to obtain an output y (n), and the multiplier T1 comprises M complex multipliers. And performing hard decision on y (n) to obtain a decision constellation point d (n), and performing difference on y (n) to obtain a difference value e (n). The pilot buffer array x (n) is multiplied by the difference e (n) and the step factor μ through the delay unit D1, and the multiplier T2 includes M complex multipliers. And accumulating the multiplication result to a tap coefficient, updating the numerical value in a tap coefficient register, and outputting the numerical value to a parallel data filtering module.
The parallel data filtering module comprises a parallel shift register, a delay unit D2, a serial-parallel conversion module, a multiplication and accumulation module 1 and a multiplication and accumulation module 2. The length of the parallel shift register is M +1, two paths of parallel data respectively enter the Mth bit and the M +1 th bit, and the data in the shift register moves two bits from the high bit to the low bit each time. The delay unit D2 is implemented by a dual-port RAM, and the read enable is pulled high after the tap coefficients are updated for the first time, and the parallel shift register data is read. The serial-parallel conversion module converts the serial M tap coefficients into two paths of parallel M tap coefficients, and is still realized by a dual-port RAM (random access memory), and serial writing and parallel reading are carried out. The multiplication and accumulation module 1 and the multiplication and accumulation module 2 respectively multiply and accumulate two parallel tap coefficient registers and data shift registers, and the multiplication and accumulation module comprises 2M complex multipliers. And the result of multiplication and accumulation is the equalized data output by the parallel filtering module.
The invention adopts a parallel shift register with the length of M +1, updates M serial tap coefficients for pilot frequency effective data in the register according to an LMS algorithm, performs parallel filtering by using the updated tap coefficients, and finally outputs two paths of parallel data.
The invention realizes two-path parallel equalization on single symbol rate and improves the working clock frequency of the module. The tap coefficient updating module adopts an LMS adaptive algorithm, reads pilot frequency data in the parallel shift register in series, updates the tap coefficient in real time through hard decision, still works after data convergence, and can track channel change in real time. And the multiplication accumulation module is multiplexed twice in the parallel data filtering module, so that two-path parallel processing is realized, and compared with a serial Volterra equalizer, the resource consumption of M complex multipliers is increased, and the operation complexity is low. The equalizer provided by the invention can effectively compensate the nonlinear distortion in the nonlinear channel of the high-flux satellite and improve the working frequency of the module.
Example 3
The time domain parallel Volterra equalizer, the equalization method and the terminal facing the broadband satellite access based on the LMS adaptive algorithm are the same as the embodiments 1-2, referring to FIG. 3, in a serial data updating module, the invention serially reads out data in a parallel shift register when pilot frequency is effective, and completes parallel-serial conversion, and specifically comprises the following steps:
as shown in FIG. 4, the parallel shift register has a length of M +1, which is represented by [ u (M +1), u (M-1), …, u (3), u (2), u (1) ], where M is the tap coefficient length, and the present invention only uses linear taps, and M takes a value of 9. Writing [ u (M +1), u (M-1), …, u (3), u (2) ] into the register 1, writing [ u (M), u (M-1), …, u (3), u (2), u (1) ] into the register 2, and storing the register 1 and the register 2 into the dual-port RAM as a writing end, wherein the bit width of read-write data is 2M W, and W is the bit width of input data u (n). At the read end of the dual port RAM, the read enable interval is twice the write enable interval. When the read enable is enabled, the high bit portion of the read data rd _ data is [ x (M +1), x (M-1), …, x (3), x (2) ], the low bit portion is [ x (M), x (M-1), …, x (3), x (2), x (1) ], and the high bit portion and the low bit portion are alternately selected, i.e., serial read is completed.
Referring to fig. 4, the serial-to-parallel conversion process of the tap coefficients in the parallel data filtering module is the inverse process of the above parallel-to-serial conversion, the length of the written tap coefficient is M, and two parallel paths of tap coefficients, which are 2M tap coefficients in total, are read out.
The invention uses the serial LMS adaptive algorithm to complete the tap coefficient updating, and uses the updated tap coefficient to perform parallel data filtering. The invention completes the interface of the two modules through the parallel-serial conversion module and the inverse process thereof, has lower FPGA realization complexity, and doubles the clock frequency supported by the serial Volterra equalizer.
Example 4
The time domain parallel Volterra equalizer, the equalization method and the terminal facing the broadband satellite access based on the LMS adaptive algorithm are the same as the embodiments 1-2, and referring to fig. 3, in the parallel data filtering module, the invention delays two parallel shift registers and respectively multiplies and accumulates the two parallel tap registers. Referring to fig. 5, the length of the parallel shift register is M +1, which is denoted as [ u (M +1), u (M-1), …, u (3), u (2), u (1) ], and the two-way tap coefficient registers are denoted as [ w1(M), w1(M-1), …, w1(3), w1(2), w1(1) ] and [ w2(M), w2(M-1), …, w2(3), w2(2), w2(1) ], respectively. When the data effective enable comes, referring to fig. 5(a), in the multiplication and accumulation module 1, [ u (M), u (M-1), …, u (2), u (1) ] are multiplied and accumulated with [ w1(M), w1(M-1), …, w1(3), w1(2), w1(1) ]; referring to fig. 5(b), in the multiply-accumulate module 2, [ u (M +1), u (M), …, u (3), u (2) ] are multiplied and accumulated with [ w2(M), w2(M-1), …, w2(3), w2(2), w2(1) ], respectively.
The invention adopts two paths of parallel data to filter data simultaneously, realizes time domain equalization, and thus, the multiplication accumulation module is multiplexed twice so as to output two paths of data simultaneously.
The invention sends two paths of parallel data into a parallel shift register, delays the data in the parallel shift register, multiplies and accumulates the data with two paths of updated parallel tap coefficient registers respectively, each multiplication and accumulation module contains M complex multipliers, and finally two paths of parallel outputs of an equalizer are obtained.
Example 5
The time domain parallel Volterra equalizer, the equalization method and the terminal facing the broadband satellite access based on the LMS adaptive algorithm are the same as the embodiments 1-2, referring to FIG. 3, in the tap coefficient updating module, when the pilot frequency is effective, the data in the parallel shift register is cached, and the cached data is read out in series, and the specific mode is shown in the embodiment 3; and multiplying and accumulating the read array and the data in the tap coefficient register, then carrying out hard decision, obtaining an error value according to the data information after decision, and updating the tap coefficient register according to the error value and the step factor.
The tap coefficient updating module processes the flow, and the specific steps comprise:
delaying input pilot frequency enabling, wherein the delay length is M/4, and performing serial reading on data X (n) in the parallel shift register according to the delayed pilot frequency enabling;
according to the LMS adaptive algorithm, obtaining equalizer output y (n) corresponding to pilot data:
y(n)＝W(n)HX(n)
the equalizer output y (n) corresponding to the pilot frequency data carries out hard decision to obtain an expected value d (n);
subtracting the output y (n) of the equalizer corresponding to the pilot frequency data from the expected value d (n) to obtain an error value e (n);
and obtaining an updated tap coefficient according to an LMS adaptive algorithm:
W(n+1)＝W(n)+μX(n)e*(n)
in a tap coefficient updating module, an M bit is set at an initial tap of a tap coefficient register, the invention multiplies the data in the parallel shift register when pilot frequency is effective by using M complex multipliers by the conjugate of an error value e (n), multiplies the data by a step factor, and accumulates the multiplied data to a tap coefficient W (n) to obtain an updated tap coefficient W (n + 1). The multiplication of the step factors can be realized by shift addition, and the use of the multiplier is reduced.
Example 6
The time domain parallel Volterra equalizer, the equalization method and the terminal facing the broadband satellite access based on the LMS adaptive algorithm are the same as the embodiments 1-2, and referring to fig. 3, the tap coefficient updating module caches the data in the parallel shift register when the pilot frequency is enabled to arrive and serially reads the cached data as described in embodiment 5. The invention updates the tap coefficient in the pilot non-effective time period because a certain interval exists between the pilot and the tap coefficient updating loop has delay. Referring to fig. 10, wr _ en is pilot active enable, and indicates two paths of being active or inactive, the length is B1, and the interval length between pilots is B2; rd _ en represents tap coefficient updating enabling, and the loop updating delay length is N; when the tap coefficient updating module works, the length of B1+ B2 should be greater than N × B1, so that it can be guaranteed that the update of the tap coefficient of the previous pilot block is completed before the next pilot is enabled.
Example 7
Referring to fig. 3, in the tap coefficient updating module of the present invention, the hard decision manner in step c) is QPSK decision, that is, the input data is decided as QPSK constellation points: when the real part or imaginary part data of the output y (n) of the equalizer is positive, the decision is 0.707; when the real or imaginary data of the equalizer output y (n) is negative, the decision is-0.707, resulting in the desired standard data point d (n). And (3) subtracting the standard constellation point from y (n) output by the equalizer to obtain a current error value e (n), which is shown as the following formula:
e(n)＝d(n)-y(n)
the technical effect of the invention is verified and explained by combining three simulation experiments.
Simulation experiment 1
Simulation conditions are as follows:
the simulation platform of the invention is Matlab2017. b. The simulation parameters are set as follows: the modulation mode is QPSK, the simulation frame number is 100 frames, the IMUX and the OMUX are simulated by 8-order and 7-order Chebyshev filters, and the TWTA adopts a saleh-HPA model.
Simulation content and simulation result analysis of the simulation experiment 1:
under the above conditions, the signal constellation before and after equalization is as shown in fig. 6(a) and fig. 6(b) by using the equalizer proposed by the present invention at the signal receiving end. As shown in fig. 6(a), when there are group delay distortion caused by IMUX-OMUX and nonlinear distortion caused by TWTA in the satellite channel, distortion occurs in the QPSK constellation. As shown in fig. 6(b), after the two-way parallel time domain equalizer proposed by the present invention, the QPSK constellation is good. EVM estimation is carried out on data before and after equalization, wherein the EVM estimation is respectively 0.185 and 0.032, and the equalizer provided by the invention has remarkable improvement on signal quality. The two-path parallel time domain equalizer provided by the invention improves the supported clock frequency and effectively compensates the linear distortion brought by IMUX-OMUX and the nonlinear distortion brought by TWTA.
Simulation experiment 2
Simulation conditions are as follows:
the simulation platform of the invention is Matlab2017. b. The simulation parameters are set as follows: the modulation mode is 8PSK, the simulation frame number is 100 frames, the IMUX and the OMUX are simulated by 8-order and 7-order Chebyshev filters, and the TWTA adopts a saleh-HPA model.
Simulation content and simulation result analysis of simulation experiment 2:
under the above conditions, the signal constellation before and after equalization is as shown in fig. 7(a) and fig. 7(b) by using the equalizer proposed by the present invention at the signal receiving end. As shown in fig. 7(a), when group delay distortion caused by IMUX-OMUX and nonlinear distortion caused by TWTA exist in a satellite channel, an 8PSK constellation may be distorted, and if equalization is not performed, decoding performance of a receiving end may be poor. As can be seen from fig. 7(b), after the two-way parallel time domain equalizer proposed by the present invention, the 8PSK constellation diagram is good. EVM estimation is carried out on data before and after equalization, wherein the EVM estimation is respectively 0.185 and 0.032, and the equalizer provided by the invention has remarkable improvement on signal quality. The two-path parallel time domain equalizer provided by the invention improves the supported clock frequency and effectively compensates the linear distortion brought by IMUX-OMUX and the nonlinear distortion brought by TWTA.
Simulation experiment 3
Simulation conditions are as follows:
the simulation platform of the invention is Matlab2017. b. The simulation parameters are set as follows: the modulation mode is 16APSK, the simulation frame number is 100 frames, the IMUX and the OMUX are simulated by 8-order and 7-order Chebyshev filters, and the TWTA adopts a saleh-HPA model.
Simulation content and simulation result analysis of simulation experiment 3:
under the above conditions, the signal constellation before and after equalization is as shown in fig. 8(a) and fig. 8(b) by using the equalizer proposed by the present invention at the signal receiving end. As shown in fig. 8(a), when group delay distortion caused by IMUX-OMUX and nonlinear distortion caused by TWTA exist in a satellite channel, a 16APSK constellation is distorted, and if equalization is not performed, decoding performance of a receiving end is poor. As can be seen from fig. 8(b), after the two-way parallel time domain equalizer proposed by the present invention, the 16APSK constellation is good. EVM estimation is carried out on data before and after equalization, wherein the EVM estimation is respectively 0.186 and 0.032, and the equalizer provided by the invention has remarkable improvement on signal quality. The two-path parallel time domain equalizer provided by the invention improves the supported clock frequency and effectively compensates the linear distortion brought by IMUX-OMUX and the nonlinear distortion brought by TWTA.
The invention discloses a low-complexity time domain parallel Volterra equalizer based on an LMS algorithm and an equalization method thereof, which mainly solve the problems of linear distortion caused by IMUX-OMUX and nonlinear distortion caused by TWTA in a high-throughput satellite communication system; meanwhile, because the system has high clock frequency and high transmission speed, the equalizer provided by the invention realizes two parallel low-complexity FPGAs. The equalizer carries out serial updating on tap coefficients through a tap coefficient updating module, and carries out two-path parallel multiplication and accumulation by utilizing the updated tap coefficients through a parallel data filtering module to obtain equalized data. The method comprises the following steps: storing input data into a parallel shift register, caching the data in the parallel shift register when pilot frequency is effective, and serially reading to obtain serial data; serially updating the read data based on the LMS algorithm; performing serial-parallel conversion on the updated tap data, and outputting two paths of parallel tap data; and delaying the parallel input data, and multiplying and accumulating the delayed parallel input data and the updated parallel tap data respectively to obtain two paths of parallel equalized data. The invention is based on the time domain equalizer structure of LMS algorithm serial updating tap and parallel filtering, and only carries out tap updating when pilot frequency data arrives, thus realizing low complexity and simple structure; compared with a serial Volterra equalizer, the supported clock frequency is doubled, and the transmission requirement of a high-throughput satellite system is met.
In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When used in whole or in part, can be implemented in a computer program product that includes one or more computer instructions. When loaded or executed on a computer, cause the flow or functions according to embodiments of the invention to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, the computer instructions may be transmitted from one website site, computer, server, or data center to another website site, computer, server, or data center via wire (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL), or wireless (e.g., infrared, wireless, microwave, etc.)). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device, such as a server, a data center, etc., that includes one or more of the available media. The usable medium may be a magnetic medium (e.g., floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., Solid State Disk (SSD)), among others.
The above description is only for the purpose of illustrating the present invention and the appended claims are not to be construed as limiting the scope of the invention, which is intended to cover all modifications, equivalents and improvements that are within the spirit and scope of the invention as defined by the appended claims.

Claims (10)

1. A time domain parallel Volterra equalization method is characterized by comprising the following steps:
firstly, shifting and registering input data, outputting the data to a tap coefficient updating module, and caching the data of a current register when pilot frequency is effective;
updating serial tap coefficients according to the cached register data based on an LMS algorithm;
and step three, delaying the input data register, and performing parallel filtering according to the updated tap coefficient to obtain equalized output data.
2. The time-domain parallel Volterra equalization method of claim 1 wherein said first step of shift registering input data and outputting to a tap coefficient update module, wherein buffering data from a current register when pilot is valid comprises:
(1) sending input data to two parallel shift registers with the length of M +1, and transmitting the input data to a tap coefficient updating module;
(2) and (3) inputting the register data into a pilot frequency cache unit, judging whether the pilot frequency enable is valid, if so, continuing to input the data, and if so, executing the step (2).
3. The time-domain parallel Volterra equalization method of claim 1 wherein said first step of shift registering input data and outputting to a tap coefficient update module, wherein buffering data in a current register when pilot is valid specifically comprises:
simultaneously writing the [ M +1:2] and [ M:1] data in the parallel shift register into a cache RAM, setting a first flag1, and negating a flag1 when pilot frequency enabling is effective;
when the first flag bit flag1 is valid, the read address of the cache RAM is increased, and [ M +1:2] data is read; when the flag bit flag1 is invalid, the [ M:1] data is read, and parallel writing and serial reading are completed.
4. The time-domain parallel Volterra equalization method of claim 1 wherein said LMS algorithm based serial tap coefficient update of said buffered register data in step two comprises:
(1) serially reading out the cached data of the shift register and multiplying the data of the shift register by the data of the current tap register;
(2) carrying out hard decision on the result of multiplication and accumulation in the step (1) to obtain a current error value;
(3) sending the cached data of the shift register in the step (1) into a delay unit, multiplying the data by a current error value and a step factor, accumulating the data to a tap coefficient register, updating a tap coefficient, outputting the updated tap coefficient to a parallel data filtering module, and executing the step (1) at the same time;
the calculation formula for multiplying the shift register data by the tap register is as follows:
y(n)＝W(n)HX(n)；
the calculation formula of the hard decision is as follows:
e(n)＝d(n)-y(n)；
the tap coefficient updating mode is based on an LMS adaptive algorithm, and the calculation formula is as follows:
W(n+1)＝W(n)+μX(n)e*(n)；
wherein, x (n) is the input signal vector at n time, w (n) is the tap weight vector of the adaptive filter at n time, the length of w (n) is M, and μ is the step factor.
5. The time-domain parallel Volterra equalization method of claim 1 wherein said delaying said input data register in step three and performing parallel filtering based on updated tap coefficients to obtain equalized output data comprises:
(1) performing serial-parallel conversion on the tap coefficients in the step two, and outputting two paths of parallel tap coefficients;
(2) and (3) delaying the data in the parallel shift register of the step one, and respectively entering the two paths of delayed data and the parallel tap coefficients of the step (1) into two multiplication accumulation modules to obtain two paths of parallel output data.
6. The time-domain parallel Volterra equalization method of claim 1, wherein delaying the input data register in step three and performing parallel filtering according to the updated tap coefficients to obtain equalized output data specifically comprises:
the serial-parallel conversion module is provided with a second flag bit flag2, and when the effective enabling output by the tap updating module comes, the flag2 is negated; when the second flag bit flag2 is valid, the write address of the cache RAM is increased, and the tap coefficient register is written into the high bit of the write port of the RAM; when the second flag bit flag2 is invalid, the tap coefficient register is written into the RAM write port bit; reading parallel data from the cache RAM, and reading addresses for two times to effectively enable the addresses to be read so as to complete serial writing and parallel reading;
the parallel shift register is delayed, and the delay length N is determined by the delay of updating the tap coefficient once; the [ M +1:2] and [ M:1] data in the parallel shift register are multiplied and accumulated by two paths of parallel tap coefficients respectively, and 2M complex multipliers are needed in total.
7. A time domain parallel Volterra equalizer implementing the time domain parallel Volterra equalizing method of any one of claims 1 to 6, the time domain parallel Volterra equalizer comprising a tap data updating module and a parallel data filtering module;
the tap data updating module comprises a tap coefficient register, a hard decision device, a delay unit and a pilot frequency buffer unit; the parallel data filtering module comprises a parallel shift register, a delay unit, a serial-parallel conversion module and a multiplication accumulation module;
the parallel shift register is connected with the pilot frequency cache unit, the output data of the parallel shift register is transmitted to the pilot frequency cache unit, and the data of the current register is cached when the pilot frequency is enabled to be effective;
the tap coefficient register is connected with the serial-parallel conversion module, and the updated tap coefficient enters the serial-parallel conversion module to perform parallel filtering on data;
wherein the tap data update module comprises:
the tap coefficient register is used for updating the tap coefficient when a new error value comes;
the hard decision device is used for obtaining an error value between the current data and the standard constellation point;
the delay unit is used for delaying the register data when the pilot frequency is effective and multiplying the delayed register data by the error value after hard decision to obtain the numerical value of the tap coefficient needing to be accumulated;
the pilot frequency caching unit is used for caching the shift register when the pilot frequency enable comes;
the parallel data filtering module comprises a parallel shift register, a delay unit, a serial-parallel conversion module and a multiplication accumulation module;
the parallel data filtering module includes:
the parallel shift register is used for inputting two paths of parallel data into a shift register with the length of N, wherein N is the length of a tap coefficient plus 1;
the delay unit is used for delaying the parallel shift register and keeping consistent with the updated tap coefficient;
the serial-parallel conversion module is used for converting the data in the tap coefficient register into two paths of parallel outputs;
and the multiplication and accumulation module is used for multiplying and accumulating the delayed parallel shift register data and the parallel tap coefficients to obtain two paths of parallel output data.
8. A computer device, characterized in that the computer device comprises a memory and a processor, the memory storing a computer program which, when executed by the processor, causes the processor to carry out the steps of:
inputting data into a parallel shift register with the length of M +1 for shift register, outputting the data to a tap coefficient updating module, and caching the data of the current register when the pilot frequency is effective; updating serial tap coefficients according to the cached register data based on an LMS algorithm; and delaying the input data register, and performing parallel filtering according to the updated tap coefficient to obtain equalized output data.
9. A computer-readable storage medium storing a computer program which, when executed by a processor, causes the processor to perform the steps of:
inputting data into a parallel shift register with the length of M +1 for shift register, outputting the data to a tap coefficient updating module, and caching the data of the current register when the pilot frequency is effective; updating serial tap coefficients according to the cached register data based on an LMS algorithm; and delaying the input data register, and performing parallel filtering according to the updated tap coefficient to obtain equalized output data.
10. An information data processing terminal, characterized in that the information data processing terminal is configured to implement the time-domain parallel Volterra equalizer of claim 7.
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