CN114420068B

CN114420068B - Display panel and display device

Info

Publication number: CN114420068B
Application number: CN202210112215.7A
Authority: CN
Inventors: 徐姗姗; 陈吉湘; 林剑涛; 朱敬光; 王文超; 刘耀; 徐旭
Original assignee: BOE Technology Group Co Ltd; Fuzhou BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Fuzhou BOE Optoelectronics Technology Co Ltd
Priority date: 2022-01-29
Filing date: 2022-01-29
Publication date: 2023-08-08
Anticipated expiration: 2042-01-29
Also published as: CN114420068A

Abstract

The application provides a display panel and a display device, and relates to the technical field of display, wherein the display panel comprises a plurality of scanning lines and a plurality of data lines, and the scanning lines and the data lines are intersected and insulated; a plurality of sub-pixels arranged in an array; the data line comprises a first data line and a second data line, and in the same row of sub-pixels arranged along the first direction, 4n+1 th and 4n+2 th sub-pixels are electrically connected with the first data line, and 4n+3 th and 4n+4 th sub-pixels are electrically connected with the second data line; wherein n is equal to zero or a positive integer; the same row of sub-pixels arranged along the second direction are electrically connected with the same scanning line; the first direction is the extending direction of the data line, and the second direction is the extending direction of the scanning line. The display panel has high charging rate and good display effect.

Description

Display panel and display device

Technical Field

The application relates to the technical field of display, in particular to a display panel and a display device.

Background

With the rapid development of display technology, performance requirements of display products are increasing. For high-quality display products such as high refresh rate and high resolution, the charging time is shorter and shorter, and it is more and more difficult to meet the standard of the pixel charging rate, and how to increase the charging rate becomes an important issue of the competitiveness of the display product.

Currently, a new display panel is needed to solve the above problems.

Disclosure of Invention

The embodiment of the application provides a display panel and a display device, and the display panel has high charging rate and good display effect.

The embodiment of the application adopts the following technical scheme:

in a first aspect, embodiments of the present application provide a display panel, including:

a plurality of scan lines and a plurality of data lines, the scan lines intersecting and insulated from the data lines;

a plurality of sub-pixels arranged in an array;

the data lines comprise a first data line and a second data line, and in the same row of the sub-pixels arranged along the first direction, 4n+1 th and 4n+2 th sub-pixels are electrically connected with the first data line, and 4n+3 th and 4n+4 th sub-pixels are electrically connected with the second data line; wherein n is equal to zero or a positive integer;

the same row of the subpixels arranged along the second direction are electrically connected with the same scanning line; the first direction is the extending direction of the data line, and the second direction is the extending direction of the scanning line.

In some embodiments of the present application, the pixels of the same row of the sub-pixels arranged along the first direction have the same color.

In some embodiments of the present application, the sub-pixel is located within an area defined by the data line and the scan line, the sub-pixel includes an opening area, and the opening area includes:

a substrate;

a first conductive layer on the substrate;

the patterned second conductive layer is positioned on one side of the first conductive layer away from the substrate and is insulated from the first conductive layer;

wherein a minimum distance between orthographic projections of the data lines onto the substrate to orthographic projections of the first conductive layer onto the substrate is smaller than a minimum distance between orthographic projections of the data lines onto the substrate to orthographic projections of the second conductive layer onto the substrate.

In some embodiments of the present application, a minimum distance between orthographic projections of the data lines on the substrate to orthographic projections of the first conductive layer on the substrate is greater than or equal to a first preset value.

In some embodiments of the present application, the first preset value is greater than or equal to 5.0 μm.

In some embodiments of the present application, an outline of the orthographic projection of the patterned second conductive layer on the substrate is located within an outline of the orthographic projection of the first conductive layer on the substrate, and a distance between the outline of the orthographic projection of the second conductive layer on the substrate to the outline of the orthographic projection of the first conductive layer on the substrate is greater than or equal to a second preset value.

In some embodiments of the present application, the second preset value is greater than or equal to 4.5 μm.

In some embodiments of the present application, in the same row of the sub-pixels arranged along the first direction, the scan line electrically connected to the 4n+1 th sub-pixel and the scan line electrically connected to the 4n+2 th sub-pixel are configured to be capable of being turned on simultaneously.

In some embodiments of the present application, the sub-pixel further includes a non-open region, the open region being connected to the non-open region;

the non-opening area comprises the substrate and at least one switch transistor positioned on the substrate, and the grid electrode of each switch transistor in the same row of the sub-pixels arranged along the second direction is electrically connected with the same scanning line;

in the same row of the sub-pixels arranged along the first direction, the first poles of the switching transistors in the 4n+1 th and 4n+2 th sub-pixels are electrically connected with the first data line, and the first poles of the switching transistors in the 4n+3 th and 4n+4 th sub-pixels are electrically connected with the second data line.

In some embodiments of the present application, the display panel further includes a plurality of GOA units and a clock signal input terminals, the clock signal input terminals are electrically connected to the GOA units, and output terminals of the GOA units are electrically connected to the scan lines;

the output signal of the nth GOA unit is used as an enabling signal of the (n+a)/2 th GOA unit, the output signal of the (n+1) th GOA unit is used as an enabling signal of the (n+1+a)/2 th GOA unit, the output signal of the (n+2) th GOA unit is used as an enabling signal of the (n+ 2+a)/2 th GOA unit, and the output signal of the (n+3) th GOA unit is used as an enabling signal of the (n+ 3+a)/2 th GOA unit;

the output signal of the (N+ 2+a)/2 th GOA unit is used as the reset signal of the (N) th GOA unit, the output signal of the (N+ 3+a)/2 th GOA unit is used as the reset signal of the (N+1) th GOA unit, the output signal of the (N+ 4+a)/2 th GOA unit is used as the reset signal of the (N+2) th GOA unit, and the output signal of the (N+ 5+a)/2 th GOA unit is used as the reset signal of the (N+3) th GOA unit, wherein N is a positive integer; a=8, 12 or 16.

In some embodiments of the present application, in the same row of the sub-pixels arranged along the first direction, the timing sequence of the output signals of the GOA units received by the scan lines electrically connected to the 4n+1 th sub-pixel and the scan lines electrically connected to the 4n+2 th sub-pixel is the same, and the timing sequence of the output signals of the GOA units received by the scan lines electrically connected to the 4n+3 th sub-pixel and the scan lines electrically connected to the 4n+4 th sub-pixel is the same.

In some embodiments of the present application, the GOA unit comprises a pull-up subunit configured to pull up an output signal of the GOA unit;

in the same row of the sub-pixels arranged along the first direction, the time sequence of the control signals in the pull-up sub-units electrically connected with the 4n+1 th sub-pixel is the same as the time sequence of the control signals in the pull-up sub-units electrically connected with the 4n+2 th sub-pixel, and the time sequence of the control signals in the pull-up sub-units electrically connected with the 4n+3 th sub-pixel is the same as the time sequence of the control signals in the pull-up sub-units electrically connected with the 4n+4 th sub-pixel.

In a second aspect, embodiments of the present application provide a display device including a display panel as described above.

Embodiments of the present application provide a display panel, a display device, the display panel including a plurality of scan lines and a plurality of data lines, the scan lines intersecting and insulated from the data lines; a plurality of sub-pixels arranged in an array; the data line comprises a first data line and a second data line, and in the same row of sub-pixels arranged along the first direction, 4n+1 th and 4n+2 th sub-pixels are electrically connected with the first data line, and 4n+3 th and 4n+4 th sub-pixels are electrically connected with the second data line; wherein n is equal to zero or a positive integer; the same row of sub-pixels arranged along the second direction are electrically connected with the same scanning line; the first direction is the extending direction of the data line, and the second direction is the extending direction of the scanning line.

Thus, based on such a double-Z inverted display panel, when a scanning signal is inputted line by line to a scanning line, a data signal inputted from a data line can be written line by line into a sub-pixel; when two scanning lines simultaneously input scanning signals, the data lines can simultaneously write data signals into the two rows of sub-pixels, and the data signals written into the two rows of sub-pixels are the same, so that the charging time of the data lines to the two rows of sub-pixels is doubled, the charging rate of the display panel is improved, the two rows of sub-pixels are ensured not to have color mixing, and the display effect of the display panel is improved.

The foregoing description is only an overview of the technical solutions of the present application, and may be implemented according to the content of the specification in order to make the technical means of the present application more clearly understood, and in order to make the above-mentioned and other objects, features and advantages of the present application more clearly understood, the following detailed description of the present application will be given.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 to fig. 6 are schematic structural diagrams of six display panels according to an embodiment of the present application;

fig. 7-8 are schematic diagrams of two scan signal timings according to embodiments of the present application;

fig. 9 is a schematic diagram showing the display effect of the related art and the display panel provided in the embodiment of the present application when two rows are simultaneously turned on;

fig. 10 and fig. 12 are schematic diagrams of cascade relationships of two GOA units according to embodiments of the present application;

fig. 11 and 13 are timing signal diagrams of two GOA units according to an embodiment of the present disclosure;

fig. 14 is a schematic circuit structure diagram of a GOA unit according to an embodiment of the present application.

Detailed Description

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.

In the drawings, the thickness of regions and layers may be exaggerated for clarity. The same reference numerals in the drawings denote the same or similar structures, and thus detailed descriptions thereof will be omitted. Furthermore, the drawings are only schematic illustrations of the present application and are not necessarily drawn to scale.

Throughout the specification and claims, the term "comprising" is to be interpreted as an open, inclusive meaning, i.e. "comprising, but not limited to, unless the context requires otherwise. In the description of the present specification, the terms "one embodiment," "some embodiments," "example embodiments," "examples," "particular examples," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present application. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

In the embodiments of the present application, the words "first," "second," and the like are used to describe the same item or similar item having substantially the same function and effect, only for clarity of describing the technical solutions of the embodiments of the present application, and should not be construed to indicate or imply that the relative importance or the number of technical features indicated is implicitly indicated.

With the rapid development of display technology, the requirements of people on the image quality of display products are increasing. The charging rate is one of the most important indexes in the design of display products, and a series of problems of substandard display, such as low transmittance, low contrast and the like, can be caused by insufficient charging rate.

Currently, for high performance display products such as high refresh frequency, high resolution and oversized, the difficulty of increasing the charging rate is more pronounced, while guaranteeing high performance of the display product itself.

An embodiment of the present application provides a display panel, shown with reference to fig. 1, including:

a plurality of scan lines Gate and a plurality of Data lines Data, the scan lines Gate and the Data lines Data intersecting and being insulated;

a plurality of sub-pixels P arranged in an array;

the Data line Data includes a first Data line D1 and a second Data line D2, and in the same row of sub-pixels P arranged along the first direction OA, 4n+1 th and 4n+2 th sub-pixels P are electrically connected to the first Data line D1, and 4n+3 th and 4n+4 th sub-pixels P are electrically connected to the second Data line D2; wherein n is equal to zero or a positive integer;

the same row of sub-pixels P arranged along the second direction OB are electrically connected with the same scanning line Gate; the first direction is the extending direction of the Data line Data, and the second direction is the extending direction of the scan line Gate.

In an exemplary embodiment, when n=0, in the same row of the subpixels P arranged along the first direction OA, the 1 st and 2 nd subpixels P are electrically connected to the first data line D1, and the 3 rd and 4 th subpixels P are electrically connected to the second data line D2.

In an exemplary embodiment, when n=1, in the same row of the subpixels P arranged along the first direction OA, the 5 th and 6 th subpixels P are electrically connected to the first data line D1, and the 7 th and 8 th subpixels P are electrically connected to the second data line D2.

When n is other positive integer, the connection between each sub-pixel and the data line is similar to that when n=0 and n=1, and will not be repeated here.

In practical application, the specific value of n is related to the number of rows of the designed sub-pixels in the display panel, and may be specifically determined according to practical situations, which is not limited herein.

The specific number of the scan lines Gate and the Data lines Data is not limited here, and may be specifically determined according to actual situations.

Here, the material of the scan line Gate and the material of the Data line Data are not limited.

Illustratively, the material of the scan line Gate may be at least one of copper (Cu), molybdenum (Mo), and aluminum (Al).

Illustratively, the material of the Data line Data may be at least one of copper (Cu), molybdenum (Mo), and aluminum (Al).

The specific structure of the sub-pixel P is not limited herein, and may be specifically determined according to the design of different display products.

In an exemplary embodiment, each of the sub-pixels P includes at least one of a red sub-pixel, a green sub-pixel, and a blue sub-pixel.

Illustratively, each subpixel P includes a red subpixel P1, a green subpixel P2, and a blue subpixel P3 as shown in fig. 2.

In an exemplary embodiment, the display panel may be adapted to a progressive scanning driving manner; alternatively, the display panel may be applied to a driving method in which two rows are scanned simultaneously.

In an exemplary embodiment, when the scan signal of the scan line Gate is turned on row by row, the Data signal of the Data line Data can be written into the pixel electrode of the sub-pixel, and the charging time at this time is defined as T; when the scan signals of the two scan lines Gate are turned on at the same time, the Data signals of the Data line Data can be written into the pixel electrodes of the sub-pixels of the two rows at the same time, and it can be understood that the charging time of the sub-pixels of the two rows is 2T at this time, and the charging time is doubled.

In an exemplary embodiment, when the scan signals of the two scan lines Gate are simultaneously turned on, the 4n+1 th and 4n+2 th rows of sub-pixels are simultaneously turned on, and the 4n+3 th and 4n+4 th rows of sub-pixels are simultaneously turned on. This driving mode may be referred to as double Z Inversion (Dual Z-Inversion).

Embodiments of the present application provide a display panel including a plurality of scan lines and a plurality of data lines, the scan lines and the data lines intersecting and insulated; a plurality of sub-pixels arranged in an array; the data line comprises a first data line and a second data line, and in the same row of sub-pixels arranged along the first direction, 4n+1 th and 4n+2 th sub-pixels are electrically connected with the first data line, and 4n+3 th and 4n+4 th sub-pixels are electrically connected with the second data line; wherein n is equal to zero or a positive integer; the same row of sub-pixels arranged along the second direction are electrically connected with the same scanning line; the first direction is the extending direction of the data line, and the second direction is the extending direction of the scanning line.

Thus, based on such a Dual Z-Inversion (Dual Z-Inversion) display panel, when a scan signal is inputted line by line to a scan line, a data signal inputted from a data line can be written line by line into a sub-pixel; when two scanning lines simultaneously input scanning signals, the data lines can simultaneously write data signals into the two rows of sub-pixels, and the data signals written into the two rows of sub-pixels are the same, so that the charging time of the data lines to the two rows of sub-pixels is doubled, the charging rate of the display panel is improved, the two rows of sub-pixels are ensured not to have color mixing, and the display effect of the display panel is improved.

In addition, the display panel provided by the embodiment of the application can be suitable for high refresh rate/high PPI products; meanwhile, the driving mode of progressive scanning is compatible; the design of the display panel is not changed, and a new Mask is not required to be designed with resources (Mask is not changed); and the method can be applicable to low-refresh frequency products and can meet the requirements of different clients.

In some embodiments of the present application, referring to fig. 2, the pixels of the same row of sub-pixels P arranged along the first direction OA have the same color.

The first row of the subpixels arranged along the first direction OA is a red subpixel P1, the second row of the subpixels arranged along the first direction OA is a green subpixel P2, and the third row of the subpixels arranged along the first direction OA is a blue subpixel P3, i.e. the arrangement modes of the subpixels are a red subpixel (R), a green subpixel (G) and a blue subpixel (B).

The arrangement of the sub-pixels may be, for example, red sub-pixels (R), blue sub-pixels (B) and green sub-pixels (G).

Fig. 5 illustrates a display panel of a related art Z-Inversion (Z-Inversion) design, in which when two rows of sub-pixels are simultaneously turned on, the charging time of the sub-pixels can be doubled, so as to improve the charging rate of the display panel, but as shown in fig. 9 (1), when two rows of sub-pixels are simultaneously turned on, for example, a green G picture is displayed, a red sub-pixel R is also written with a write signal, which results in a color mixing problem of an actual display picture.

In addition, fig. 6 illustrates a display panel of a dual data line design in the related art, wherein two data lines are disposed between two adjacent columns of sub-pixels, wherein one data line connects only half of the sub-pixels in the same column; when two rows of sub-pixels are simultaneously turned on, a display panel can normally display a pure color picture or a non-pure color picture, the purposes of doubling the charging time and improving the charging rate can be achieved without color mixing, however, the distance between two adjacent rows of sub-pixels is relatively short, the problem of signal crosstalk is very easy to occur, and therefore, the distance between the two data lines is set to be more than 12 mu m, so that the aperture ratio of the display panel is reduced, the transmittance of the display panel is greatly reduced, and the display effect is poor.

However, in the embodiment of the present application, by setting the same row of the sub-pixels P arranged along the first direction OA to have the same pixel color, the 4n+1 th and 4n+2 th sub-pixels are electrically connected to the first data line, and the 4n+3 th and 4n+4 th sub-pixels are electrically connected to the second data line in the same row of the sub-pixels arranged along the first direction; in this way, when two rows of sub-pixels are turned on simultaneously (4n+1 row and 4n+2 row) in the display panel and the second data line inputs a data signal, as shown in (2) of fig. 9, 4n+1 and 4n+2 sub-pixels are turned on to green, it can be understood that in the display panel of the Dual Z Inversion (Dual Z-Inversion) design, when two rows of sub-pixels are turned on simultaneously, on one hand, the charging time of the sub-pixels is doubled, and the charging rate is improved; on the other hand, the two rows of sub-pixels are simultaneously turned on to display the picture, so that the cross color problem does not occur.

In some embodiments of the present application, the sub-pixel P is located within an area defined by the Data line Data and the scan line Gate, and the sub-pixel includes an opening area, which includes, referring to fig. 3 or 4:

a substrate 100;

a first conductive layer 101 on the substrate 100;

a patterned second conductive layer 104, which is located on a side of the first conductive layer 101 away from the substrate 100 and is insulated from the first conductive layer 101;

wherein, the minimum distance between the orthographic projections of the Data line Data on the substrate 100 to the orthographic projections of the first conductive layer 101 on the substrate 100 is smaller than the minimum distance between the orthographic projections of the Data line Data on the substrate 100 to the orthographic projections of the second conductive layer 104 on the substrate 100.

The minimum distance between orthographic projections of the Data line Data onto the substrate 100 onto orthographic projections of the first conductive layer 101 onto the substrate 100 means: the distance between the orthographic projection edge of the Data line Data on the substrate 100 and the orthographic projection edge of the first conductive layer 101 closest thereto on the substrate 100.

The minimum distance between the orthographic projection of the Data line Data on the substrate 100 to the orthographic projection of the second conductive layer 104 on the substrate 100 refers to the distance between the orthographic projection edge of the Data line Data on the substrate 100 to the orthographic projection edge of the second conductive layer 104 closest thereto on the substrate 100.

In an exemplary embodiment, the materials of the first conductive layer 101 and the second conductive layer 104 may be light-transmitting conductive materials.

Illustratively, the first conductive layer 101 and the second conductive layer 104 are the same material and are both Indium Tin Oxide (ITO).

The specific pattern of the patterned second conductive layer 104 is not limited herein, and may be determined according to practical situations.

Wherein a first insulating layer 102 and a second insulating layer 103 are provided between the first conductive layer 101 and the second conductive layer 104.

The materials of the first conductive layer 101 and the second conductive layer 104 may each be at least one or a combination of more than one of silicon oxide, silicon nitride, and silicon oxynitride.

In some embodiments of the present application, referring to fig. 3, a minimum distance between orthographic projections of the Data line Data on the substrate 100 and orthographic projections of the first conductive layer 101 on the substrate 100 is greater than or equal to a first preset value.

The first preset value may be, for example, 5.0 μm, or the first preset value may be 5.5 μm.

It is understood that the minimum distance between orthographic projections of the Data lines Data on the substrate 100 to orthographic projections of the first conductive layer 101 on the substrate 100 is greater than or equal to 5.0 μm.

In some embodiments of the present application, referring to fig. 3, the outline of the orthographic projection of the patterned second conductive layer 104 on the substrate 100 is located within the outline of the orthographic projection of the first conductive layer 101 on the substrate 100, and the distance between the outline of the orthographic projection of the second conductive layer 104 on the substrate 100 and the outline of the orthographic projection of the first conductive layer 101 on the substrate 100 is greater than or equal to a second preset value.

It is understood that the distance between the outer contour of the orthographic projection of the second conductive layer 104 on the substrate 100 to the outer contour of the orthographic projection of the first conductive layer 101 on the substrate 100 is greater than or equal to 4.5 μm.

In an exemplary embodiment, the minimum distance between the orthographic projection of the Data line Data onto the substrate 100 to the orthographic projection of the second conductive layer 104 onto the substrate 100 is equal to the sum of the minimum distance between the orthographic projection of the Data line Data onto the substrate 100 to the orthographic projection of the first conductive layer 101 onto the substrate 100 and the distance between the outer contour of the orthographic projection of the second conductive layer 104 onto the substrate 100 to the outer contour of the orthographic projection of the first conductive layer 101 onto the substrate 100.

In an exemplary embodiment, a minimum distance between orthographic projections of the Data line Data on the substrate 100 to orthographic projections of the second conductive layer 104 on the substrate 100 is greater than or equal to a third preset value.

Wherein the third preset value is equal to the sum of the first preset value and the second preset value.

The third preset value may be, for example, greater than 9.5 μm.

In the embodiment of the present application, by setting the minimum distance between the orthographic projection of the Data line Data on the substrate 100 and the orthographic projection of the second conductive layer 104 on the substrate 100 to be greater than or equal to the third preset value, the cross-grain phenomenon of the display panel can be avoided to a great extent, and the display effect is improved.

In some embodiments of the present application, in the same row of sub-pixels arranged along the first direction, the scan line electrically connected to the 4n+1 th sub-pixel and the scan line electrically connected to the 4n+2 th sub-pixel are configured to be capable of being turned on simultaneously.

In an exemplary embodiment, the display panel shown in fig. 1 can be scanned line by line, or both lines can be turned on at the same time.

Specifically, the display panel shown in fig. 1 may enable the scan line electrically connected to the 4n+1 th subpixel and the scan line electrically connected to the 4n+2 th subpixel to be turned on at the same time according to the timing chart shown in fig. 7. The display panel shown in fig. 1 may be such that each scanning line scans line by line according to the timing chart shown in fig. 8.

In some embodiments of the present application, referring to fig. 1, the sub-pixel further includes a non-open region, where the open region is connected to the non-open region; the non-opening region comprises a substrate 100 and at least one switching transistor FT positioned on the substrate 100, and the grid electrode of each switching transistor TFT in the same row of sub-pixels arranged along the second direction OB is electrically connected with the same scanning line Gate; in the same row of the sub-pixels arranged along the first direction OA, the first poles of the switching transistors TFT in the 4n+1 th and 4n+2 th sub-pixels are electrically connected to the first data line D1, and the first poles of the switching transistors TFT in the 4n+3 th and 4n+4 th sub-pixels are electrically connected to the second data line D2.

In a subpixel, the meaning of an opening region is: a light-permeable region; similarly, the non-open areas are areas that are not transparent to light. In the display panel, the size of the opening area largely determines the light transmittance of the display panel, and the larger the size of the opening area is, the smaller the size of the non-opening area is, the better the display effect of the display panel is, and the smaller the power consumption is.

Unlike the related art GOA cell connection method shown in fig. 12, in some embodiments of the present application, referring to fig. 10, the display panel further includes a plurality of GOA cells and a clock signal input terminals, the clock signal input terminals being electrically connected to the GOA cells, and an output terminal Gout of the GOA cells being electrically connected to the scan lines; to output a scan signal to the scan line.

the output signal of the (N+ 2+a)/2 (GOA) unit is used as the reset signal of the (N+ 3+a)/2 (GOA) unit, the output signal of the (N+ 3+a)/2 (GOA) unit is used as the reset signal of the (N+1) GOA unit, the output signal of the (N+ 4+a)/2 (GOA) unit is used as the reset signal of the (N+2) GOA unit, and the output signal of the (N+ 5+a)/2 (GOA) unit is used as the reset signal of the (N+3) GOA unit, wherein N is a positive integer; a=8, 12 or 16.

In the case of a=8, the output signal of the nth GOA unit (GOA N) is taken as the enabling signal of the n+4th GOA unit, the output signal of the n+1th GOA unit is taken as the enabling signal of the n+5th GOA unit, the output signal of the n+2th GOA unit is taken as the enabling signal of the n+6th GOA unit, and the output signal of the n+3th GOA unit is taken as the enabling signal of the n+7th GOA unit;

the output signal of the (n+6) th GOA unit is used as the reset signal of the (n+7) th GOA unit, the output signal of the (n+1) th GOA unit is used as the reset signal of the (n+2) th GOA unit, the output signal of the (n+9) th GOA unit is used as the reset signal of the (n+3) th GOA unit, wherein N is a positive integer.

In an exemplary embodiment, when n=1, the first output terminal (Gout) of the first GOA unit (GOA 1) is electrically connected to the first scan line, and the second output terminal is electrically connected to the fifth GOA unit (GOA 5); the output signal of the second output end of the first GOA unit is input into a fifth GOA unit and used as an enabling signal of the fifth GOA unit to control the fifth GOA unit to be started. The first output end of the second GOA unit (GOA 2) is electrically connected with the second scanning line, and the second output end is electrically connected with the sixth GOA unit (GOA 6); the output signal of the second output end of the second GOA unit (GOA 2) is input into the sixth GOA unit and is used as an enabling signal of the sixth GOA unit to control the sixth GOA unit to be started. The first output end of the third GOA unit is electrically connected with the third scanning line, and the second output end of the third GOA unit is electrically connected with the seventh GOA unit (GOA 7); the output signal of the second output end of the third GOA unit is input into the seventh GOA unit and used as the enabling signal of the seventh GOA unit to control the seventh GOA unit to be started. The first output of the fourth GOA unit is electrically connected to the fourth scan line, and the second output is electrically connected to the eighth GOA unit (GOA 8). The output signal of the second output end of the fourth GOA unit is input into the eighth GOA unit and used as the enabling signal of the eighth GOA unit to control the opening of the eighth GOA unit.

The case of a=12 or 16 is similar to the case of a=8, and a detailed description thereof is omitted.

In addition, fig. 10 and 12 provided in the embodiments of the present application are drawn with a=8.

In an exemplary embodiment, the number of clock signal inputs a may also include other numbers, which may be specifically determined according to practical situations, and only three cases a=8, 12 or 16 are provided for illustration.

In some embodiments of the present application, in the same row of sub-pixels P arranged along the first direction OA, the timings of output signals of the GOA units received by the scan lines Gate electrically connected to the 4n+1 th sub-pixel P and the scan lines Gate electrically connected to the 4n+2 th sub-pixel P are the same, and the timings of output signals of the GOA units received by the scan lines Gate electrically connected to the 4n+3 th sub-pixel P and the scan lines Gate electrically connected to the 4n+4 th sub-pixel P are the same.

Illustratively, when n=1, referring to fig. 11, the timing of the output signal of the first scan line G1 is the same as the timing of the output signal of the second scan line G2, the timing of the output signal of the third scan line G3 is the same as the timing of the output signal of the fourth scan line G4, the timing of the output signal of the fifth scan line G5 is the same as the timing of the output signal of the sixth scan line G6, and the timing of the output signal of the seventh scan line G7 is the same as the timing of the output signal of the eighth scan line G8. Therefore, the first row of sub-pixels and the second row of sub-pixels are controlled to be simultaneously turned on, the third row of sub-pixels and the fourth row of sub-pixels are controlled to be simultaneously turned on, the fifth row of sub-pixels and the sixth row of sub-pixels are controlled to be simultaneously turned on, and the seventh row of sub-pixels and the eighth row of sub-pixels are controlled to be simultaneously turned on, so that the charging rate of the display panel is improved.

In some embodiments of the present application, the GOA unit includes a pull-up subunit configured to pull up an output signal of the GOA unit;

in the related art, under the condition that two rows are simultaneously turned on, in the same row of sub-pixels arranged along the first direction, the time sequence of a control signal PU signal in a pull-up sub-unit electrically connected with the 4n+1 th sub-pixel is different from the time sequence of a control signal PU signal in a pull-up sub-unit electrically connected with the 4n+2 th sub-pixel, one time sequence of the control signal PU signal is directly reduced from a first level to a second level, and the first level is larger than the second level; the other time sequence is firstly reduced to a third level from the first level and then reduced to a second level, and the third level is larger than the second level and smaller than the first level. Thus, the output signals of the odd-numbered lines and the even-numbered lines are different, and the Gout signals of the odd-numbered lines are abnormal in output, so that abnormal discharge is caused; the timing of the output signals of the GOA units of the odd numbered rows occurs a tailing problem as indicated by the arrow position in fig. 13 when the level is changed from the high level to the low level, and a signal delay occurs, thereby reducing the display effect.

However, in the embodiment of the present application, in the case where two rows are simultaneously turned on, referring to fig. 11, in the same row of the sub-pixels arranged along the first direction, the timing of the control signal PU signal in the pull-up sub-unit to which the 4n+1 th sub-pixel is electrically connected is the same as the timing of the control signal PU signal in the pull-up sub-unit to which the 4n+2 th sub-pixel is electrically connected, and the timing of the control signal PU signal in the pull-up sub-unit to which the 4n+3 th sub-pixel is electrically connected is the same as the timing of the control signal PU signal in the pull-up sub-unit to which the 4n+4 th sub-pixel is electrically connected.

It should be noted that, the simultaneous opening of two rows means that in the same row of the sub-pixels arranged along the first direction, the 4n+1 th scanning line electrically connected to the sub-pixels and the 4n+2 th scanning line electrically connected to the sub-pixels can be simultaneously opened, and the 4n+3 th scanning line electrically connected to the sub-pixels and the 4n+4 th scanning line electrically connected to the sub-pixels can be simultaneously opened.

In an exemplary embodiment, the PU signal first drops from the first level to a third level and then drops to the second level when returning from the high level, the third level is greater than the second level and less than the first level, and the timing of the PU signal in the GOA unit to which the scan lines of the 4n+1 th row and the 4n+2 th row are electrically connected is the same, and the timing of the PU signal in the GOA unit to which the scan lines of the 4n+3 th row and the 4n+4 th row are electrically connected is the same.

In an exemplary embodiment, the simple structure of the GOA unit may be as shown in fig. 14, where the Gout end is electrically connected to one scan line in the display area, the output signal of the GOA unit may be pulled up by the point location of the PU point, and the PU point Reset (to a low level) may be assisted by a Reset unit (Reset PU), and the detailed circuit of the GOA unit may refer to the related art and will not be described herein.

In the embodiment of the present application, as shown in fig. 10 and 11, when two rows are opened simultaneously, the odd rows carry the odd rows, the odd rows reset the odd rows, the even rows carry the even rows, the even rows reset the even rows, and the waveforms of the PU signals are the same; the GOA can normally output even and odd two lines no matter the two lines are opened line by line or simultaneously, the display effect is good, and the problem of picture color mixing can not occur. It should be noted that, carry refers to the output signal of the GOA unit of the previous stage as the enabling signal of the GOA unit of the subsequent cascade, and controls the start of the GOA unit; reset refers to the restoration of the signal to an initial state.

The display panel provided by the embodiments of the present application may be a liquid crystal display panel, which may be a TN (Twisted Nematic) type, VA (Vertical Alignment) type, IPS (In-Plane Switching) type, ADS (Advanced Super Dimension Switch) type, or the like liquid crystal display panel. The liquid crystal display screen can comprise an array substrate, a color film substrate and liquid crystal positioned between the array substrate and the color film substrate; other arrangements of drive circuitry, etc. may of course be included. Only the structure related to the present invention will be described, and other structures included in the display panel may be obtained according to the related art or common general knowledge, and will not be described again.

Embodiments of the present application provide a display device including a display panel as described above.

The display device provided in the embodiment of the application includes: a plurality of scanning lines and a plurality of data lines, wherein the scanning lines and the data lines are intersected and insulated; a plurality of sub-pixels arranged in an array; the data line comprises a first data line and a second data line, and in the same row of sub-pixels arranged along the first direction, 4n+1 th and 4n+2 th sub-pixels are electrically connected with the first data line, and 4n+3 th and 4n+4 th sub-pixels are electrically connected with the second data line; wherein n is equal to zero or a positive integer; the same row of sub-pixels arranged along the second direction are electrically connected with the same scanning line; the first direction is the extending direction of the data line, and the second direction is the extending direction of the scanning line. Thus, based on such a Dual Z-Inversion (Dual Z-Inversion) display device, when a scan signal is inputted line by line to a scan line, a data signal inputted to a data line can be written line by line into a sub-pixel; when two scanning lines simultaneously input scanning signals, the data lines can simultaneously write data signals into the two rows of sub-pixels, and the data signals written into the two rows of sub-pixels are the same, so that the charging time of the data lines to the two rows of sub-pixels is doubled, the charging rate of the display device is improved, the two rows of sub-pixels are ensured not to have color mixing, and the display effect of the display device is improved. In addition, the display device provided by the embodiment of the application can be suitable for high refresh frequency/high PPI products; meanwhile, the driving mode of progressive scanning is compatible; the design of the display panel in the display device is not changed, and a new Mask is not required to be designed with resources (Mask is not changed); and the method can be applicable to low-refresh frequency products and can meet the requirements of different clients.

The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes and substitutions are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A display panel, comprising:

a plurality of sub-pixels arranged in an array, wherein the sub-pixels are located in an area defined by the data lines and the scanning lines, the sub-pixels comprise an opening area, and the opening area comprises:

a substrate;

a first conductive layer on the substrate;

the minimum distance between orthographic projections of the data lines on the substrate and orthographic projections of the first conductive layer on the substrate is smaller than the minimum distance between orthographic projections of the data lines on the substrate and orthographic projections of the second conductive layer on the substrate, the data lines comprise first data lines and second data lines, and in the same row of sub-pixels arranged along a first direction, 4n+1 th and 4n+2 th sub-pixels are electrically connected with the first data lines, and 4n+3 th and 4n+4 th sub-pixels are electrically connected with the second data lines; wherein n is equal to zero or a positive integer;

2. The display panel of claim 1, wherein pixels of the same row of subpixels arranged along the first direction are the same color.

3. The display panel of claim 2, wherein a minimum distance between orthographic projections of the data lines onto the substrate and orthographic projections of the first conductive layer onto the substrate is greater than or equal to a first preset value.

4. A display panel according to claim 3, wherein the first preset value is greater than or equal to 5.0 μm.

5. The display panel of claim 2, wherein an outline of the orthographic projection of the patterned second conductive layer on the substrate is within an outline of the orthographic projection of the first conductive layer on the substrate, and a distance between the outline of the orthographic projection of the second conductive layer on the substrate to the outline of the orthographic projection of the first conductive layer on the substrate is greater than or equal to a second preset value.

6. The display panel of claim 5, wherein the second preset value is greater than or equal to 4.5 μιη.

7. The display panel according to claim 1, wherein in the same row of the sub-pixels arranged along the first direction, the scan line electrically connected to 4n+1 th sub-pixel and the scan line electrically connected to 4n+2 th sub-pixel are configured to be simultaneously turned on.

8. The display panel of claim 2, wherein the sub-pixel further comprises a non-open area, the open area being connected to the non-open area;

9. The display panel of claim 7, further comprising a plurality of GOA cells and a clock signal inputs, the clock signal inputs electrically connected to the GOA cells, the outputs of the GOA cells electrically connected to the scan lines;

10. The display panel of claim 9, wherein in the same row of the subpixels arranged along the first direction, timings of output signals of the GOA units received by the scan lines electrically connected to 4n+1 th subpixels and the scan lines electrically connected to 4n+2 th subpixels are the same, and timings of output signals of the GOA units received by the scan lines electrically connected to 4n+3 th subpixels and the scan lines electrically connected to 4n+4 th subpixels are the same.

11. The display panel of claim 9, wherein the GOA unit comprises a pull-up subunit configured to pull up an output signal of the GOA unit;

12. A display device comprising a display panel according to any one of claims 1-11.