CN114416637A - SOC chip reset processing method and device, SOC chip and medium - Google Patents
SOC chip reset processing method and device, SOC chip and medium Download PDFInfo
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- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
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Abstract
The application discloses a method and a device for resetting an SOC chip, the SOC chip and a medium, comprising the following steps: writing a reset processing program into an on-chip RAM from an initial address of the on-chip RAM; mapping an initial address of the on-chip RAM to a CPU reset vector address; and when the SOC chip is not in cold reset, reading from the initial address of the on-chip RAM and executing the reset processing program so as to perform corresponding reset processing. Thus, when the SOC chip is not in cold reset, the CPU reads from the start address of the on-chip RAM and executes the reset processing program to perform the reset processing. After the chip is subjected to chip flow and chip return, different reset processing programs can be repeatedly written into the RAM for debugging according to the chip debugging requirements, the flexibility of chip reset processing is improved, BootROM is not required for non-cold reset to be executed again, and the time for processing the non-cold reset by the chip is saved.
Description
Technical Field
The present disclosure relates to the field of chip design technologies, and in particular, to a method and an apparatus for resetting an SOC chip, and a medium.
Background
With the rapid development of chip technology, the functions of chips are more and more powerful, so that the complexity of the chips is higher and more reset types are supported. The chip reset type mainly comprises: cold reset, debug reset, software reset, watchdog reset, PCIe (high speed serial computer extended bus standard) reset, etc.
Currently, in most chip designs, a CPU reset vector (i.e., a CPU (Central Processing Unit) reset vector) address space is used to place an on-chip ROM (i.e., a random access Memory) whose content is a BootROM program (i.e., a first section of code executed by a processor when the processor is powered on or reset). After the chip is reset, a CPU (central processing unit) can read and execute an instruction from a reset vector address, BootROM starts executing, reset processing is completed in a BootROM program, the BootROM program can firstly judge the type of the current reset, and enter a corresponding reset processing branch, and then corresponding processing is carried out according to the reset type. Since the BootROM program is fixed in the on-chip ROM, the chip can not be modified after being taped, which means that the code of the reset process can not be modified after being taped, and the method has no flexibility. In addition, after the chip reset occurs, the BootROM program needs to be re-executed, and the execution of the BootROM program needs time, especially the execution of an encryption and decryption algorithm in the BootROM program needs a large amount of time, so that the chip reset needs to be processed by spending valuable time.
Disclosure of Invention
In view of the above, an object of the present application is to provide a method and an apparatus for resetting an SOC chip, and a medium, which can improve flexibility of resetting the chip and save time for processing non-cold reset by the chip. The specific scheme is as follows:
in a first aspect, the present application discloses a method for resetting an SOC chip, comprising:
writing a reset processing program into an on-chip RAM from an initial address of the on-chip RAM;
mapping an initial address of the on-chip RAM to a CPU reset vector address;
and when the SOC chip is not in cold reset, reading from the initial address of the on-chip RAM and executing the reset processing program so as to perform corresponding reset processing.
Optionally, the executing the reset processing program to perform corresponding reset processing includes:
and executing the reset processing program, reading the register value of the reset state register in the executing process, judging the reset type of the current reset based on the register value, and executing the reset processing subprogram corresponding to the reset type according to the reset type so as to perform corresponding reset processing.
Optionally, the mapping the start address of the on-chip RAM to the CPU reset vector address includes:
operating a preset on-chip RAM mapping register to map a starting address of the on-chip RAM to a CPU reset vector address.
Optionally, the preset on-chip RAM mapping register is reset to a default value when the SOC chip is subjected to cold reset;
if the initial address of an on-chip ROM of the SOC chip is consistent with the CPU reset vector address, the default value of the preset on-chip RAM mapping register indicates that the initial address of the on-chip RAM is not mapped; and if the starting address of the on-chip ROM is inconsistent with the CPU reset vector address, the default value of the preset on-chip RAM mapping register represents that the starting address of the on-chip ROM is mapped to the CPU reset vector address.
Optionally, the method further includes:
when the SOC chip is in cold reset, reading from the initial address of the on-chip ROM and executing a BootROM program;
and after the BootROM program is executed, executing a Bootlloader program, and in the process of executing the BootROM program, starting from the initial address of the on-chip RAM, writing a reset processing program into the on-chip RAM, and mapping the initial address of the on-chip RAM to the CPU reset vector address.
Optionally, after mapping the starting address of the on-chip RAM to the CPU reset vector address, the method further includes:
the preset on-chip ROM control register is operated to turn off the power and clock of the on-chip ROM.
Optionally, the preset on-chip ROM control register is reset to a default value when the SOC chip is in a cold reset state, where the default value indicates that the power supply and the clock of the on-chip ROM are enabled.
In a second aspect, the present application discloses an SOC chip reset processing apparatus, including:
a reset processing program writing module for writing a reset processing program into the on-chip RAM from an initial address of the on-chip RAM;
the RAM address mapping module is used for mapping the initial address of the on-chip RAM to a CPU reset vector address;
and the SOC chip reset processing module is used for reading from the initial address of the on-chip RAM and executing the reset processing program to perform corresponding reset processing when the SOC chip is not in cold reset.
In a third aspect, the present application discloses an SOC chip, comprising:
a memory for storing a computer program;
and the processor is used for executing the computer program to realize the SOC chip reset processing method.
In a fourth aspect, the present application discloses a computer-readable storage medium for storing a computer program which, when executed by a processor, implements the foregoing SOC chip reset processing method.
Therefore, the reset processing program is written into the on-chip RAM from the initial address of the on-chip RAM, the initial address of the on-chip RAM is mapped to the CPU reset vector address, and when the SOC chip is not in cold reset, the reset processing program is read from the initial address of the on-chip RAM and executed so as to perform corresponding reset processing. That is, in the embodiment of the present application, the address space of the on-chip RAM is mapped to the address space of the CPU reset vector, and the reset processing program is written in the start position of the on-chip RAM. Because the content in the RAM can be modified, after the chip is subjected to tape-out and chip-back, different reset processing programs can be repeatedly written into the RAM for debugging according to the chip debugging requirement, and a final deliverable program is found out.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a flowchart of a reset processing method for an SOC chip disclosed in the present application;
FIG. 2 is a diagram illustrating an exemplary address mapping disclosed herein;
FIG. 3 is a schematic diagram of another specific address mapping disclosed herein;
FIG. 4 is a schematic diagram of a specific SOC chip reset process flow disclosed herein;
fig. 5 is a schematic structural diagram of an SOC chip reset processing apparatus disclosed in the present application;
fig. 6 is a structure diagram of an SOC chip disclosed in the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Currently, in most chip designs, a block of on-chip ROM (i.e., a Read Only Memory) is placed in the CPU reset vector address space, and the content of the ROM is a BootROM program. After the chip is reset, a CPU (central processing unit) can read and execute an instruction from a reset vector address, BootROM starts executing, reset processing is completed in a BootROM program, the BootROM program can firstly judge the type of the current reset, and enter a corresponding reset processing branch, and then corresponding processing is carried out according to the reset type. Since the BootROM program is fixed in the on-chip ROM, the chip can not be modified after being taped, which means that the code of the reset process can not be modified after being taped, and the method has no flexibility. In addition, after the chip reset occurs, the BootROM program needs to be re-executed, and the execution of the BootROM program needs time, especially the execution of an encryption and decryption algorithm in the BootROM program needs a large amount of time, so that the chip reset needs to be processed by spending valuable time. Therefore, the SOC (System On Chip) Chip reset scheme is provided, so that the flexibility of Chip reset processing can be improved, and the time for processing non-cold reset of the Chip is saved.
Referring to fig. 1, an embodiment of the present application discloses a method for resetting an SOC chip, including:
step S11: the reset handler is written to an on-chip RAM (Random Access Memory) starting from a start address of the on-chip RAM.
That is, in the embodiment of the present application, the reset handler is written to the on-chip RAM, and writing is started from the start address of the on-chip RAM.
Step S12: mapping a starting address of the on-chip RAM to a CPU reset vector address.
It should be noted that, after the CPU reset vector address is the CPU reset, the address where the first instruction is located is read, the start address of the on-chip RAM is mapped to the CPU reset vector address, and after the CPU reset, the address where the first instruction is located is read, which is the start address of the on-chip RAM.
In a particular embodiment, a preset on-chip RAM mapping register is operated to map a starting address of the on-chip RAM to a CPU reset vector address.
The preset on-chip RAM mapping register is reset to a default value when the SOC chip is subjected to cold reset; if the initial address of the on-chip ROM of the SOC chip is consistent with the CPU reset vector address, the default value of the preset on-chip RAM mapping register indicates that the initial address of the on-chip RAM is not mapped; and if the starting address of the on-chip ROM is inconsistent with the CPU reset vector address, the default value of the preset on-chip RAM mapping register represents that the starting address of the on-chip ROM is mapped to the CPU reset vector address.
It should be noted that, in the design of the SOC chip architecture, the address allocated to the CPU reset vector on the address space bus is determined according to the type of the CPU selected by the SOC chip architecture. For example, the CPU of ARM company is used, and the CPU reset vector address is set to 0x00000000, but other addresses may be used according to the actual situation. And allocating an address space of the on-chip ROM on an address bus, wherein the initial address of the address space can be consistent with the address of the CPU reset vector or not, and the specific selection is determined according to the design requirement of the chip. According to the requirement of the chip on the on-chip RAM, one on-chip RAM or a plurality of on-chip RAMs are configured for the chip, and address space is distributed for the on-chip RAMs. If the RAM is a plurality of on-chip RAMs, one of the on-chip RAMs is selected as a main RAM and is used when an address mapping function is used. When allocating address spaces for the on-chip ROM and the on-chip RAM, the allocation is performed in combination with the type of the selected CPU, because the current CPU generally adopts a delayed Memory model, and some CPUs perform area division on the bus address space by default and configure corresponding Memory access types for the areas.
Further, the present application designs an on-chip RAM mapping register for mapping the on-chip RAM address space to the CPU reset vector address. In the chip design, when the initial address of the on-chip ROM is consistent with the address of the CPU reset vector, the default value of the mapping register indicates that the on-chip RAM mapping function is not enabled, when the register enables the RAM mapping function, the initial address of the on-chip RAM is mapped to the address of the CPU reset vector, and when the address of the CPU reset vector and the address of the on-chip RAM size space behind the address of the CPU reset vector are accessed, the accessed content is the content of the on-chip RAM, but not the content of the on-chip ROM. In the chip design, when the on-chip ROM initial address is inconsistent with the CPU reset vector address, the on-chip RAM mapping register default value is used for mapping the on-chip ROM initial address to the CPU reset vector address, when the register enables the RAM mapping function, the on-chip RAM initial address is mapped to the CPU reset vector address, and the function that the on-chip ROM initial address is mapped to the CPU reset vector address is cancelled.
For example, referring to fig. 2, fig. 2 is a specific address mapping schematic diagram disclosed in the embodiment of the present application, in fig. 2, a start address of a ROM is consistent with a CPU reset vector address, referring to fig. 3, fig. 3 is another specific address mapping schematic diagram disclosed in the embodiment of the present application, in fig. 3, the start address of the ROM is not consistent with the CPU reset vector address.
In addition, the method and the device operate a preset on-chip ROM control register after mapping the initial address of the on-chip RAM to the CPU reset vector address so as to close the power supply and the clock of the on-chip ROM.
The preset on-chip ROM control register is reset to a default value when the SOC chip is subjected to cold reset, and the default value indicates that the power supply and the clock of the on-chip ROM are enabled.
That is, the present application designs an on-chip ROM control register for controlling the power (i.e., power) and clock (i.e., clock) of the on-chip ROM, with default values indicating that the power and clock are enabled. The register has two functions, one is that when power and clock are not enabled, the on-chip ROM cannot be accessed, and the content of the on-chip ROM cannot be read, because the BootROM program of the chip is solidified in the on-chip ROM, and is the trust root of the whole chip and is the safe base stone of the chip; second, when power and clock are not enabled, the on-chip ROM generates no power consumption, which reduces the power consumption of the entire chip, which is particularly important in low power chip design.
It can be understood that, when the chip reset function is designed, the effect of the chip reset function on the on-chip RAM mapping function register and the on-chip ROM control register is different for different reset type designs. When the cold reset occurs, the on-chip RAM map register and the on-chip ROM control register are reset to default values, and the functions controlled by the registers are reset to default states. When the non-cold reset occurs, the values set by the on-chip RAM mapping register and the on-chip ROM control register are saved and not reset to the default values, and the functions controlled by the functions also keep the current states and are not reset to the default states.
Step S13: and when the SOC chip is not in cold reset, reading from the initial address of the on-chip RAM and executing the reset processing program so as to perform corresponding reset processing.
In a specific implementation manner, the reset processing program is executed, a register value of a reset state register is read in the execution process, a current reset type is judged based on the register value, and a reset processing subroutine corresponding to the reset type is executed according to the reset type to perform corresponding reset processing.
In addition, in the embodiment of the application, when the SOC chip is subjected to cold reset, a BootROM program is read and executed from the initial address of the on-chip ROM; and after the BootROM program is executed, executing a Bootlloader program, and in the process of executing the BootROM program, starting from the initial address of the on-chip RAM, writing a reset processing program into the on-chip RAM, and mapping the initial address of the on-chip RAM to the CPU reset vector address.
It can be understood that, according to all the reset types of non-cold reset supported in the chip design, the present application writes a reset processing program, in the reset processing program, the type of the current reset is judged by reading the chip reset state register, and then the branch processing code of the reset type is skipped to process. The reset processing program in the embodiment of the application is placed from the initial address of the on-chip RAM, and the entry address of the reset processing program is ensured to be consistent with the address of the CPU reset vector. In addition, in the Bootloader program, in the chip initialization stage, the reset processing program code is copied to the initial address of the on-chip RAM and the subsequent address space, and after copying is completed, the on-chip RAM address space is mapped to the CPU reset vector address through the on-chip RAM mapping function register. The power and clock of the on-chip ROM are then turned off by operating the on-chip ROM control register.
For example, referring to fig. 4, an embodiment of the present application discloses a schematic processing flow diagram of a chip Boot after reset occurs. In the design of an SOC chip, a mechanism for mapping an on-chip RAM address space to a reset vector address space of a CPU is designed, the mechanism is controlled by a register, and after the mapping mechanism takes effect, the mapping mechanism can only be reset by cold reset and cannot be reset by other types of reset. In addition, a register is set for the on-chip ROM to control its power and clock, the default value of the register is the power and clock of the enable ROM, and similarly, after the register closes the power and clock of the ROM, it can only be reset by cold reset and can not be reset by other types of reset. When the chip generates cold reset, the CPU starts reading instructions from a reset vector and executes the instructions, the BootROM program starts executing, after the execution is finished, the next-level Bootloader program is skipped to execute, in the Bootloader program, corresponding reset processing programs are written in the initial address of the RAM, the RAM address space mapping mechanism is enabled through the operation mapping register, simultaneously, the power and clock of the ROM are closed through the ROM register, and after the chip generates reset except the cold reset, the CPU starts reading instructions from the initial address of the RAM and executes the instructions, namely, executes the reset processing programs written in the front of the initial address of the RAM. After the chip generates cold reset, the CPU reads and executes instructions from the start address of the ROM, that is, executes the BootROM program.
Therefore, in the embodiment of the application, a reset processing program is written into the on-chip RAM from the initial address of the on-chip RAM, the initial address of the on-chip RAM is mapped to the CPU reset vector address, and when the SOC chip is not in cold reset, the reset processing program is read from the initial address of the on-chip RAM and executed so as to perform corresponding reset processing. That is, in the embodiment of the present application, the address space of the on-chip RAM is mapped to the address space of the CPU reset vector, and the reset processing program is written in the start position of the on-chip RAM. Because the content in the RAM can be modified, after the chip is subjected to tape-out and chip-back, different reset processing programs can be repeatedly written into the RAM for debugging according to the chip debugging requirement, and a final deliverable program is found out.
Moreover, after the on-chip RAM is mapped, the power and clock of the on-chip ROM can be closed, so that the power consumption of the chip is saved, and the safety of the content in the ROM is guaranteed.
Referring to fig. 5, an embodiment of the present application discloses an SOC chip reset processing apparatus, including:
a reset handler writing module 11, configured to write a reset handler into the on-chip RAM starting from an initial address of the on-chip RAM;
a RAM address mapping module 12, configured to map an initial address of the on-chip RAM to a CPU reset vector address;
the SOC chip reset processing module 13 is configured to, when the SOC chip is not in cold reset, start reading from the start address of the on-chip RAM and execute the reset processing program, so as to perform corresponding reset processing.
Therefore, in the embodiment of the application, a reset processing program is written into the on-chip RAM from the initial address of the on-chip RAM, the initial address of the on-chip RAM is mapped to the CPU reset vector address, and when the SOC chip is not in cold reset, the reset processing program is read from the initial address of the on-chip RAM and executed so as to perform corresponding reset processing. That is, in the embodiment of the present application, the address space of the on-chip RAM is mapped to the address space of the CPU reset vector, and the reset processing program is written in the start position of the on-chip RAM. Because the content in the RAM can be modified, after the chip is subjected to tape-out and chip-back, different reset processing programs can be repeatedly written into the RAM for debugging according to the chip debugging requirement, and a final deliverable program is found out.
The SOC chip reset processing module 13 is specifically configured to execute the reset processing program, read a register value of a reset status register in the execution process, determine a current reset type based on the register value, and execute a reset processing subroutine corresponding to the reset type according to the reset type to perform corresponding reset processing.
The RAM address mapping module 12 is specifically configured to operate a preset on-chip RAM mapping register, so as to map a starting address of the on-chip RAM to a CPU reset vector address.
The preset on-chip RAM mapping register is reset to a default value when the SOC chip is subjected to cold reset; if the initial address of an on-chip ROM of the SOC chip is consistent with the CPU reset vector address, the default value of the preset on-chip RAM mapping register indicates that the initial address of the on-chip RAM is not mapped; and if the starting address of the on-chip ROM is inconsistent with the CPU reset vector address, the default value of the preset on-chip RAM mapping register represents that the starting address of the on-chip ROM is mapped to the CPU reset vector address.
Further, the apparatus is further configured to: when the SOC chip is in cold reset, reading from the initial address of the on-chip ROM and executing a BootROM program; and after the BootROM program is executed, executing a Bootlloader program, and in the process of executing the BootROM program, starting from the initial address of the on-chip RAM, writing a reset processing program into the on-chip RAM, and mapping the initial address of the on-chip RAM to the CPU reset vector address.
Furthermore, the device also comprises a power supply and clock control module of the ROM, which is used for operating a preset on-chip ROM control register to turn off the power supply and the clock of the on-chip ROM.
The preset on-chip ROM control register is reset to a default value when the SOC chip is subjected to cold reset, and the default value indicates that the power supply and the clock of the on-chip ROM are enabled.
Referring to fig. 6, an embodiment of the present application discloses an SOC chip including a processor 21 and a memory 22; wherein, the memory 22 is used for saving computer programs; the processor 21 is configured to execute the computer program, and the SOC chip reset processing method disclosed in the foregoing embodiment.
For the specific process of the above SOC chip reset processing method, reference may be made to the corresponding contents disclosed in the foregoing embodiments, and details are not repeated here.
Further, an embodiment of the present application also discloses a computer-readable storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the SOC chip reset processing method disclosed in the foregoing embodiment.
For the specific process of the above SOC chip reset processing method, reference may be made to the corresponding contents disclosed in the foregoing embodiments, and details are not repeated here.
The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
The SOC chip reset processing method, the SOC chip reset processing apparatus, the SOC chip and the medium provided by the present application are introduced in detail, and a specific example is applied in the present application to explain the principle and the implementation of the present application, and the description of the above embodiment is only used to help understanding the method and the core idea of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (10)
1. An SOC chip reset processing method is characterized by comprising the following steps:
writing a reset processing program into an on-chip RAM from an initial address of the on-chip RAM;
mapping an initial address of the on-chip RAM to a CPU reset vector address;
and when the SOC chip is not in cold reset, reading from the initial address of the on-chip RAM and executing the reset processing program so as to perform corresponding reset processing.
2. The SOC chip reset processing method according to claim 1, wherein executing the reset processing program to perform a corresponding reset process includes:
and executing the reset processing program, reading the register value of the reset state register in the executing process, judging the reset type of the current reset based on the register value, and executing the reset processing subprogram corresponding to the reset type according to the reset type so as to perform corresponding reset processing.
3. The SOC chip reset processing method of claim 1, wherein the mapping the start address of the on-chip RAM to a CPU reset vector address comprises:
operating a preset on-chip RAM mapping register to map a starting address of the on-chip RAM to a CPU reset vector address.
4. The SOC chip reset processing method of claim 3, wherein the preset on-chip RAM mapping register is reset to a default value when a cold reset occurs to the SOC chip;
if the initial address of an on-chip ROM of the SOC chip is consistent with the CPU reset vector address, the default value of the preset on-chip RAM mapping register indicates that the initial address of the on-chip RAM is not mapped; and if the starting address of the on-chip ROM is inconsistent with the CPU reset vector address, the default value of the preset on-chip RAM mapping register represents that the starting address of the on-chip ROM is mapped to the CPU reset vector address.
5. The SOC chip reset processing method of claim 4, further comprising:
when the SOC chip is in cold reset, reading from the initial address of the on-chip ROM and executing a BootROM program;
and after the BootROM program is executed, executing a Bootlloader program, and in the process of executing the BootROM program, starting from the initial address of the on-chip RAM, writing a reset processing program into the on-chip RAM, and mapping the initial address of the on-chip RAM to the CPU reset vector address.
6. The SOC chip reset processing method of claim 1, further comprising, after said mapping the start address of the on-chip RAM to a CPU reset vector address:
the preset on-chip ROM control register is operated to turn off the power and clock of the on-chip ROM.
7. The SOC chip reset processing method of claim 6, wherein the preset on-chip ROM control register is reset to a default value when a cold reset occurs to the SOC chip, the default value indicating that power and clocks of the on-chip ROM are enabled.
8. An SOC chip reset processing apparatus, comprising:
a reset processing program writing module for writing a reset processing program into the on-chip RAM from an initial address of the on-chip RAM;
the RAM address mapping module is used for mapping the initial address of the on-chip RAM to a CPU reset vector address;
and the SOC chip reset processing module is used for reading from the initial address of the on-chip RAM and executing the reset processing program to perform corresponding reset processing when the SOC chip is not in cold reset.
9. An SOC chip, comprising:
a memory for storing a computer program;
a processor for executing the computer program to implement the SOC chip reset processing method according to any one of claims 1 to 7.
10. A computer-readable storage medium storing a computer program which, when executed by a processor, implements the SOC chip reset processing method according to any one of claims 1 to 7.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116932334A (en) * | 2023-09-15 | 2023-10-24 | 苏州利氪科技有限公司 | Abnormal reset monitoring method and device for multi-core micro control unit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116932334A (en) * | 2023-09-15 | 2023-10-24 | 苏州利氪科技有限公司 | Abnormal reset monitoring method and device for multi-core micro control unit |
| CN116932334B (en) * | 2023-09-15 | 2023-11-28 | 苏州利氪科技有限公司 | Abnormal reset monitoring method and device for multi-core micro control unit |
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