CN114416408A

CN114416408A - Interrupt processing method and device

Info

Publication number: CN114416408A
Application number: CN202111520281.XA
Authority: CN
Inventors: 刘莹; 李振宇; 李泓霖
Original assignee: Phytium Technology Co Ltd
Current assignee: Phytium Technology Co Ltd
Priority date: 2021-12-13
Filing date: 2021-12-13
Publication date: 2022-04-29

Abstract

An interrupt processing method and device relate to the technical field of computers and solve the problems of high hardware cost, low monitoring efficiency and poor compatibility when monitoring whether a host crashes or crashes. The interrupt processing method is applied to a host, and the host comprises the following steps: the device comprises M processor cores and N virtual timers, wherein the M processor cores correspond to the N virtual timers, M is a positive integer, and N is an integer which is greater than or equal to 1 and less than or equal to M. The specific scheme comprises the following steps: the interrupt processing device registers a callback function corresponding to each processor core, generates a target interrupt request under the condition that the target virtual timer is overtime in the N virtual timers, and acquires the abnormal operation information of the M processor cores according to the interrupt processing function corresponding to the target interrupt request and the callback functions corresponding to the M processor cores. And each callback function is used for storing the running exception information of the corresponding processor core after being called back.

Description

Interrupt processing method and device

Technical Field

The present application relates to the field of computer technologies, and in particular, to an interrupt processing method and apparatus.

Background

With the development of science and technology, Operating Systems (OS) such as Windows and Linux are applied more and more widely in various fields. The operating system is system software of a host, the processor core is a hardware resource of the host, and the operating system runs on the processor core to execute tasks of the host.

Currently, when an OS runs on a processor core, a problem of a host crash down may occur. When the host crashes and crashes, the host acquires running abnormal information by triggering a fast interrupt request (FIQ).

In the prior art, the host may monitor whether the crash is down by using a watchdog circuit included in its hardware resources. However, this solution is costly in hardware. Or, the host may monitor whether the host crashes or crashes by using an external watchdog monitoring device connected to the host. However, the scheme has a complex flow, which results in low monitoring efficiency.

Disclosure of Invention

The application provides an interrupt processing method and device, and solves the problems of high hardware cost, low monitoring efficiency and poor compatibility when monitoring whether a host crashes or crashes.

In order to achieve the purpose, the technical scheme is as follows:

in a first aspect, the present application provides an interrupt processing method, where the method is applied to a host, and the host may include: the device comprises M processor cores and N virtual timers, wherein the M processor cores correspond to the N virtual timers, M is a positive integer, and N is an integer which is greater than or equal to 1 and less than or equal to M. The method comprises the following steps: the interrupt processing device registers a callback function corresponding to each processor core, generates a target interrupt request under the condition that the target virtual timer is overtime in the N virtual timers, and acquires the abnormal operation information of the M processor cores according to the interrupt processing function corresponding to the target interrupt request and the callback functions corresponding to the M processor cores. And each callback function is used for storing the running exception information of the corresponding processor core after being called back.

Therefore, the running state of each processor core of the host is monitored by using the N virtual timers corresponding to the M processor cores in the host to replace a watchdog circuit or external watchdog monitoring equipment, so that the hardware cost is reduced, the running state of the corresponding processor core is monitored by using the virtual timers, the monitoring function is realized by a software control method, and the monitoring efficiency and the compatibility of the host are improved.

In one possible implementation manner of the present application, the interrupt processing method may further include: the interrupt processing device performs interrupt configuration on each virtual timer in the N virtual timers, and the configured virtual timers are used for monitoring the running state of the corresponding processor cores.

In a possible implementation manner of the present application, the performing, by the interrupt processing apparatus, an interrupt configuration on each virtual timer of the N virtual timers specifically includes: the interrupt processing device enables each virtual timer, enables each virtual timer to interrupt, registers an interrupt number corresponding to each virtual timer, establishes a corresponding relation between the registered interrupt number and an interrupt type, and registers an abnormal information address corresponding to each processor core, wherein the abnormal information address is used for storing running abnormal information of the corresponding processor core. In this case, the generating, by the interrupt processing apparatus, a target interrupt request when a target virtual timer is overtime in the N virtual timers specifically includes: the interrupt processing device generates a target interrupt request when the target virtual timer is overtime, the target virtual timer is enabled, and the target virtual timer is interrupt enabled.

In a possible implementation manner of the present application, registering, by the interrupt processing apparatus, a callback function corresponding to each processor core specifically includes: and the interrupt processing device calls a registration function and registers the address of the callback function corresponding to each processor core.

In a possible implementation manner of the present application, the generating of the target interrupt request by the interrupt processing apparatus specifically includes: the interrupt processing device acquires a target interrupt number corresponding to the target virtual timer, acquires a target interrupt type corresponding to the target interrupt number according to a corresponding relation between a pre-stored interrupt number and an interrupt type, and generates a target interrupt request according to the target interrupt type.

In a possible implementation manner of the present application, the acquiring, by the interrupt processing device, the abnormal operation information of the M processor cores according to the interrupt processing function corresponding to the target interrupt request and the callback function corresponding to the M processor cores specifically includes: the interrupt processing device acquires an interrupt processing function corresponding to the target interrupt request, calls a trigger interrupt function based on the interrupt processing function, and acquires the abnormal operation information of the M processor cores based on the trigger interrupt function and callback functions corresponding to the M processor cores.

In a possible implementation manner of the present application, the acquiring, by the interrupt processing device, the abnormal operation information of the M processor cores according to the interrupt processing function corresponding to the target interrupt request and the callback function corresponding to the M processor cores specifically includes: and the interrupt processing device acquires the abnormal operation information of each processor core according to the interrupt processing function and the callback function corresponding to each processor core in the M processor cores. Or the interrupt processing device acquires the running exception information corresponding to each processor core in the processor cores corresponding to the target virtual timer according to the interrupt processing function and the callback function corresponding to each processor core in the processor cores corresponding to the target virtual timer.

In one possible implementation of the present application, the host may further include an interrupt controller. The generating, by the interrupt processing apparatus, the target interrupt request when the target virtual timer is overtime in the N virtual timers may specifically include: and under the condition that the target virtual timer is overtime, generating an interrupt message by a target processor core corresponding to the target virtual timer, sending the interrupt message to an interrupt controller, generating a target interrupt request by the interrupt controller according to the interrupt message, wherein the interrupt message comprises a target interrupt number corresponding to the target virtual timer. Or when M is greater than 1 and M processor cores comprise a master core and at least one slave core, under the condition that the target virtual timer is overtime, the target processor core corresponding to the target virtual timer generates interrupt messages and sends the interrupt messages to the master core, the master core sends the interrupt messages to the interrupt controller after receiving all the interrupt messages, and the interrupt controller generates a target interrupt request according to all the interrupt messages.

In a second aspect, an interrupt handling apparatus is provided, where the interrupt handling apparatus is located in a host, and the host may include: the device comprises M processor cores and N virtual timers, wherein the M processor cores correspond to the N virtual timers, M is a positive integer, and N is an integer which is greater than or equal to 1 and less than or equal to M. The interrupt processing means may include: the register unit is used for registering the callback function corresponding to each processor core, and each callback function is used for acquiring the abnormal operation information of the corresponding processor core after being recalled; the generating unit is used for generating a target interrupt request under the condition that the target virtual timer is overtime in the N virtual timers; and the acquisition unit is used for acquiring the abnormal operation information of the M processor cores according to the interrupt processing function corresponding to the target interrupt request generated by the generation unit and the callback functions corresponding to the M processor cores registered by the registration unit.

In one possible implementation manner of the present application, the interrupt processing apparatus further includes: and a configuration unit. And the configuration unit is used for performing interrupt configuration on each virtual timer in the N virtual timers, and the configured virtual timers are used for monitoring the running state of the corresponding processor cores.

In a possible implementation manner of the present application, the configuration unit is specifically configured to: enabling each virtual timer, enabling each virtual timer to interrupt, registering an interrupt number corresponding to each virtual timer, establishing a corresponding relation between the registered interrupt number and an interrupt type, and registering an abnormal information address corresponding to each processor core, wherein the abnormal information address is used for storing running abnormal information of the corresponding processor core. A generating unit, specifically configured to: and generating a target interrupt request under the conditions that the target virtual timer is overtime, the target virtual timer is enabled and the target virtual timer is interrupt enabled.

In a possible implementation manner of the present application, the registration unit is specifically configured to: and calling a registration function, and registering the address of the callback function corresponding to each processor core.

In a possible implementation manner of the present application, the generating unit is specifically configured to: acquiring a target interrupt number corresponding to a target virtual timer; acquiring a target interrupt type corresponding to the target interrupt number according to a corresponding relation between the pre-stored interrupt number and the interrupt type; and generating a target interrupt request according to the target interrupt type.

In a possible implementation manner of the present application, the obtaining unit is specifically configured to: acquiring an interrupt processing function corresponding to the target interrupt request; based on the interrupt processing function, calling a trigger interrupt function; and acquiring the abnormal operation information of the M processor cores based on the triggering interrupt function and the callback functions corresponding to the M processor cores.

In a possible implementation manner of the present application, the obtaining unit is specifically configured to: and acquiring the abnormal operation information of each processor core according to the interrupt processing function and the callback function corresponding to each processor core in the M processor cores. Or acquiring the running exception information corresponding to each processor core in the processor cores corresponding to the target virtual timer according to the interrupt processing function and the callback function corresponding to each processor core in the processor cores corresponding to the target virtual timer.

In a third aspect, an interrupt handling apparatus is provided that includes a memory and a processor. The memory is coupled to the processor. The memory is for storing computer program code, the computer program code including computer instructions. When the processor executes the computer instructions, the interrupt handling means performs an interrupt handling method as in the first aspect and any possible implementation thereof.

In a fourth aspect, a chip system is provided, which is applied to an interrupt processing apparatus. The chip system includes one or more interface circuits, and one or more processors. The interface circuit and the processor are interconnected through a line; the interface circuit is configured to receive signals from a memory of the interrupt processing device and to send signals to the processor, the signals including computer instructions stored in the memory. When the processor executes the computer instructions, the interrupt handling means performs an interrupt handling method as in the first aspect and any possible implementation thereof.

In a fifth aspect, a computer-readable storage medium is provided, which comprises computer instructions that, when run on an interrupt handling apparatus, cause the interrupt handling apparatus to perform an interrupt handling method as in the first aspect and any one of its possible implementations.

In a sixth aspect, the present application provides a computer program product comprising computer instructions that, when run on an interrupt handling apparatus, cause the interrupt handling apparatus to perform an interrupt handling method as in the first aspect and any one of its possible implementations.

Reference may be made in detail to the second to sixth aspects and various implementations of the first aspect in this application; moreover, for the beneficial effects of the second aspect to the sixth aspect and various implementation manners thereof, reference may be made to beneficial effect analysis in the first aspect and various implementation manners thereof, and details are not described here.

These and other aspects of the present application will be more readily apparent from the following description.

Drawings

Fig. 1 is a schematic structural diagram of an interrupt processing apparatus according to an embodiment of the present disclosure;

fig. 2 is a schematic structural diagram of a virtual timer control register according to an embodiment of the present application;

FIG. 3 is a diagram illustrating a software architecture of a host according to an embodiment of the present application;

fig. 4 is a flowchart illustrating an interrupt processing method according to an embodiment of the present application;

fig. 5A is a schematic view of a scenario of an interrupt processing method according to an embodiment of the present application;

fig. 5B is a second scenario of an interrupt processing method according to the present application;

fig. 6 is a schematic structural diagram of an interrupt processing apparatus according to an embodiment of the present application;

fig. 7 is a second schematic structural diagram of an interrupt processing apparatus according to an embodiment of the present application.

Detailed Description

In this application, the words "exemplary" or "such as" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "e.g.," is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the word "exemplary" or "such as" is intended to present concepts related in a concrete fashion. In the description of the embodiments of the present application, "at least one" means one or more, and "a plurality" means two or more unless otherwise specified.

Timer interrupts refer to interrupts triggered by a timer overflow. The interruption is when the program is normally executed, an emergency occurs, the processor of the host stops the execution of the current program, the processing of the emergency is carried out, and the original program is returned to the interrupted position for continuous execution after the processing is finished.

In the related art, when the host crashes and crashes, the host can acquire abnormal information by triggering the FIQ. Specifically, the host may adopt the following two schemes to collect the exception information.

In the first scheme, when the host operates normally, the processor core in the host sends a dog feeding signal to the watchdog circuit in the host in a timing mode. And after the watchdog circuit receives the dog feeding signal at regular time, the timer in the watchdog circuit is cleared. When the host crashes and crashes, the processor core cannot send a dog feeding signal to the watchdog circuit, so that a timer in the watchdog circuit overflows, and the watchdog circuit sends a reset signal to the processor core. After receiving the reset signal, the processor core generates an FIQ and executes an interrupt process corresponding to the FIQ, for example, collects the running exception information of the processor core in the host. In the first scheme, the host monitors the running state of the host through a watchdog circuit, namely, whether the host runs normally or crashes down is detected.

However, in the first scheme, the host needs to rely on a watchdog circuit to detect whether the crash occurs, the hardware cost is high, and the compatibility of the host is poor.

In the second scheme, if the host does not include the watchdog circuit, the host can be connected with an external watchdog monitoring device, and the external watchdog monitoring device is utilized to realize the function of the watchdog circuit, so that whether the host crashes or crashes is monitored.

The second scheme described above, although improving the compatibility of the host compared to the first scheme. However, the second scheme has a complicated process, consumes a large amount of human resources, and results in low monitoring efficiency.

In summary, in the related art, there are problems of high hardware cost, low monitoring efficiency, and poor compatibility when monitoring whether the host crashes or crashes.

In order to solve the above technical problems, embodiments of the present application provide an interrupt processing method and apparatus, in which N virtual timers corresponding to M processor cores in a host are used to replace a watchdog circuit or an external watchdog monitoring device to monitor an operating state of each processor core of the host, so that not only is hardware cost reduced, but also the virtual timers are used to monitor the operating state of the corresponding processor cores, thereby implementing a monitoring function by a software control method, and improving monitoring efficiency and host compatibility.

The execution main body of the interrupt processing method provided by the embodiment of the application is an interrupt processing device. The interrupt processing device may be a host or a chip in the host.

In some embodiments, the host may be a terminal device, a server, a cloud computing platform, or the like that includes an interrupt handling apparatus. The terminal device may be a mobile phone (mobile phone), a tablet computer, a notebook computer, a palm computer, a computer, or the like.

The host may include the elements included in the interrupt handling apparatus shown in figure 1. The hardware structure of the host will be described below by taking the interrupt processing apparatus shown in fig. 1 as an example.

As shown in fig. 1, the interrupt handling means may include a processor 11, a memory 12, a communication interface 13, a bus 14, and an interrupt controller (GIC) 15. The processor 11, the memory 12, and the communication interface 13 may be connected by a bus 14, and the processor 11 and the interrupt controller 15 may be connected by the bus 14.

The processor 11 is a control center of the interrupt processing apparatus, and may be a general processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of the program according to the present embodiment.

As an embodiment, the type of the processor 11 is various, and the type of the processor 11 may be distinguished by the CPU architecture of the processor 11, and one type of the processor 11 corresponds to one CPU architecture. The CPU architecture of the processor 11 is different and the instruction set supported by the processor 11 is different. The CPU architecture may include: an X86 architecture, a Reduced Instruction Set Computer (RISC) processor (ARM) architecture, and the like, and the embodiments of the present application are not particularly limited herein. Wherein, when the CPU architecture is the X86 architecture, the processor 11 supports the X86 instruction set, and when the CPU architecture is the ARM architecture, the processor 11 supports the ARM instruction set. When the processor 11 supports the X86 instruction set, the interrupt handler may install a Windows system. When the processor 11 supports the ARM instruction set, the interrupt processing device may be installed with Linux, Windows, or the like.

As an example, the processor 11 may be a single-core processor (single-CPU) or a multi-core processor (multi-CPU). Processor 11 may refer herein to one or more devices, circuits, and/or processing cores that process data (e.g., computer instructions). When the processor 11 is a single-core processor, the processor 11 includes one processor core. When the processor 11 is a multi-core processor, the processor 11 includes a plurality of processor cores, which may include a master core and the rest are slave cores. Each processor core includes a Processing Element (PE), and a set of timers. Wherein the processing unit is a processing center of the processor 11. The set of timers may include a physical timer (physical timer), a virtual timer (virtual timer), and the like. The running state of the corresponding processor core can be monitored by utilizing the virtual timer in the processor core. The processor 11 is illustrated in fig. 1 as including one processor core.

For example, assuming that the interrupt processing apparatus may include M processor cores, where M is a positive integer, each processor core may include a virtual timer, and N of the M virtual timers may be used to monitor the operating states of the M processor cores, that is, the M processor cores correspond to the N virtual timers, where N is an integer greater than or equal to 1 and less than or equal to M. When N is equal to M, the running state of each processor core is monitored by a virtual timer in the processor core. When N is 1, the running states of the M processor cores are uniformly monitored by any one of the M virtual timers. When N is larger than 1 and smaller than M, each virtual timer in N virtual timers is utilized to monitor the running states of two or more processor cores.

For one embodiment, the processor core may further include a register associated with the virtual timer. For example, the processor core may include: a virtual timer value register (virtual timer value register), a virtual timer control register (virtual timer control register). As shown in table 1, is information of the relevant register of the virtual timer.

TABLE 1

Name (R)	Width of	Type (B)	Description of the invention
				CNTV_TVAL_EL0	32 bits	RW	Virtual timer value register
CNTV_CTL_EL0	32 bits	RW	Virtual timer control register

The virtual timer value register is a 32-bit register for holding the timer value of the virtual timer. And the virtual timer value register is a signed down counter or alternatively, the virtual timer value register may be an up counter. When the virtual timer value register is a down counter, the timer value in the virtual timer value register is decremented with each increment of the corresponding counter, and the virtual timer interrupt may be triggered when the timer value is less than zero. When the virtual timer value register is an up counter, the timer value in the virtual timer value register is incremented with each increment of the corresponding counter, and when the timer value is greater than a preset value, a virtual timer interrupt may be triggered.

It is noted that in the present embodiment, all values in the virtual timer value register are signed and stored in the form of a standard two's complement. After the virtual timer is triggered, the timer value in the virtual timer value register continues to decrease or increase downwards, and at this time, the time length after the virtual timer is triggered can be obtained by reading the timer value.

The virtual timer control register is used for controlling the virtual timer, and is a 32-bit register including bits 0 to 31. Fig. 2 is a schematic diagram of a virtual timer control register.

As shown in fig. 2, bit 0 in the virtual timer control register is ENABLE, which is a virtual timer ENABLE bit, and when bit 0 is 0, it indicates that the virtual timer is disabled, and when bit 0 is 1, it indicates that the virtual timer is enabled.

The 1 st bit in the virtual timer control register is IMASK, which is a virtual timer interrupt mask bit, when the 1 st bit is 0, it indicates that the virtual timer interrupt is not masked, and when the 1 st bit is 1, it indicates that the virtual timer interrupt is masked.

The 2 nd bit in the virtual timer control register is ISTATUS, which is a virtual timer interrupt enable bit, when the 2 nd bit is 0, the virtual timer interrupt is indicated to be forbidden, and when the 2 nd bit is 1, the virtual timer interrupt enable is indicated.

The memory 12 may be, but is not limited to, a read-only memory (ROM) or other type of static storage device that may store static information and instructions, a Random Access Memory (RAM) or other type of dynamic storage device that may store information and instructions, an electrically erasable programmable read-only memory (EEPROM), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer.

In a possible implementation, the memory 12 may be present separately from the processor 11, and the memory 12 may be connected to the processor 11 via a bus 14 for storing instructions or program code. The processor 11 can implement the interrupt processing method provided in the following embodiments of the present application when calling and executing the instructions or program codes stored in the memory 12.

In another possible implementation, the memory 12 may also be integrated with the processor 11.

The communication interface 13 is configured to connect the interrupt processing apparatus with other devices through a communication network, where the communication network may be an ethernet, a Radio Access Network (RAN), a Wireless Local Area Network (WLAN), or the like. The communication interface 13 may comprise a receiving unit for receiving data and a transmitting unit for transmitting data.

The bus 14 may be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, an extended ISA (enhanced industry standard architecture) bus, or the like. The bus may be divided into an address bus, a data bus, a control bus, etc.

The interrupt controller 15 is mainly configured to generate an interrupt request and execute a corresponding interrupt processing operation according to the interrupt request. The interrupt request may be a FIQ.

It is noted that the architecture shown in fig. 1 does not constitute a limitation of the interrupt handling means, which may comprise more or less components than those shown in fig. 1, or some components in combination, or a different arrangement of components than those shown in fig. 1.

The host-installed software system may employ an X86 architecture, an ARM architecture, or the like. In the embodiment of the present application, a Linux system with an ARM architecture is taken as an example to exemplarily explain a software structure of a host.

In some embodiments, as shown in fig. 3, the Linux system may be divided into four layers, which are an application layer, an operating system layer, a virtual machine layer (HYP), and a security monitoring layer from top to bottom.

The application layer, also called the user layer, may include a series of application packages, as well as reliability services (trusted services).

As shown in fig. 3, the application package may include applications such as a camera, gallery, calendar, phone call, map, music, short message, etc.

The operating system layer may include a plurality of general purpose operating systems (rich OS), and a reliable operating system. The general operating system may include a Linux operating system, and is configured to provide all functions of the host to the upper layer application.

The virtual machine layer may include a virtual machine monitor (hypervisor). The virtual machine monitor is used to establish the software, firmware, hardware, etc. needed to execute the virtual machine.

The security monitoring layer may include a security manager (security monitor).

It should be noted that, in the embodiment of the present application, the ARM architecture may include four privilege modes, and the four privilege modes are respectively indicated by EL0, EL1, EL2, and EL 3. The EL3 model has the highest operation authority, the EL0 model has the lowest operation authority, and the high and low operation authority can influence the access of resources.

The EL0 mode can run application programs, the EL1 mode can run an operating system, the EL2 mode runs virtual machines, and the EL3 mode runs security management. That is, the EL0 mode corresponds to an application layer, the EL1 mode corresponds to an operating system layer, the EL2 mode corresponds to a virtual machine layer, and the EL3 mode corresponds to a security monitoring layer.

The virtual timer value register and the virtual timer control register described above in fig. 1 may be accessed from the EL0 mode or may not be accessed from the EL0 mode. The EL0VTEN bit of the CNTKCTL _ EL1 register determines whether it can be accessed from EL0 mode. When the EL0VTEN bit of the CNTKCTL _ EL1 register is set to 1, the virtual timer value register, the virtual timer control register, can be accessed from the EL0 mode.

Based on the introduction of the hardware architecture and the software architecture of the host, an interrupt processing method is provided in the embodiments of the present application, and the interrupt processing method provided in the embodiments of the present application is described below with reference to the accompanying drawings.

As shown in fig. 4, the interrupt handling method may include the following steps 401 to 403.

401. The host registers the callback function corresponding to each processor core.

After the host is started, a callback function corresponding to each processor core in the M processor cores included in the host may be registered, where the callback function is used to obtain running exception information of the corresponding processor core after being recalled, that is, used to obtain a last-minute word of the processor core after being recalled, that is, the running exception information refers to information when the processor core runs abnormally.

In some embodiments, the host may call a registration function to register the address of the callback function corresponding to each processor core. The registration function may be a Security Monitor Call (SMC) function.

Optionally, in this embodiment of the application, in order to monitor the operating state of the processor core by using the virtual timer, so as to timely know whether the processor core crashes or crashes, interrupt configuration may be performed on each of the N virtual timers in the host in advance, so that the configured virtual timer is used to monitor the operating state of the corresponding processor core.

In a specific implementation, the performing interrupt configuration on each virtual timer of the N virtual timers may specifically include: enabling each virtual timer, enabling each virtual timer to interrupt, registering an interrupt number corresponding to each virtual timer, establishing a corresponding relation between the registered interrupt number and an interrupt type, and registering an abnormal information address corresponding to each processor core. And the abnormal information address is used for storing the running abnormal information of the corresponding processor core.

Enabling each virtual timer refers to setting the 0 th bit in the virtual timer control register corresponding to each virtual timer to 1.

Enabling each virtual timer interrupt refers to setting the 2 nd bit in the virtual timer control register corresponding to each virtual timer to 1.

Different interrupt numbers are usually used to distinguish different types of timers, and the interrupt numbers of the N virtual timers are the same. For example, the interrupt numbers corresponding to the N virtual timers may all be 27.

Establishing the corresponding relationship between the registered interrupt number and the interrupt type refers to binding each of the N virtual timers corresponding to the M processor cores in the host with the target interrupt type in advance. The target interrupt type may be an interrupt type of a high priority FIQ because of the higher urgency of an event in which the processor core crashes down.

402. And the host generates a target interrupt request when the target virtual timer is overtime in the N virtual timers.

Optionally, in this embodiment of the present application, the host may generate the target interrupt request when the target virtual timer is expired, and the target virtual timer is enabled and the target virtual timer is interrupt enabled.

Optionally, in this embodiment of the application, when the host generates the target interrupt request, the target interrupt number corresponding to the target virtual timer may be first obtained, and then the target interrupt type corresponding to the target interrupt number is obtained according to a correspondence between the pre-stored interrupt number and the interrupt type. The host may then generate a target interrupt request according to the target interrupt type.

Optionally, in this embodiment of the present application, the host may generate the target interrupt request in multiple ways, and this embodiment of the present application is not limited herein. As a possible implementation manner, in the case that the target virtual timer is overtime, the target processor core corresponding to the target virtual timer may generate an interrupt message and send the interrupt message to the interrupt controller. The interrupt controller generates a target interrupt request based on the received interrupt message. The interrupt message comprises a target interrupt number corresponding to the target virtual timer. As another possible implementation manner, when M is greater than 1 and M processor cores include one master core and at least one slave core, in the case that the target virtual timer is overtime, the target processor core corresponding to the target virtual timer may generate an interrupt message and send the interrupt message to the master core. The master core can send all interrupt messages to the interrupt controller after receiving all interrupt messages, and the interrupt controller generates a target interrupt request according to all interrupt messages.

It is to be understood that, in the embodiment of the present application, the target interrupt type may be a type of FIQ, and the target interrupt request may be a FIQ.

In addition, the time-out of the target virtual timer may be that a timing value of the target virtual timer is smaller than zero, or that the timing value of the target virtual timer is greater than a preset value, which is not limited herein.

For example, after the host starts, each of the N virtual timers may count with the system counter and assign a value to the virtual timer value register, i.e., store the timer value in the virtual timer value register. For each processor core, if the processor core runs normally in the running process, the processing unit in the processor core can send a dog feeding signal to the virtual timer corresponding to the processor core in a timing mode. After receiving the dog feeding signal of the processing unit, the virtual timer corresponding to the processor core can recover the virtual timer, that is, the timer value of the virtual timer value register is recovered to the initial value, and the timing with the system counter is restarted. If the processor core runs abnormally, the processing unit of the processor core cannot send a dog feeding signal to the virtual timer corresponding to the processor core at regular time, and the virtual timer corresponding to the processor core is caused to be overtime.

When a target processor core exists in M processor cores in the host and a target virtual timer corresponding to the target processor core is overtime, the target virtual timer corresponding to each target processor core can send overtime information to a processing unit of the target processor core.

After receiving the timeout information, the processing unit of the target processor core may generate an interrupt message including a target interrupt number corresponding to the target virtual timer if it is determined that the target virtual timer is enabled and the target virtual timer is interrupt enabled. Thereafter, the processing unit of the target processor core may send an interrupt message to the interrupt controller.

In one possible implementation, the processing unit of the target processor core may send the interrupt message directly to the interrupt controller.

In another possible implementation, the processing unit of the target processor core may send an interrupt message to a master core of the M processor cores (without sending if the target processor core is the master core). The master core may then uniformly send all interrupt messages to the interrupt controller after receiving the interrupt messages for all target processor cores. Compared with the mode, the mode only communicates with the interrupt controller through the main core, so that message interaction can be reduced, and unified management of interrupt messages can be realized.

After receiving an interrupt message sent by a processing unit in a target processor core, the interrupt controller can acquire a target interrupt number included in the interrupt message, and acquire a target interrupt type corresponding to the target interrupt number according to a pre-stored corresponding relationship between the interrupt number and the interrupt type. Thereafter, the interrupt controller may generate a target interrupt request according to the target interrupt type.

It should be noted that, in the embodiment of the present application, the execution of step 401 and the execution of step 402 have no precedence relationship. Step 401 may be executed first, then step 402 may be executed, or step 402 may be executed first, then step 401 may be executed, or step 401 and step 402 may be executed simultaneously, which is not particularly limited in this embodiment of the application.

403. And the host acquires the abnormal operation information of the M processor cores according to the interrupt processing function corresponding to the target interrupt request and the callback functions corresponding to the M processor cores.

After the host registers the callback function corresponding to each processor core and the interrupt controller generates the target interrupt request, the interrupt controller may execute the interrupt processing operation corresponding to the target interrupt request.

As a possible implementation, the interrupt controller may obtain an interrupt processing function corresponding to the target interrupt request, and call the trigger interrupt function based on the interrupt processing function. Then, the interrupt controller may obtain and store the running exception information of the M processor cores based on the trigger interrupt function and the callback functions corresponding to the M processor cores. Of course, the interrupt controller may also perform other interrupt handling operations, such as invoking self-refresh, etc. The interrupt processing function is used for executing the interrupt processing corresponding to the target interrupt request.

It will be appreciated that the above-described triggered interrupt function may be a software triggered interrupt function. When the target interrupt request is FIQ, the interrupt processing function may be a FIQ processing function. In this case, the interrupt controller may first call an FIQ processing function to process the FIQ, and may call software to trigger the interrupt function to generate a notification message corresponding to the M processor cores during the processing, where the notification message is used to notify each processor core to execute interrupt processing, and the notification message includes an address of a callback function corresponding to the processor core. After receiving the notification message sent by the interrupt controller, each processor core can stop running, and records running exception information of the processor core according to the address of the callback function, namely records the context when the processor core runs abnormally.

Optionally, in this embodiment of the application, the process of obtaining the abnormal operation information of the M processor cores according to the interrupt processing function corresponding to the target interrupt request and the callback functions corresponding to the M processor cores may be: and the interrupt controller acquires the abnormal operation information of each processor core according to the interrupt processing function and the callback function corresponding to each processor core in the M processor cores. Or, the interrupt controller may obtain the running exception information corresponding to each of the processor cores corresponding to the target virtual timer according to the interrupt processing function and the callback function corresponding to each of the processor cores corresponding to the target virtual timer. That is, when the target virtual timer times out, the interrupt controller may acquire the operation exception information of each of the M processor cores, or may acquire the operation exception information of each of the target processor cores. Compared with the two modes, the first mode obtains more comprehensive information, but the data processing pressure of the equipment is larger. The second way obtains less information but the data processing pressure of the device is less. In practical application, which way to acquire the abnormal operation information may be determined according to an actual scene.

According to the interrupt processing method provided by the embodiment of the application, the host registers the callback function corresponding to each processor core, generates the target interrupt request under the condition that the target virtual timer is overtime in the N virtual timers, and stores the abnormal operation information of the M processor cores according to the interrupt processing function corresponding to the target interrupt request and the callback functions corresponding to the M processor cores. Therefore, the running state of each processor core of the host is monitored by using the N virtual timers corresponding to the M processor cores in the host to replace a watchdog circuit or external watchdog monitoring equipment, so that the hardware cost is reduced, the running state of the corresponding processor core is monitored by using the virtual timers, the monitoring function is realized by a software control method, and the monitoring efficiency and the compatibility of the host are improved.

For example, in the embodiment of the present application, the interrupt processing apparatus may include M processor cores. When the interrupt processing apparatus includes one processor core, the processor in the interrupt processing apparatus is a single-core processor. When the interrupt processing apparatus includes two or more processor cores, the processor in the interrupt processing apparatus is a multicore processor. Each processor core in the interrupt handling apparatus includes a virtual timer. N is equal to M, and each virtual timer is used for monitoring the running state of the processor core corresponding to the virtual timer.

As shown in fig. 5A, assuming that the interrupt handling apparatus includes a plurality of processor cores, a plurality of virtual timers in the interrupt handling apparatus count with the system counter and store the recorded timing values in the virtual timer value registers. If the timing value corresponding to the target virtual timer is less than zero, the target virtual timer may send timeout information to the processing unit of the target processor core.

And the processing unit of the target processor core sends an interrupt message to the interrupt controller under the conditions of receiving the timeout information and determining that the target virtual timer is enabled and the target virtual timer is interrupt enabled, wherein the interrupt message comprises a target interrupt number of the virtual timer in the target processor core.

After receiving the interrupt message, the interrupt controller may obtain a target interrupt type corresponding to the target interrupt number based on the target interrupt number included in the interrupt message and a pre-stored correspondence between the interrupt number and the interrupt type, and generate a target interrupt request based on the target interrupt type. The target interrupt request is assumed to be FIQ in FIG. 5A. And then, the interrupt controller can call an FIQ processing function to process the FIQ, and can call a software-triggered interrupt function to generate a notification message corresponding to each processor core in the processing process, wherein the notification message is used for notifying each processor core to execute interrupt processing, and the notification message comprises the address of a callback function corresponding to the processor core. After receiving the notification message sent by the interrupt controller, each processor core can stop running, and records running exception information of the processor core according to the address of the callback function, namely records the context when the processor core runs abnormally.

As shown in fig. 5B, in connection with the example in fig. 5A, the target processor core is assumed to be a slave core. Then, the processing unit of the target processor core sends an interrupt message to the master core if the timeout information is received and the target virtual timer is enabled, the target virtual timer interrupt is enabled, and the processing unit determines that the target virtual timer is enabled.

And the main core sends an interrupt message to the interrupt controller, and the interrupt controller generates the FIQ after receiving the interrupt message sent by the main core. And then, the interrupt controller can call an FIQ processing function to process the FIQ, and can call a software-triggered interrupt function to generate a notification message corresponding to the target processor core in the processing process, wherein the notification message is used for notifying the target processor core to execute interrupt processing, and the notification message comprises the address of a callback function corresponding to the processor core. The target processor core can stop running after receiving the notification message sent by the interrupt controller, and records running abnormal information of the processor core according to the address of the callback function, namely records the context when the processor core runs abnormally.

The scheme provided by the embodiment of the application is mainly introduced from the perspective of a method. To implement the above functions, it includes hardware structures and/or software modules for performing the respective functions. Those of skill in the art would readily appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as hardware or combinations of hardware and computer software. Whether a function is performed as hardware or computer software drives hardware depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

Fig. 6 is a schematic structural diagram of an interrupt processing apparatus 60 according to an embodiment of the present disclosure, where the interrupt processing apparatus 60 is configured to execute the interrupt processing method shown in fig. 4 or fig. 5. The interrupt processing apparatus 60 may include a registration unit 61, a generation unit 62, and an acquisition unit 63.

And the registering unit 61 is configured to register a callback function corresponding to each processor core, where each callback function is used to obtain the running exception information of the corresponding processor core after being recalled.

A generating unit 62, configured to generate the target interrupt request if there is a timeout of the target virtual timer in the N virtual timers.

The obtaining unit 63 is configured to obtain the abnormal operation information of the M processor cores according to the interrupt processing function corresponding to the target interrupt request generated by the generating unit 62 and the callback functions corresponding to the M processor cores registered by the registering unit 61.

Optionally, as shown in fig. 7, the interrupt processing apparatus further includes: a configuration unit 64.

The configuration unit 64 is configured to perform interrupt configuration on each of the N virtual timers, where the configured virtual timer is used to monitor an operating state of the corresponding processor core.

Optionally, the configuration unit 64 is specifically configured to: enabling each virtual timer, enabling each virtual timer to interrupt, registering an interrupt number corresponding to each virtual timer, establishing a corresponding relation between the registered interrupt number and an interrupt type, and registering an abnormal information address corresponding to each processor core, wherein the abnormal information address is used for storing running abnormal information of the corresponding processor core. The generating unit 62 is specifically configured to: and generating a target interrupt request under the conditions that the target virtual timer is overtime, the target virtual timer is enabled and the target virtual timer is interrupt enabled.

Optionally, the registering unit 61 is specifically configured to: and calling a registration function, and registering the address of the callback function corresponding to each processor core.

Optionally, the generating unit 62 is specifically configured to: acquiring a target interrupt number corresponding to a target virtual timer; acquiring a target interrupt type corresponding to the target interrupt number according to a corresponding relation between the pre-stored interrupt number and the interrupt type; and generating a target interrupt request according to the target interrupt type.

Optionally, the obtaining unit 63 is specifically configured to: acquiring an interrupt processing function corresponding to the target interrupt request; based on the interrupt processing function, calling a trigger interrupt function; and acquiring the running exception information of each processor core based on the triggering interrupt function and the callback function corresponding to each processor core.

Optionally, the obtaining unit 63 is specifically configured to: and acquiring the abnormal operation information of each processor core according to the interrupt processing function and the callback function corresponding to each processor core in the M processor cores. Or acquiring the running exception information corresponding to each processor core in the processor cores corresponding to the target virtual timer according to the interrupt processing function and the callback function corresponding to each processor core in the processor cores corresponding to the target virtual timer.

Of course, the interrupt processing device 60 provided in the embodiment of the present application includes, but is not limited to, the above units.

Another embodiment of the present application further provides a computer-readable storage medium, where a computer instruction is stored in the computer-readable storage medium, and when the computer instruction runs on an interrupt processing apparatus, the interrupt processing apparatus is caused to perform each step performed by the interrupt processing apparatus in the method flow shown in the foregoing method embodiment.

Another embodiment of the present application further provides a chip system, and the chip system is applied to an interrupt processing apparatus. The chip system includes one or more interface circuits, and one or more processors. The interface circuit and the processor are interconnected by a line. The interface circuit is configured to receive signals from a memory of the interrupt processing device and to send signals to the processor, the signals including computer instructions stored in the memory. When the processor executes the computer instructions, the interrupt processing device executes the steps executed by the interrupt processing device in the method flow shown in the above-mentioned embodiment of the method.

In another embodiment of the present application, a computer program product is also provided, where the computer program product includes computer instructions, which, when executed on an interrupt handling apparatus, cause the interrupt handling apparatus to execute each step executed by the interrupt handling apparatus in the method flow shown in the foregoing method embodiment.

In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented using a software program, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. The processes or functions according to the embodiments of the present application are generated in whole or in part when the computer-executable instructions are loaded and executed on a computer. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored on a computer readable storage medium or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wire (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). Computer-readable storage media can be any available media that can be accessed by a computer or can comprise one or more data storage devices, such as servers, data centers, and the like, that can be integrated with the media. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., Solid State Disk (SSD)), among others.

The foregoing is only illustrative of the present application. Those skilled in the art can conceive of changes or substitutions based on the specific embodiments provided in the present application, and all such changes or substitutions are intended to be included within the scope of the present application.

Claims

1. An interrupt processing method applied to a host, wherein the host includes M processor cores and N virtual timers, the M processor cores correspond to the N virtual timers, M is a positive integer, N is an integer greater than or equal to 1 and less than or equal to M, and the method includes:

registering a callback function corresponding to each processor core, wherein each callback function is used for acquiring the abnormal operation information of the corresponding processor core after being called back;

generating a target interrupt request under the condition that a target virtual timer is overtime in the N virtual timers;

and acquiring the abnormal operation information of the M processor cores according to the interrupt processing function corresponding to the target interrupt request and the callback functions corresponding to the M processor cores.

2. The interrupt processing method of claim 1, further comprising:

and performing interrupt configuration on each virtual timer in the N virtual timers, wherein the configured virtual timer is used for monitoring the running state of the corresponding processor core.

3. The interrupt processing method according to claim 2,

the performing interrupt configuration on each virtual timer of the N virtual timers includes:

enabling each virtual timer, enabling each virtual timer to interrupt, registering an interrupt number corresponding to each virtual timer, establishing a corresponding relation between the registered interrupt number and an interrupt type, and registering an abnormal information address corresponding to each processor core, wherein the abnormal information address is used for storing running abnormal information of the corresponding processor core;

generating a target interrupt request when a target virtual timer in the N virtual timers is overtime, wherein the generating comprises:

and generating the target interrupt request under the conditions that the target virtual timer is overtime, the target virtual timer is enabled and the target virtual timer is interrupt enabled.

4. The interrupt processing method of any one of claims 1 to 3, wherein registering the callback function for each processor core comprises:

and calling a registration function, and registering the address of the callback function corresponding to each processor core.

5. The interrupt processing method of any of claims 1-3, wherein the generating a target interrupt request comprises:

acquiring a target interrupt number corresponding to the target virtual timer;

acquiring a target interrupt type corresponding to the target interrupt number according to a corresponding relation between a prestored interrupt number and an interrupt type;

and generating the target interrupt request according to the target interrupt type.

6. The interrupt processing method according to any one of claims 1 to 3, wherein the obtaining of the running exception information of the M processor cores according to the interrupt processing function corresponding to the target interrupt request and the callback functions corresponding to the M processor cores includes:

acquiring an interrupt processing function corresponding to the target interrupt request;

based on the interrupt processing function, calling a trigger interrupt function;

and acquiring the running exception information of the M processor cores based on the triggering interrupt function and the callback functions corresponding to the M processor cores.

7. The interrupt processing method according to any one of claims 1 to 3, wherein the obtaining of the running exception information of the M processor cores according to the interrupt processing function corresponding to the target interrupt request and the callback functions corresponding to the M processor cores includes:

acquiring running abnormal information of each processor core according to the interrupt processing function and the callback function corresponding to each processor core in the M processor cores;

alternatively, the first and second electrodes may be,

and acquiring the abnormal operation information corresponding to each processor core in the processor cores corresponding to the target virtual timer according to the interrupt processing function and the callback function corresponding to each processor core in the processor cores corresponding to the target virtual timer.

8. The interrupt processing method according to any one of claims 1 to 3, wherein the host further comprises an interrupt controller, and the generating a target interrupt request in the presence of a target virtual timer timeout in the N virtual timers comprises:

under the condition that the target virtual timer is overtime, a target processor core corresponding to the target virtual timer generates an interrupt message and sends the interrupt message to an interrupt controller, the interrupt controller generates the target interrupt request according to the interrupt message, and the interrupt message comprises a target interrupt number corresponding to the target virtual timer;

alternatively, the first and second electrodes may be,

when M is larger than 1 and the M processor cores comprise a main core and at least one slave core, under the condition that the target virtual timer is overtime, the target processor core corresponding to the target virtual timer generates interrupt messages and sends the interrupt messages to the main core, the main core sends all the interrupt messages to the interrupt controller after receiving all the interrupt messages, and the interrupt controller generates the target interrupt request according to all the interrupt messages.

9. An interrupt processing apparatus at a host, the host including M processor cores and N virtual timers, the M processor cores corresponding to the N virtual timers, M being a positive integer, N being an integer greater than or equal to 1 and less than or equal to M, the interrupt processing apparatus comprising:

the register unit is used for registering the callback function corresponding to each processor core, and each callback function is used for acquiring the abnormal operation information of the corresponding processor core after being recalled;

a generating unit, configured to generate a target interrupt request when a target virtual timer is overtime in the N virtual timers;

and the acquisition unit is used for acquiring the abnormal operation information of the M processor cores according to the interrupt processing function corresponding to the target interrupt request generated by the generation unit and the callback functions corresponding to the M processor cores registered by the registration unit.

10. The interrupt handling apparatus of claim 7, wherein the interrupt handling apparatus further comprises: a configuration unit;

the configuration unit is configured to perform interrupt configuration on each of the N virtual timers, and the configured virtual timer is used to monitor an operating state of the corresponding processor core.

11. The interrupt processing apparatus of claim 10,

the configuration unit is specifically configured to: enabling each virtual timer, enabling each virtual timer to interrupt, registering an interrupt number corresponding to each virtual timer, establishing a corresponding relation between the registered interrupt number and an interrupt type, and registering an abnormal information address corresponding to each processor core, wherein the abnormal information address is used for storing running abnormal information of the corresponding processor core;

the generating unit is specifically configured to: and generating the target interrupt request under the conditions that the target virtual timer is overtime, the target virtual timer is enabled and the target virtual timer is interrupt enabled.

12. The interrupt processing apparatus according to any one of claims 9 to 11, wherein the registration unit is specifically configured to:

13. The interrupt processing apparatus according to any one of claims 9 to 11, wherein the generation unit is specifically configured to:

acquiring a target interrupt number corresponding to the target virtual timer;

14. The interrupt processing apparatus according to any one of claims 9 to 11, wherein the obtaining unit is specifically configured to:

15. The interrupt processing apparatus according to any one of claims 9 to 11, wherein the obtaining unit is specifically configured to:

alternatively, the first and second electrodes may be,

16. An interrupt handling apparatus at a host, the interrupt handling apparatus comprising a memory and a processor; the memory and the processor are coupled; the memory for storing computer program code, the computer program code comprising computer instructions; when the processor executes the computer instructions, the interrupt handling apparatus performs the interrupt handling method of any of claims 1-8.

17. A computer-readable storage medium comprising computer instructions that, when executed on an interrupt handling apparatus, cause the interrupt handling apparatus to perform an interrupt handling method according to any one of claims 1 to 8.