CN114397555A

CN114397555A - Fault detection method and device of PFC circuit, terminal and storage medium

Info

Publication number: CN114397555A
Application number: CN202111591734.8A
Authority: CN
Inventors: 王志东; 崔玉洁; 黄劲松; 张晓明; 王子硕
Original assignee: Zhangzhou Kehua Technology Co Ltd; Kehua Data Co Ltd
Current assignee: Zhangzhou Kehua Technology Co Ltd; Kehua Data Co Ltd
Priority date: 2021-12-23
Filing date: 2021-12-23
Publication date: 2022-04-26

Abstract

The invention provides a fault detection method, a fault detection device, a terminal and a storage medium of a PFC circuit, wherein the method comprises the following steps: applying an alternating current signal to the PFC circuit; independently applying a switching signal to a target switching module, and monitoring a direct-current side electric signal of the PFC circuit at the moment; and if the direct-current side electric signal of the PFC circuit changes in the switching period of the target switch module, judging that the target switch module is normal, otherwise, judging that the target switch module has a fault. Through the scheme, the fault detection of the switch module in the PFC circuit can be realized, the problem that the fault components in the PFC circuit cannot be positioned in the prior art is solved, and the accuracy of fault positioning is improved.

Description

Fault detection method and device of PFC circuit, terminal and storage medium

Technical Field

The present invention relates to the field of PFC circuits, and in particular, to a method and an apparatus for detecting a fault in a PFC circuit, a terminal, and a storage medium.

Background

At present, a PFC (Power Factor Correction) circuit is widely used, and whether the PFC circuit can normally operate or not directly affects the reliable operation of a related device. Therefore, it is necessary to periodically perform maintenance on the devices inside the PFC circuit.

At present, when a PFC circuit is subjected to fault detection, whether the PFC circuit is in fault or not can be detected generally, and components with faults cannot be specifically positioned.

Disclosure of Invention

In view of this, the invention provides a method, an apparatus, a terminal and a storage medium for detecting a fault of a PFC circuit, which can solve the problem in the prior art that a faulty component of the PFC circuit cannot be accurately located.

In a first aspect, an embodiment of the present invention provides a method for detecting a fault of a PFC circuit, where the method includes:

applying an alternating current signal to the PFC circuit;

independently applying a switching signal to a target switching module, and monitoring a direct-current side electric signal of the PFC circuit; the target switch module is any one switch module in the PFC circuit;

and if the direct-current side electric signal of the PFC circuit changes in the switching period of the target switch module, judging that the target switch module is normal, otherwise, judging that the target switch module has a fault.

In a second aspect, an embodiment of the present invention provides a fault detection apparatus for a PFC circuit, including:

the alternating current signal applying module is used for applying an alternating current signal to the PFC circuit;

the direct-current side signal monitoring module is used for independently applying a switching signal to a target switching module and monitoring a direct-current side electric signal of the PFC circuit; the target switch module is any one switch module in the PFC circuit;

and the fault judgment module is used for judging that the target switch module is normal if the direct-current side electric signal of the PFC circuit changes in the switching period of the target switch module, and otherwise, judging that the target switch module has a fault.

In a third aspect, an embodiment of the present invention provides a terminal, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, where the processor, when executing the computer program, implements the steps of the method according to any one of the possible implementation manners of the first aspect.

In a fourth aspect, the present invention provides a computer-readable storage medium, where a computer program is stored, and when the computer program is executed by a processor, the computer program implements the steps of the method according to any one of the possible implementation manners of the first aspect.

Compared with the prior art, the embodiment of the invention has the following beneficial effects:

the embodiment of the invention firstly applies an alternating current signal to a PFC circuit; then, independently applying a switching signal to a target switching module, and monitoring a direct-current side electric signal of the PFC circuit at the moment; and if the direct-current side electric signal of the PFC circuit changes in the switching period of the target switch module, judging that the target switch module is normal, otherwise, judging that the target switch module has a fault. Through the scheme, the automatic fault detection of the switch module in the PFC circuit can be realized, the problem that the fault components in the PFC circuit cannot be positioned in the prior art is solved, and the accuracy of fault positioning is improved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.

Fig. 1 is a flowchart illustrating an implementation of a fault detection method for a PFC circuit according to an embodiment of the present invention;

fig. 2 is a schematic circuit diagram of a PFC circuit according to an embodiment of the present invention;

FIG. 3 is a schematic waveform diagram of a set of fault detection signals provided by an embodiment of the present invention;

FIG. 4 is a schematic circuit diagram of a three-phase zero-line two-level AC/DC circuit provided by an embodiment of the present invention; fig. 4a is a signal flow diagram when only the switch module S2 is in the on state in the region 1, the region 3, the region 4, and the region 6 according to the embodiment of the present invention; fig. 4b is a signal flow diagram of the switch module S2 in the off state when zone 1, zone 3, zone 4 and zone 6 are provided by the embodiment of the present invention;

FIG. 5 is a three-phase zero-free topological partition diagram provided by an embodiment of the present invention;

fig. 6 is a circuit schematic diagram of a three-phase four-wire two-level AC/DC circuit provided by the embodiment of the present invention, wherein fig. 6a is a signal flow diagram when only the switch module S2 provided by the embodiment of the present invention is in a conducting state; fig. 6b is a signal flow diagram of the switching module S2 in the off state according to the embodiment of the present invention;

fig. 7 is a schematic circuit diagram of a three-phase four-wire T-type three-level AC/DC circuit according to an embodiment of the present invention, where fig. 7a is a signal flow diagram when U is a positive half-wave and the forward switch tube S7 is turned on; fig. 7b is a signal flow diagram when U is a negative half-wave and the positive switch tube S7 is turned off according to the embodiment of the present invention; fig. 7c is a signal flow diagram when U is a positive half-wave and the reverse switching tube S8 is turned on according to the embodiment of the present invention; fig. 7d is a signal flow diagram when the negative half-wave reverse switch tube S8 is turned off according to the embodiment of the present invention;

fig. 8 is a schematic structural diagram of a fault detection apparatus of a PFC circuit according to an embodiment of the present invention;

fig. 9 is a schematic diagram of a terminal according to an embodiment of the present invention.

Detailed Description

In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.

In order to make the objects, technical solutions and advantages of the present invention more apparent, the following description is made by way of specific embodiments with reference to the accompanying drawings.

Fig. 1 is a flowchart illustrating an implementation of a fault detection method for a PFC circuit according to an embodiment of the present invention. As shown in fig. 1, the detailed implementation flow of the fault detection method of the PFC circuit is as follows:

s101: an alternating current signal is applied to the PFC circuit.

Specifically, the execution main body (terminal) of the present embodiment may be a controller of the PFC circuit, and the present embodiment first applies an ac electrical signal to the ac side of the PFC circuit at the time of fault detection of the PFC circuit, for observing a change in the dc electrical signal based on the switching state of the switching module in the PFC circuit.

S102: independently applying a switching signal to a target switching module, and monitoring a direct-current side electric signal of the PFC circuit; the target switch module is any one switch module in the PFC circuit.

In this embodiment, fig. 2 shows a schematic diagram of a PFC circuit, as shown in fig. 2, the PFC circuit includes a plurality of switch modules (S1 to S6), and in order to avoid interference of the plurality of switch modules with a dc-side electrical signal, in this embodiment, a switch signal is separately applied to each switch module during fault detection, and when a switch signal is applied to a certain switch module, other switch modules are all in an off state, that is, a low-level signal is applied to other switch modules.

Specifically, a fault detection signal group is pre-stored in the terminal, the fault detection signal group is a group of switch signals, as shown in fig. 3, each switch signal corresponds to one switch module, and each switch signal (T) is_n,n∈[1,6]) Are arranged staggered in time. When the target switch module is detected, the applied switch signal can be a switch signal with one switching period, so as to improve the detectionThe switching signal can also set a plurality of switching cycles to measure the accuracy.

S103: and if the direct-current side electric signal of the PFC circuit changes in the switching period of the target switch module, judging that the target switch module is normal, otherwise, judging that the target switch module has a fault.

In this embodiment, when the fault detection signal group is used to sequentially perform fault detection on each switch module of the PFC circuit, in order to ensure that the terminal can distinguish which switch module corresponds to which switch signal application time period the detected dc-side electrical signal is, in this embodiment, when the fault detection signal group is set, the first rising edge time of the switch signal of the switch module S1 (i.e., the starting time of one switching cycle of the switch signal) may be used as a zero point, and then the time of the application time period of the switch signal corresponding to each switch module relative to the starting time may be sequentially determined. When the switching signal is applied, when the first rising edge of the switching signal of the switching module S1 is monitored, timing is started, and the dc-side electrical signal in the switching signal application time period of each switching module is monitored at the same time, and the fault of the corresponding switching module is determined according to the change of the dc-side electrical signal in the corresponding time period.

As can be seen from the above embodiments, in the embodiments of the present invention, an ac signal is applied to the PFC circuit; then, independently applying a switching signal to a target switching module, and monitoring a direct-current side electric signal of the PFC circuit at the moment; and if the direct-current side electric signal of the PFC circuit changes in the switching period of the target switch module, judging that the target switch module is normal, otherwise, judging that the target switch module has a fault. Through the scheme, the fault detection of the switch module in the PFC circuit can be realized, the problem that the fault component in the PFC circuit cannot be positioned in the prior art is solved, and the accuracy of fault positioning is improved.

In one embodiment, the specific implementation flow of S103 includes:

s201: and if the absolute value of the direct-current side electric signal of the PFC circuit rises in the switching period of the target switch module, judging that the target switch module is normal, otherwise, judging that the target switch module has a fault.

In one embodiment, as shown in fig. 4, the PFC circuit comprises a three-phase zero-line two-level AC/DC circuit; the specific implementation process of S201 includes:

and if the absolute value of the direct-current side electric signal in the off period of the target switch module is higher than the absolute value of the direct-current side electric signal in the on period of the target switch module, judging that the target switch module is normal, otherwise, judging that the target switch module is in fault.

In this embodiment, taking the switch module S2 in fig. 4 as an example, the dc-side electrical signal variation rule of S2 in a switching cycle is analyzed as follows:

in the switching cycle of S2, the three-phase zero-free topology partition diagram is shown in fig. 5, and it can be seen from fig. 4 and 5 that when the

regions

1, 3, 4 and 6 of the switch module S2 are in the conducting state, the signal flow diagram is shown in fig. 4a, and as can be seen from fig. 4a, the switch module S2 does not flow through the C4 when the

regions

1, 3, 4 and 6 are in the conducting state, and therefore, the dc side electrical signal is not changed. When the switch module S2 is in the off state in the

areas

1, 3, 4 and 6, the signal flow is as shown in fig. 4b, and as can be seen from fig. 4b, the switch module S2 charges the C4 when the

areas

1, 3, 4 and 6 are in the off state, so the dc side signal rises; the turn-on and turn-off of S2 at

zones

2 and 5 does not affect the control result.

From the above analysis, it can be seen that, in the switching cycle alone of S2, it is possible to determine whether or not S2 has failed by detecting whether or not the dc-side electric signal rises. Although the signal flow path of the other switch modules is slightly different from that of S2, the change rule of the dc-side electrical signal is the same, and is not described herein again. Therefore, when the PFC circuit is a three-phase zero-line-free two-level AC/DC circuit, whether the target switch module has a fault can be determined by observing whether the direct-current signal rises in the switching period of the target switch module, and the implementation method is simple and easy to implement.

In one embodiment, referring to fig. 6, the PFC circuit comprises a three-phase four-wire two-level AC/DC circuit; the direct current side electric signal comprises a positive bus voltage between a positive direct current bus and a zero line;

the specific implementation process of S201 includes:

and if the absolute value of the positive bus voltage of the three-phase four-wire two-level AC/DC circuit is increased in the switching period of the target switch module, judging that the target switch module is normal, otherwise, judging that the target switch module is in fault.

In this embodiment, also taking S2 as an example, the DC-side electrical signal variation law of the three-phase four-wire two-level AC/DC circuit in the single switching period of S2 is analyzed as follows:

as shown in fig. 6a, when switch module S2 is turned on, current flows through the U phase to negative dc Bus-corresponding capacitor C5 and then back to the N line, which discharges C5. However, due to the support of the diodes in the S2, S4, S6 bodies, the negative DC Bus voltage does not drop below the U, V, W rectified voltage. Meanwhile, the negative direct current Bus-voltage is the lowest voltage in the whole topology, so that the inductance is charged no matter the U-phase voltage is positive or negative, and the direct current side electric signal is not obviously changed when the switch module S2 is switched on. As shown in fig. 6b, when switching module S2 is off, current flows through the U phase to positive dc Bus + capacitor C4 and back to the NBUS line, which charges C4 causing the Bus + voltage to rise.

From the above analysis, it can be seen that, in the switching cycle alone of S2, it is possible to determine whether or not S2 is faulty by detecting whether or not the positive bus voltage is raised. Although the signal flow path of the other switch modules of the three-phase four-wire two-level AC/DC circuit is slightly different from that of the S2, the change rule of the positive bus voltage is the same, and the description is omitted. Therefore, when the PFC circuit is a three-phase four-wire two-level AC/DC circuit, whether the target switch module has a fault can be determined by observing whether the voltage of the positive bus in the switching period of the target switch module rises, and the implementation method is simple and easy to implement.

In one embodiment, referring to fig. 7, the PFC circuit includes a three-phase four-wire T-type three-level AC/DC circuit; the direct-current side electric signal comprises a positive bus voltage between the positive direct-current bus and the zero line and a negative bus voltage between the negative direct-current bus and the zero line;

the three-phase four-wire T-shaped three-level AC/DC circuit comprises a three-phase longitudinal bridge arm, a three-phase transverse switch module, a first capacitor and a second capacitor; each phase of transverse switch module comprises a forward switch tube and a reverse switch tube;

the first end of the three-phase longitudinal bridge arm and the first end of the first capacitor are respectively connected with a positive direct-current bus of the three-phase four-wire T-type three-level AC/DC circuit, and the second end of the three-phase longitudinal bridge arm and the second end of the second capacitor are respectively connected with a negative direct-current bus of the three-phase four-wire T-type three-level AC/DC circuit; the positive electrode of each phase of forward switch tube is respectively connected with the midpoint of the corresponding phase of longitudinal bridge arm, the negative electrode of each phase of forward switch tube is respectively connected with the negative electrode of the corresponding reverse switch tube, and the positive electrode of each reverse switch tube, the second end of the first capacitor and the first end of the second capacitor are respectively connected with a zero line;

the specific implementation process of S201 includes:

if the absolute value of the positive bus voltage of the three-phase four-wire T-type three-level AC/DC circuit is increased in the switching period of a first target switch module, judging that a forward switch tube in the first target switch module is normal, otherwise, judging that the forward switch tube in the first target switch module has a fault; the first target switch module is any one of three-phase transverse switch modules;

if the absolute value of the negative bus voltage of the three-phase four-wire T-shaped three-level AC/DC circuit is increased in the switching period of the first target switch module, determining that a negative switch tube in the first target switch module is normal, otherwise, determining that the negative switch tube in the first target switch module has a fault.

In this embodiment, for a three-phase four-wire two-level ACDC circuit, the fault detection methods of the vertical switch module and the horizontal switch module are different.

Regarding the positive switch tube in the transverse switch module of the three-phase four-wire two-level ACDC circuit, taking S7 as an example, when U is a positive half wave and S7 is turned on, the signal flow is as shown in fig. 7a, and when U is a negative half wave and S7 is turned off, the signal flow is as shown in fig. 7b, and it can be seen that the positive dc bus voltage has a phenomenon of rising during the switching period of the positive switch tube S7.

For the negative switch tube in the transverse switch module of the three-phase four-wire two-level ACDC circuit, taking S8 as an example, when U is a positive half-wave and S8 is turned on, the signal flow is as shown in fig. 7c, and when U is a negative half-wave and S8 is turned off, the signal flow is as shown in fig. 7d, which shows that the negative dc bus voltage has a rising phenomenon in the switching period of S8.

In one embodiment, each phase of longitudinal legs comprises two switch modules; the specific implementation process of S201 further includes:

and if the absolute value of the positive bus voltage of the three-phase four-wire T-shaped three-level AC/DC circuit is increased in the switching period of a second target switch module, judging that the second target switch module is normal, otherwise, judging that the second target switch module has a fault, wherein the second target switch module is any one switch module in a three-phase longitudinal bridge arm.

In the present embodiment, the fault detection method is the same as that of the three-phase four-wire two-level AC/DC circuit for the switching modules (S1 to S6) of the vertical arms in the three-phase four-wire two-level ACDC circuit.

In one embodiment, the specific implementation flow of S102 includes:

simultaneously applying switching signals to a positive switching tube and a negative switching tube in the first target switching module;

or, a switching signal is applied to a target switching tube separately, and the target switching tube is any one of a forward switching tube and a reverse switching tube in the first target switching module.

In this embodiment, since the monitoring points corresponding to the forward switching tube and the reverse switching tube of the transverse switching module in the three-phase four-wire two-level ACDC circuit are different, the same switching signal can be simultaneously applied to the forward switching tube and the reverse switching tube of one transverse switching module, when the voltage of the positive bus is detected to be increased, the forward switching tube is determined to be normal, and when the voltage of the negative bus is detected to be increased, the negative switching tube is determined to be normal.

It can be known from the foregoing embodiment that, in this embodiment, the method can simply and quickly perform fault detection on each switch module of the PFC circuit, and the method provided in this embodiment only needs to compare the magnitude change of the direct-current side electrical signal in the switching period of the switch module to be detected, and is simple in calculation and easy to implement.

It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present invention.

The following are embodiments of the apparatus of the invention, reference being made to the corresponding method embodiments described above for details which are not described in detail therein.

Fig. 8 is a schematic structural diagram of a fault detection apparatus of a PFC circuit according to an embodiment of the present invention, and for convenience of description, only the parts related to the embodiment of the present invention are shown, and detailed descriptions are as follows:

as shown in fig. 8, the fault detection apparatus 100 of the PFC circuit includes: .

An ac signal application module 110, configured to apply an ac signal to the PFC circuit;

a dc side signal monitoring module 120, configured to apply a switching signal to a target switching module separately, and monitor a dc side electrical signal of the PFC circuit; the target switch module is any one switch module in the PFC circuit;

a fault determining module 130, configured to determine that the target switch module is normal if an electrical signal at a direct current side of the PFC circuit changes within a switching period of the target switch module, and otherwise determine that the target switch module is faulty.

In one embodiment, the failure determination module 130 includes:

and the fault judging unit is used for judging that the target switch module is normal if the absolute value of the direct-current side electric signal of the PFC circuit is increased in the switching period of the target switch module, and otherwise, judging that the target switch module is in fault.

In one embodiment, the PFC circuit comprises a three-phase zero-line two-level AC/DC circuit; the failure determination unit includes:

In one embodiment, the PFC circuit comprises a three-phase four-wire two-level AC/DC circuit; the direct current side electric signal comprises a positive bus voltage between a positive direct current bus and a zero line; the failure determination unit includes:

In one embodiment, the PFC circuit comprises a three-phase four-wire T-type three-level AC/DC circuit; the direct-current side electric signal comprises a positive bus voltage between the positive direct-current bus and the zero line and a negative bus voltage between the negative direct-current bus and the zero line;

the failure determination unit includes:

In one embodiment, each phase of longitudinal legs comprises two switch modules; the failure determination unit includes:

In one embodiment, the dc-side signal monitoring module comprises a switching signal applying unit for:

The embodiment of the invention firstly applies an alternating current signal to a PFC circuit; then, independently applying a switching signal to a target switching module, and monitoring a direct-current side electric signal of the PFC circuit at the moment; and if the direct-current side electric signal of the PFC circuit changes in the switching period of the target switch module, judging that the target switch module is normal, otherwise, judging that the target switch module has a fault. Through the scheme, the fault detection of the switch module in the PFC circuit can be realized, the problem that the fault component in the PFC circuit cannot be positioned in the prior art is solved, and the accuracy of fault positioning is improved.

The fault detection apparatus of the PFC circuit provided in this embodiment may be configured to implement the above-mentioned fault detection method of the PFC circuit, and the implementation principle and the technical effect are similar, which are not described herein again.

Fig. 9 is a schematic diagram of a terminal according to an embodiment of the present invention. As shown in fig. 9, the terminal 9 of this embodiment includes: a processor 90, a memory 91 and a computer program 92 stored in said memory 91 and executable on said processor 90. The processor 90, when executing the computer program 92, implements the steps in the above-described method embodiments of fault detection for each PFC circuit, such as the steps 101 to 103 shown in fig. 1. Alternatively, the processor 90, when executing the computer program 92, implements the functions of the modules/units in the above-mentioned device embodiments, such as the functions of the units 110 to 130 shown in fig. 8.

Illustratively, the computer program 92 may be partitioned into one or more modules/units that are stored in the memory 91 and executed by the processor 90 to implement the present invention. The one or more modules/units may be a series of computer program instruction segments capable of performing specific functions, which are used to describe the execution of the computer program 92 in the terminal 9.

The terminal 9 may include, but is not limited to, a processor 90, a memory 91. It will be appreciated by those skilled in the art that fig. 9 is only an example of a terminal 9 and does not constitute a limitation of the terminal 9 and may comprise more or less components than those shown, or some components may be combined, or different components, for example the terminal may further comprise input output devices, network access devices, buses, etc.

The Processor 90 may be a Central Processing Unit (CPU), other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic, discrete hardware components, etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

The memory 91 may be an internal storage unit of the terminal 9, such as a hard disk or a memory of the terminal 9. The memory 91 may also be an external storage device of the terminal 9, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card) and the like provided on the terminal 9. Further, the memory 91 may also include both an internal storage unit and an external storage device of the terminal 9. The memory 91 is used for storing the computer program and other programs and data required by the terminal. The memory 91 may also be used to temporarily store data that has been output or is to be output.

It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-mentioned division of the functional units and modules is illustrated, and in practical applications, the above-mentioned function distribution may be performed by different functional units and modules according to needs, that is, the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-mentioned functions. Each functional unit and module in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units are integrated in one unit, and the integrated unit may be implemented in a form of hardware, or in a form of software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working processes of the units and modules in the system may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

In the embodiments provided in the present invention, it should be understood that the disclosed apparatus/terminal and method may be implemented in other ways. For example, the above-described apparatus/terminal embodiments are merely illustrative, and for example, the division of the modules or units is only one logical division, and there may be other divisions when actually implemented, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The integrated modules/units, if implemented in the form of software functional units and sold or used as separate products, may be stored in a computer readable storage medium. Based on such understanding, all or part of the flow of the method according to the above embodiments may be implemented by a computer program, which may be stored in a computer readable storage medium, and when the computer program is executed by a processor, the steps of the embodiments of the fault detection method for each PFC circuit may be implemented. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, usb disk, removable hard disk, magnetic disk, optical disk, computer Memory, Read-Only Memory (ROM), Random Access Memory (RAM), electrical carrier wave signals, telecommunications signals, software distribution medium, and the like. It should be noted that the computer readable medium may contain other components which may be suitably increased or decreased as required by legislation and patent practice in jurisdictions, for example, in some jurisdictions, computer readable media which may not include electrical carrier signals and telecommunications signals in accordance with legislation and patent practice.

The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present invention, and are intended to be included within the scope of the present invention.

Claims

1. A fault detection method of a PFC circuit is characterized by comprising the following steps:

applying an alternating current signal to the PFC circuit;

2. The method according to claim 1, wherein the determining that the target switch module is normal if an electrical signal on a dc side of the PFC circuit changes within a switching period of the target switch module, and otherwise determining that the target switch module is faulty comprises:

and if the absolute value of the direct-current side electric signal of the PFC circuit rises in the switching period of the target switch module, judging that the target switch module is normal, otherwise, judging that the target switch module has a fault.

3. The method of claim 2, wherein the PFC circuit comprises a three-phase zero-line two-level AC/DC circuit; if the absolute value of the direct-current side electric signal of the PFC circuit increases in the switching period of the target switch module, determining that the target switch module is normal, otherwise determining that the target switch module has a fault, including:

4. The method of fault detection for a PFC circuit of claim 2, wherein the PFC circuit comprises a three-phase four-wire two-level AC/DC circuit; the direct current side electric signal comprises a positive bus voltage between a positive direct current bus and a zero line;

if the absolute value of the direct-current side electric signal of the PFC circuit increases in the switching period of the target switch module, determining that the target switch module is normal, otherwise determining that the target switch module has a fault, including:

5. The method of fault detection for a PFC circuit of claim 2, wherein the PFC circuit comprises a three-phase four-wire T-type three-level AC/DC circuit; the direct-current side electric signal comprises a positive bus voltage between the positive direct-current bus and the zero line and a negative bus voltage between the negative direct-current bus and the zero line;

6. The method according to claim 5, wherein each phase of the longitudinal bridge arm comprises two switching modules;

7. The method of claim 5, wherein the applying the switching signal to the target switching module individually comprises:

8. A fault detection device for a PFC circuit, comprising:

9. A terminal comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that the processor implements the steps of the method according to any of the preceding claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 7.