CN114388450B - Integrated circuit device structure and integrated chip - Google Patents

Abstract

The embodiment of the invention discloses an integrated circuit device structure and an integrated chip. The integrated circuit device structure includes: the device comprises a first component, an isolation unit and a first power supply network; the isolation unit surrounds the first component and is arranged at the same layer with the first component; the first power supply network is positioned on one side of the first component and is electrically connected with the first component; the first power supply network comprises a plurality of first metal layers which are arranged in a stacked mode; the first metal layer of the same layer comprises a plurality of first power lines which are parallel to each other, and any two first power lines are insulated from each other; in the same direction, the vertical projection of the first power supply network is positioned in the vertical projection of the isolation unit; the line width index of at least one first metal layer in the first power supply network is larger than 1. According to the technical scheme of the embodiment of the invention, the voltage drop in the first power supply network for supplying power to the first component is smaller, and the electromigration phenomenon in the first power supply network for supplying power to the first component is less obvious.

Description

Integrated circuit device structure and integrated chip

Technical Field

The embodiment of the invention relates to the technical field of semiconductors, in particular to an integrated circuit device structure and an integrated chip.

Background

As semiconductor process processes are approaching physical limits, the requirements of the corresponding chips on the power supply network are also increasing. Smaller processes allow line widths to reach smaller levels to achieve smaller components, but a reduction in line width increases the equivalent resistance of the power supply network, resulting in an increase in voltage drop (IR-drop). Furthermore, the chip with high integration and the high frequency clock design bring higher power consumption density and current density, and the power line with high current density and high frequency variation is easy to generate Electromigration (EM) phenomenon.

On the basis, in the design of the chip, for a clock tree or a special high-frequency signal, a component capable of driving a large load (which may be called a large driving component for short) is required to be driven; for example, large drive components are employed to drive 16, 32 or even more of the next stage logic. When the frequency is increased, compared with a common component (i.e. a component for driving a small load), the large-driving component is overturned for more times in unit time to generate larger current; therefore, the power supply lines near the large drive components need to carry a larger current, resulting in a larger voltage drop. In addition, the electromigration phenomenon is aggravated because the line length of the low-level power line where the large driving component is located is generally long.

Disclosure of Invention

Embodiments of the present invention provide an integrated circuit device structure and an integrated chip to reduce voltage drop in a power supply network and improve electromigration in the power supply network.

In a first aspect, an embodiment of the present invention provides an integrated circuit device structure, including: a first component; an isolation unit surrounding the first component and disposed in the same layer as the first component; a first power supply network including a plurality of first metal layers arranged in a stack; the first power grid is positioned on one side of the first component and is electrically connected with the first component; the first metal layer on the same layer comprises a plurality of first power lines which are parallel to each other, and any two first power lines are insulated from each other; two adjacent first metal layers, wherein the extending direction of the first power line of one first metal layer is staggered with the extending direction of the first power line of the other first metal layer, and two first power sources with staggered extending directions are electrically connected at staggered sections; wherein, in the same direction, the vertical projection of the first power grid is located within the vertical projection of the isolation unit; in the first power supply network, the line width index of at least one first metal layer is greater than 1; the line width index of the first metal layer is the ratio of the line width of the first power line of the first metal layer to the preset basic line width of the layer.

Optionally, in the first power grid, a line width indicator of the first metal layer is in a decreasing trend in a direction in which the first component points to the first power grid; the minimum value of the line width index of each first metal layer is 1.

Optionally, the first metal layer with a line width index greater than 1 has a line width index in a range from 1.5 to 2.

Optionally, in the first power supply network, a line number index of at least one first metal layer is greater than 1; the line number index of the first metal layer is a ratio of the number of the first power lines of the first metal layer to the number of preset basic lines of the layer.

Optionally, in the first power grid, a line number index of the first metal layer is in a decreasing trend in a direction in which the first component points to the first power grid; the minimum value of the line number index of each first metal layer is 1.

Optionally, the isolation unit comprises: a coupling capacitor subunit, disposed around and in contact with the first component, and configured to reduce noise of the first component; a first boundary subunit disposed around the coupling capacitor subunit and contacting the coupling capacitor subunit; a second border cell disposed around the first border sub-cell; an isolation strip is arranged between the second boundary subunit and the first boundary subunit; and in the same direction, the vertical projection of the first power supply network is positioned in the vertical projection of the isolation strip.

In a second aspect, an embodiment of the present invention further provides an integrated chip, including at least one integrated circuit device structure as described in the first aspect; and the integrated circuit device structures are arranged on the same layer.

Optionally, the method further comprises: a plurality of second components; the second component and the first component are arranged on the same layer and are positioned on the periphery of the isolation unit; a second power supply network including a plurality of second metal layers stacked; the second power supply network and the first power supply network are arranged on the same layer and are electrically connected with the second component; the second metal layers correspond to the first metal layers one by one, and the second metal layers and the corresponding first metal layers are arranged on the same layer; the second metal layer on the same layer comprises a plurality of second power lines which are parallel to each other, and any two second power lines are insulated from each other; two adjacent second metal layers, wherein the extending direction of the second power line of one second metal layer is staggered with the extending direction of the second power line of the other second metal layer, and two second power sources with staggered extending directions are electrically connected at staggered sections; the line width index and the line number index of the second metal layer are both 1, the line width index of the second metal layer is the ratio of the line width of the second power line of the second metal layer to the preset basic line width of the layer, and the line number index of the second metal layer is the ratio of the number of the second power lines of the second metal layer to the preset basic line number of the layer; the preset basic line width of the second metal layer is equal to the corresponding preset basic line width of the first metal layer; the first metal layer and the second metal layer are arranged on the same layer, and the extending directions of the first power line and the second power line are collinear or parallel.

Optionally, the method further comprises: the third power supply network is positioned on one side of the first power supply network far away from the first component; in the same direction, the vertical projections of the first power supply network and the second power supply network are both positioned in the vertical projection of the third power supply network, and the third power supply network is electrically connected with the first power supply network and the second power supply network; the third power supply network comprises a plurality of third metal layers which are arranged in a stacked mode; the third metal layer on the same layer comprises a plurality of third power lines which are parallel to each other, and any two third power lines are insulated from each other; two adjacent layers of the third metal layers, wherein the extending direction of the third power line of one layer of the third metal layer is staggered with the extending direction of the second power line of the other layer of the third metal layer, and two third power sources with staggered extending directions are electrically connected at staggered sections; the line width index and the line number index of the third metal layer are both 1, the line width index of the third metal layer is the ratio of the line width of the third power line of the third metal layer to the preset basic line width of the layer, and the line number index of the third metal layer is the ratio of the number of the third power lines of the third metal layer to the preset basic line number of the layer; the extension directions of the third power line and the second power line are collinear.

Optionally, the three power grids, the second power grid and the first power grid are integrally arranged.

The integrated circuit device structure and the integrated chip provided by the embodiment of the invention are provided with an isolation unit and a first power supply network aiming at a first component, such as a large driving component. The isolation unit is arranged around the first component and is arranged on the same layer as the first component, the vertical projection of the first power grid in the same direction is located in the vertical projection of the isolation unit, the line width index of at least one first metal layer in the first power grid is larger than 1, the first power grid for supplying power to the first component is enabled to be short, the line length of the first power line is short, and the line width of the first power line is wide, so that the voltage drop in the first power grid is reduced, the electromigration phenomenon in the first power grid is improved, and a good power supply basis is provided for the first component.

Drawings

FIG. 1 is a schematic diagram of a top view of an integrated circuit device structure according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a top view of another integrated circuit device structure provided by an embodiment of the present invention;

FIG. 3 is a schematic diagram of a top view of another integrated circuit device structure provided by an embodiment of the present invention;

fig. 4 is a schematic top view of an isolation unit according to an embodiment of the present invention;

fig. 5 is a schematic diagram of a top view structure of an integrated chip according to an embodiment of the present invention;

fig. 6 is a schematic cross-sectional view of another integrated chip according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

Fig. 1 is a schematic top view of an integrated circuit device structure according to an embodiment of the present invention. Referring to fig. 1, an integrated circuit device structure includes a first component 110, an isolation unit 120, and a first power supply network; the isolation unit 120 surrounds the first component 110 and is disposed at the same layer as the first component 110; the first power grid is located on one side of the first component 110 and is electrically connected to the first component 110; the first power supply network comprises a plurality of first metal layers which are arranged in a stacked mode; the first metal layer of the same layer comprises a plurality of first power lines which are parallel to each other, and any two first power lines are insulated from each other; the extending direction of the first power line of one first metal layer is staggered with the extending direction of the first power line of the other first metal layer, and two first power sources with staggered extending directions are electrically connected at the staggered section; in the same direction, the vertical projection of the first power grid is located within the vertical projection of the isolation unit 120; in the first power supply network, the line width index of at least one first metal layer is greater than 1; the line width index of the first metal layer is the ratio of the line width of the first power line of the first metal layer to the preset basic line width of the layer.

Specifically, the first component 110 may be any component in an integrated circuit, such as a logic element, a transmission element, an inversion element, an operation element, or the like. In the embodiment of the present invention, the first component 110 is taken as an example, and the large driving component may be a large driving logic component.

For the first component 110, before the first power supply network is locally provided, the isolation unit 120 is provided; the isolation unit 120 surrounds the first component 110 and is disposed at the same layer as the first component 110. Thus, the isolation unit 120 may function to include at least: the first component 110 is isolated from other components in the integrated circuit so as not to influence each other, input and output signals of the first component 110 are optimized, the design of the structure of the integrated circuit device meets the electrical characteristics and the process characteristics of the integrated circuit design, and the first component 110 is provided with a first power supply network in a targeted and local mode.

The first power grid is located on one side of the first component 110 and is electrically connected to the first component 110. For example, if the first component 110 is on the lower layer and the first power network is on the upper layer, the first power network may provide current to the first component 110 from top to bottom. The first power network supplies power to the first component 110, including but not limited to a power voltage VDD and a ground voltage VSS.

The first power supply network includes a plurality of first metal layers stacked one on another, and may be a plurality of first metal layers stacked one on another in sequence. For example, a first layer first metal layer a1, a second layer first metal layer a2, a …, An nth layer first metal layer An (the first metal layer is marked with a letter a) are sequentially stacked in a direction away from the first component 110, where n is a positive integer. The first layer of the first metal layer a1 and the second layer of the first metal layer a2 are illustrated in fig. 1 by way of example only, with the first layer of the first metal layer a1 being located between the second layer of the first metal layer a2 and the first component device 110. In practice, n may be less than 15 or more than 15, and the number of the first metal layers is not particularly limited in the embodiment of the present invention.

The first metal layer of the same layer includes a plurality of first power lines 130 parallel to each other, and any two first power lines 130 are insulated from each other. As exemplarily illustrated in fig. 1, the first layer of the first metal layer a1 includes four first power lines 130_1, 130_2, 130_3, and 130_4 that are parallel to each other and insulated from each other; the second layer of the first metal layer a2 includes four first power lines 130_5, 130_6, 130_7, and 130_8 that are parallel to each other and insulated from each other.

The extending direction of the first power line of one of the two adjacent first metal layers is staggered with the extending direction of the first power line of the other first metal layer, and the two first power sources with staggered extending directions are electrically connected at the staggered section. As exemplarily illustrated in fig. 1, the first layer of the first metal layer a1 is adjacent to the second layer of the first metal layer a2, the extending direction of the first power line 130_2 of the first layer of the first metal layer a1 is perpendicular to the extending direction of the first power line 130_5 of the second layer of the first metal layer a2, and the first power line 130_2 and the first power line 130_5 are electrically connected at the interleaved section 131 thereof. For example, when the staggered segment 131 is electrically connected through the conductive via, the current on the first power line 130_5 may flow to the first component device 110 through the conductive via and the first power line 130_2 in sequence, thereby implementing the first power network to provide the current to the first component device 110 from top to bottom.

On this basis, the vertical projection of the first power net is located within the vertical projection of the isolation unit 120 in the same direction (e.g. in a direction perpendicular to the surface of the first component 110). The arrangement is such that the vertical projection of the first metal layer in the first power supply network is located within the vertical projection of the isolation unit 120, that is, the vertical projection of the first power supply line of the first metal layer is located within the vertical projection of the isolation unit 120, so that the line length of the first power supply line is limited within the boundary of the isolation unit 120. Embodiments of the present invention thus ensure that the first power line within the first power network supplying power to the first component 110 has a smaller line length.

According to the Blech effect: when the line length of the metal line is smaller than a specific threshold value, the maximum current value allowed to pass through the metal line is larger, and the electromigration effect is less obvious. Accordingly, the embodiment of the present invention locally provides the first power network to the first component device 110, and the line length of the first power line in the first power network is limited to be less than or equal to the specific threshold value based on the isolation unit 120, so as to avoid the electromigration phenomenon of the first power line supplying power to the first component device 110, thereby improving the electromigration phenomenon of the first power network.

In the embodiment of the invention, in the first power supply network, each layer of the first metal layer corresponds to a preset basic line width, and the preset basic line width of the first metal layer is specifically the preset basic line width of the first power supply line of the first metal layer. The preset basic line widths corresponding to any two layers of first metal layers can be the same or different. The predetermined base line width may be understood as a conventionally set line width of a power line in any power network capable of supplying power to the first component 110, that is, a line width set without considering factors such as voltage drop but considering only factors such as process specification requirements and transmission of current to the first component 110. The conventionally set line width can be determined in advance according to actual requirements before the power grid is manufactured. In general, in a power supply network, a line width of a power supply line with multiple metal layers in a conventional arrangement tends to gradually increase along a direction away from a component. In view of this, in the embodiment of the present invention, the preset basic line width is increased from the first metal layer a1 to the nth first metal layer An in the first power net. As exemplarily illustrated in fig. 1, the preset basic line width d1 of the first power line of the first metal layer a1 is smaller than the preset basic line width d2 of the first power line of the second metal layer a2, and the line widths or the preset basic line widths of the first power lines in the same first metal layer are the same.

To this end, in the embodiment of the present invention, in the first power net, the line width index of at least one first metal layer is greater than 1, and the line width index of the first metal layer is a ratio of the line width of the first power line of the first metal layer to the preset basic line width of the layer. As exemplarily illustrated in fig. 1, the line width of the first power line of the first layer first metal layer a1 is D1, the line width index of the first layer first metal layer a1 is D1/D1, and D1 is greater than D1, the line width index of the first layer first metal layer a1 is greater than 1; the line width of the first power line of the second first metal layer a2 is equal to the preset basic line width d2, and the line width index of the second first metal layer a2 is d2/d2, that is, the line width index of the second first metal layer a2 is d2/d2 is equal to 1. It can be seen that setting the line width index of at least one first metal layer in the first power network to be greater than 1 means that the line width of the first power line of at least one first metal layer in the first power network is obtained by widening the line width of the layer on the preset basis. For example, the line width D1 of the first power line of the first metal layer a1 is widened above the predetermined basic line width D1 of the first metal layer a1, and the added width is (D1-D1).

The embodiment of the invention is arranged in such a way that on the basis of ensuring that the line length of the first power line in the first power network is smaller, the line width of the first power line of at least one first metal layer in the first power network is widened on the preset basic line width of the layer, so that on one hand, the equivalent resistance of the first power line of the at least one first metal layer is reduced, the voltage drop is reduced, and on the other hand, according to the Blech effect, the maximum current value allowed by the at least one first power line is increased, and the electromigration effect is less obvious. Accordingly, the voltage drop in the first power supply network is reduced, and the electromigration phenomenon in the first power supply network is further improved.

As mentioned in the background art, when the first component 110 is a large driving component, the line length of the low-level power line where the large driving component is located is generally long, and the electromigration phenomenon is serious. In contrast, in the embodiment of the present invention, the vertical projection of the first power line of each first metal layer in the first power network is always located within the vertical projection of the isolation unit 120, that is, the line length of the first power line of each first metal layer is limited to be smaller, so that the first power line of each first metal layer is not easy to generate the electromigration phenomenon, that is, the electromigration phenomenon of each first metal layer is improved. Here, the first power line of the first layer a1 and/or the second layer a2 may be considered as a power line of a lower layer where the first component 110 is located; alternatively, all the first power lines of the first metal layer in the first power network may be considered as the power lines of the lower layer where the first component device 110 is located.

Further, for example, the first component 110 may be powered by a plurality of power grids stacked on top of each other and electrically connected to each other, one of the power grids stacked on top of each other and electrically connected to each other is a first power grid, and the first power grid is closest to the first component 110 compared to the rest of the power grids, and the first power grid may include a first layer to a fifth layer of first metal layers, that is, five layers of first metal layers in total. Based on the technical scheme of the embodiment of the invention, the vertical projections of the first power lines of the five first metal layers are all positioned in the vertical projection of the isolation unit 120, so that the lengths of the first power lines of the five first metal layers are all smaller, and the electromigration phenomenon of the first power grid is less obvious. Further, since the first power supply network is closest to the first component 110, at this time, the first to fifth first metal layers may all belong to the lower-level metal layers in the power supply network that supplies power to the first component 110, and the preset basic line width of the lower-level metal layers is smaller and the conventional layer thickness is thinner, so that the line widths of the first power lines of the first to fifth first metal layers may be widened on the preset basic line width of the layer, respectively, thereby reducing the voltage drop in the first power supply network and further improving the electromigration phenomenon of the first power supply network.

Finally, the power lines near the large drive components need to carry more current, resulting in a larger voltage drop. In this regard, in the embodiment of the present invention, the first power line of the first metal layer a1 and/or the second metal layer a2 may also be the first power line of the first to nth first metal layers, and the line widths of the first power line of the first to nth first metal layers are widened on a predetermined basis, so as to reduce the equivalent resistance thereof, reduce the voltage drop thereon, and further improve the electromigration phenomenon thereon. Here, the first power line of the first layer first metal layer a1 and/or the second layer first metal layer a2 may be considered as a power line located near the first component device 110.

Fig. 2 is a schematic top view of another integrated circuit device structure according to an embodiment of the present invention. Referring to fig. 2, on the basis of the foregoing embodiments, optionally, in the first power net, in a direction in which the first component device 110 points to the first power net, a line width index of the first metal layer is in a decreasing trend; the minimum value of the line width index of each first metal layer is 1. The minimum line width of the first power line of the first metal layer is equal to the preset basic line width of the first power line, so that the minimum value of the line width index of the first metal layer is 1.

Specifically, in comparison, the power line with a smaller predetermined basic line width is more susceptible to electromigration and has a larger equivalent resistance than the power line with a larger predetermined basic line width; therefore, in improving the electromigration phenomenon and the large voltage drop phenomenon of the first power supply network, the widening degree of the first power supply line having the smaller predetermined basic line width may be slightly larger, and the widening degree of the first power supply line having the larger predetermined basic line width may be slightly smaller.

Accordingly, since the preset basic line width of the first metal layer is in an increasing trend in the direction in which the first component 110 points to the first power grid, the line width index of the first metal layer is in a decreasing trend in the direction in which the first component 110 points to the first power grid, that is, the widening degree of the first power line of the first metal layer is in a decreasing trend in the direction in which the first component 110 points to the first power grid, thereby reasonably improving the electromigration phenomenon and the large voltage drop phenomenon of the first power grid.

It is understood that the widening degree of the first power line of the multi-layer first metal layer is in a decreasing trend, and it is not limited that the widening degrees decrease from layer to layer, but the widening degrees of the first layer and the second layer are allowed to be the same, the widening degree of the third layer and the fourth layer is allowed to be the same, and the widening degree of the third layer is smaller than the widening degree of the second layer.

Illustratively, as shown in fig. 2, the first layer first metal layer a1 and the second layer first metal layer a2 are both widened at a preset base line width of the present layer. That is, for the first layer first metal layer a1, widening is performed on the preset basic line width D1, and the line width of the first layer first metal layer a1 is D1, and the added width is (D1-D1); widening the second layer first metal layer A2 at a preset basic line width D2 to obtain a second layer first metal layer A2 with a line width D2 and a sum width (D2-D2); wherein D2 is greater than D1 and (D1-D1) is greater than (D2-D2).

On the basis of the foregoing embodiments, optionally, the first metal layer with a line width index greater than 1 has a line width index in a range from 1.5 to 2. Specifically, the line width index is too large, which may easily cause a violation of physical design rules with a metal layer inside the first component 110 or cause the input and output signal lines of the first component 110 to be unable to go through; the line width index is not small enough to improve the electromigration phenomenon and the large voltage drop phenomenon in the first power supply network. The range of the line width index of the first metal layer with the line width index larger than 1 is set to be 1.5-2, so that the first component is ensured not to be violated by physical design rules around the first component, and the electromigration phenomenon and the large voltage drop phenomenon can be improved well. For example, D1/D1 is equal to 1.8, i.e., the linewidth of the first metal layer A1 is 1.8; meanwhile, D2/D2 is equal to 1.5, i.e., the line width index of the first metal layer A2 of the second layer is 1.5.

Fig. 3 is a schematic top view of another integrated circuit device structure according to an embodiment of the present invention. Referring to fig. 3, based on the foregoing embodiments, optionally, in the first power network, a line number index of at least one first metal layer is greater than 1; the line number index of the first metal layer is the ratio of the number of the first power lines of the first metal layer to the number of the preset basic lines of the layer.

Specifically, in two adjacent first metal layers, two first power lines with mutually staggered extension directions are electrically connected at staggered sections of the first power lines through conductive through holes; one staggered section corresponds to one conductive through hole, and one conductive through hole can be equivalent to one resistor. Therefore, a plurality of conductive through holes are arranged between two adjacent first metal layers, and the equivalent is that a plurality of resistors are connected in parallel between the two adjacent first metal layers. Thus, when the number of the conductive through holes arranged between the two adjacent first metal layers is small, the number of the resistors connected in parallel between the two adjacent first metal layers is small, so that the total equivalent resistance between the two adjacent first metal layers is large, the equivalent resistance of the first power supply network is large, and the voltage drop in the first power supply network is large; when the number of the conductive through holes arranged between the two adjacent first metal layers is large, the number of the resistors connected in parallel between the two adjacent first metal layers is large, so that the total equivalent resistance between the two adjacent first metal layers is small, the equivalent resistance of the first power supply network is small, and the voltage drop in the first power supply network is small.

In the embodiment of the invention, in the first power supply network, each layer of the first metal layer corresponds to a preset number of basic lines, and the preset number of basic lines of the first metal layer is specifically the preset number of basic lines of the first power supply line of the first metal layer. The numbers of the preset base lines corresponding to any two layers of the first metal layers can be the same or different. The predetermined number of base lines may be understood as the number of conventional arrangement lines of power lines in any power net metal layer capable of supplying power to the first component 110, i.e., the number of power lines arranged without consideration of equivalent resistance and the like, but only considering process specification requirements and factors of transmitting current to the first component 110. The number of the conventional setting lines can be determined in advance according to actual requirements before the power grid is manufactured. In general, in the power supply network, the number of the conventional arrangement lines of the power supply lines of each metal layer is the same. In view of this, in the embodiment of the present invention, the first power net is exemplarily disposed from the first metal layer a1 to the nth first metal layer An, and the number of the predetermined basic lines is the same. As exemplarily illustrated in fig. 1 and 2, the number of the predetermined basic lines of the first metal layer a1 is the same as the number of the predetermined basic lines of the second metal layer a2, and each of the predetermined basic lines is four first power lines.

In the embodiment of the invention, at least one first metal layer in the first power network has a wire number index greater than 1; the line number index of the first metal layer is the ratio of the number of the first power lines of the first metal layer to the number of the preset basic lines of the layer. As exemplarily illustrated in fig. 1 or fig. 2, the number of the predetermined basic lines of the first layer first metal layer a1 is four, as exemplarily illustrated in fig. 3, the number of the lines of the first layer first metal layer a1 is six, and in fig. 3, compared to fig. 2, the first power line 130_9 and the first power line 130_10 are newly added to the first layer first metal layer a1, and at this time, the number of the lines of the first layer first metal layer a1 is a ratio of six to four, that is, greater than 1; and, as exemplarily shown in fig. 1 or fig. 2, the number of the predetermined basic lines of the second layer first metal layer a2 is four, as exemplarily shown in fig. 3, the number of the lines of the second layer first metal layer a2 is five, and in fig. 3, compared to fig. 2, the first power line 130_11 is newly added to the second layer first metal layer a2, and at this time, the number of the lines of the second layer first metal layer a2 is a ratio of five to four, which is greater than 1.

It can be seen that the index of the number of lines of at least one first metal layer in the first power network is set to be greater than 1, which means that the number of first power lines of at least one first metal layer in the first power network is obtained by adding a certain number of first power lines above the number of preset basic lines of the layer. For example, the number of first power lines of the first metal layer a1 is obtained by adding two first power lines above four predetermined basic lines of the first metal layer a 1; the number of the first power lines of the second first metal layer a2 is obtained by adding a new first power line above the number of four predetermined basic lines of the second first metal layer a 2.

The arrangement of the embodiment of the invention ensures that the number of lines of the first power line of at least one first metal layer in the first power network is increased on the basis of ensuring that the length of the first power line in the first power network is smaller. When the number of the first power lines of any one layer of the first metal layer is increased, the number of the conductive through holes between the layer of the first metal layer and the adjacent first metal layer is increased, which is equivalent to the number of the resistors connected in parallel between the layer of the first metal layer and the adjacent first metal layer, so that the total equivalent resistance between the layer of the first metal layer and the adjacent first metal layer is reduced, the equivalent resistance of the first power network is reduced, and the voltage drop in the first power network is reduced. According to the embodiment of the invention, the equivalent resistance of the first power supply network is reduced, so that the voltage drop of the first power supply network is reduced.

On the basis of the foregoing embodiments, optionally, in the first power grid, in a direction in which the first component 110 points to the first power grid, the line number index of the first metal layer is in a decreasing trend; the minimum value of the index of the number of lines of each first metal layer is 1. The minimum number of the first power lines of the first metal layer is equal to the number of the preset basic lines of the layer, so that the minimum value of the line number index of each first metal layer is 1.

In particular, the power line with a smaller line width is more susceptible to electromigration and has a larger equivalent resistance than the power line with a larger line width; therefore, in improving the electromigration phenomenon and the large voltage drop phenomenon of the first power supply network, the number of the first power supply lines in the first metal layer having a smaller line width may be increased slightly more, and the number of the first power supply lines in the first metal layer having a larger line width may be increased slightly less.

Therefore, since the line width of the first metal layer increases in the direction in which the first component 110 points to the first power supply network, the line number index of the first metal layer decreases in the direction in which the first component 110 points to the first power supply network, that is, the line number increase of the first power line of the first metal layer decreases in the direction in which the first component 110 points to the first power supply network, thereby reasonably improving the electromigration phenomenon and the large voltage drop phenomenon of the first power supply network. For example, comparing fig. 3 and fig. 2, the number of first power lines of the first layer first metal layer a1 is increased by two, and the number of first power lines of the second layer first metal layer a2 is increased by one. It can be understood that, the line number increase of the first power line of the multi-layer first metal layer is in a decreasing trend, and the line number increase is not limited to decrease gradually from layer to layer, but the line number increase of the first layer and the second layer is allowed to be the same, the line number increase of the third layer is allowed to be the same as the line number increase of the fourth layer, the line number increase of the third layer is smaller than the line number increase of the second layer, and the like.

It should be noted that the technical features in the embodiments of the present invention may be arbitrarily combined. For example, in the first power supply network provided by the embodiment of the present invention, the line width may be increased only for the first power supply line of the at least one first metal layer on the basis of limiting the first power supply line to have a smaller line length; the number of lines can be increased only for the first power line of the at least one first metal layer on the basis of limiting the first power line to have a smaller line length; the line width of the first power line of the at least one first metal layer can be increased, and the number of lines of the first power line of the at least one first metal layer can be increased on the basis of limiting the first power line to have a smaller line length.

Fig. 4 is a schematic top-view structure diagram of an isolation unit according to an embodiment of the present invention, and fig. 4 further illustrates the first component 110. Referring to fig. 4, the isolation unit 120 includes: a coupling capacitor subunit 121, a first boundary subunit 122 and a second boundary subunit 124. The coupling capacitor sub-unit 121 is disposed around the first component 110, contacts the first component 110, and is used to reduce noise of the first component 110; the first boundary subunit 122 is disposed around (or may be half-around or surround) the coupling capacitor subunit 121, and is in contact with the coupling capacitor subunit 121; the second boundary subunit 124 is disposed around the first boundary subunit 122; the second boundary subunit 124 and the first boundary subunit 122 have an isolation zone 123 therebetween; wherein, in the same direction, the vertical projection of the first power grid is located within the vertical projection of the isolation strip 123.

In particular, the coupling capacitor subunit 121 is, for example, a high-frequency coupling capacitor unit, and may be used to optimize the input and output signals of the first component 110, for example, to reduce noise of the first component 110 when the first component 110 is flipped. The first border subcell 122 serves as a border cell of the integrated circuit device structure such that the cell design within the area including the first border subcell 122 (i.e., including the area where the first component 110 is located) satisfies the electrical and process characteristics of the integrated circuit design.

The isolation zone 123 is a blank area between the first boundary subunit 122 and the second boundary subunit 124, and the blank area is an area where no material may be disposed to isolate the first component 110 from other components in the integrated circuit. The second boundary subunit 124 is a boundary unit of a common component (i.e., a boundary unit of other components in the integrated circuit) such that the cell design in the region outside the second boundary subunit 124 (i.e., the region including the common component) satisfies the electrical and process characteristics of the integrated circuit design.

Since the second boundary subunit 124 is used as a boundary unit of a common component, the vertical projection of the first power grid can be set to be located within the vertical projection of the isolation strip 123 in the same direction. Optionally, in the same direction, the vertical projection of the first power line is located within the vertical projection of the isolation strip 123 and beyond the vertical projection of the first boundary subunit 122.

The embodiment of the present invention further provides an integrated chip, where the integrated chip includes at least one integrated circuit device structure provided in any of the above technical solutions, and each integrated circuit device structure is arranged in the same layer. Accordingly, the integrated chip and the integrated circuit device structure belong to the same inventive concept, and can achieve the same technical effect, and repeated content is not repeated here.

Fig. 5 is a schematic top view of an integrated chip according to an embodiment of the present invention. Referring to fig. 5, on the basis of the foregoing embodiments, optionally, the integrated chip further includes: a second power supply network and a plurality of second components 210; the second component 210 is disposed on the same layer as the first component 110 and is located at the periphery of the isolation unit 120; the second power grid is disposed on the same layer as the first power grid and electrically connected to the second component 210; the second power supply network comprises a plurality of second metal layers which are arranged in a stacked mode; the second metal layers correspond to the first metal layers one by one, and the second metal layers and the corresponding first metal layers are arranged on the same layer; the second metal layer on the same layer comprises a plurality of second power lines which are parallel to each other, and any two second power lines are insulated from each other; two adjacent second metal layers, wherein the extending direction of the second power line of one second metal layer is staggered with the extending direction of the second power line of the other second metal layer, and the two second power lines with staggered extending directions are electrically connected at the staggered section;

the line width index and the line number index of the second metal layer are both 1, the line width index of the second metal layer is the ratio of the line width of a second power line of the second metal layer to the preset basic line width of the layer, and the line number index of the second metal layer is the ratio of the number of the second power lines of the second metal layer to the preset basic line number of the layer; the preset basic line width of the second metal layer is equal to the preset basic line width of the corresponding first metal layer; the first metal layer and the second metal layer are arranged on the same layer, and the extending directions of the first power line and the second power line are collinear or parallel.

In particular, the second component 210 may be any component in an integrated circuit, such as a logic unit, a transmission element, an inversion element, or an arithmetic element. In the embodiment of the present invention, the second component 210 is taken as an example of a common component. The second component 210 is disposed on the same layer as the first component 110 and is located at the periphery of the isolation unit 120, that is, in the integrated circuit, the isolation unit 120 may be disposed only on the first component 110 without disposing the isolation unit 120 on the second component 210, and at this time, the isolation unit 120 is located between the first component 110 and the second component 210.

For a plurality of second components 210 (or one second component 210), a second power supply network is directly disposed, the second power supply network is disposed on the same layer as the first power supply network, and the second power supply network and the plurality of second components 210 are all electrically connected to simultaneously supply power to the plurality of second components 210, where the supplied power includes, but is not limited to, a power supply voltage VDD and a ground voltage VSS.

The second power supply network includes a plurality of second metal layers stacked in layers, and may be a plurality of second metal layers stacked in sequence. For example, a first layer of the second metal layer B1, a second layer of the second metal layer B2, a … and an nth layer of the second metal layer Bn are sequentially stacked along a direction away from the second component 210 or the first component 110, where n is a positive integer. The first layer of the second metal layer B1 and the second layer of the second metal layer B2 are illustrated in FIG. 5 as examples only, with the first layer of the second metal layer B1 being between the second layer of the second metal layer B2 and the second component 210.

The second metal layers correspond to the first metal layers one by one, and the second metal layers and the corresponding first metal layers are arranged on the same layer. The first layer second metal layer B1, as exemplarily illustrated in fig. 5, is in a same layer as the first layer first metal layer a1, which corresponds thereto; the second layer, second metal layer B2, is on the same layer as the second layer, first metal layer A2, and corresponds thereto, the second metal layer being labeled with the letter B.

As exemplarily illustrated in fig. 5, the first-layer second metal layer B1 includes at least six second power supply lines 230_1, 230_2, 230_3, 230_4, 230_5, and 230_ 6; the second layer second metal layer B2 includes at least six second power supply lines 230_7, 230_8, 230_9, 230_10, 230_11, and 230_ 12. As exemplarily illustrated in fig. 5, the first layer second metal layer B1 is adjacent to the second layer second metal layer B2, the extending direction of the second power line 230_2 of the first layer second metal layer B1 is perpendicular to the extending direction of the second power line 230_11 of the second layer second metal layer B2, and the second power line 230_2 and the second power line 230_11 are electrically connected at the interleaved section 231 thereof. For example, when the interleaved segments 231 are electrically connected through the conductive via, the current on the second power line 230_11 can flow to the second component device 210 through the conductive via and the second power line 230_2 in sequence.

In the embodiment of the invention, the first metal layer and the second metal layer are arranged on the same layer, and the extending directions of the first power line and the second power line are collinear. The first layer of the first metal layer a1 and the first layer of the second metal layer B1 are located at the same layer as exemplarily illustrated in fig. 5, wherein the first power line 130 and the second power line 230 extend in the same line; the second layer of the first metal layer a2 and the second layer of the second metal layer B2 are located on the same layer, and the extending directions of the first power line 130 and the second power line 230 are also collinear. Alternatively, the first and second liquid crystal display panels may be,

the first metal layer and the second metal layer are arranged on the same layer, and the extending directions of the first power line and the second power line are parallel. This may occur when the number of lines of the first power line of any one of the first metal layers in the first power grid increases above the preset base number of lines in the layer, and the first metal layer is parallel to the extending direction of the first power line and the second power line in the same layer, or the extending direction of part of the first power line and part of the second power line is collinear and the extending direction of part of the first power line and part of the second power line is parallel.

In the embodiment of the invention, in the second power supply network, each layer of second metal layer corresponds to a preset basic line width respectively, and the preset basic line width of the second metal layer is specifically the preset basic line width of the second power supply line of the second metal layer; the preset basic line widths corresponding to any two layers of second metal layers can be the same or different; moreover, the preset basic line width of the second metal layer is equal to the preset basic line width of the corresponding first metal layer (i.e. the first metal layer disposed on the same layer). As exemplarily illustrated in fig. 5, the preset base line width m1 of the first layer second metal layer B1 is equal to the preset base line width d1 of the first layer first metal layer a 1; and the predetermined basic line width m2 of the second layer second metal layer B2 is equal to the predetermined basic line width d2 of the second layer first metal layer a 2.

On this basis, the line width index of each second metal layer is 1, that is, the line width of each second metal layer is equal to the preset basic line width of the layer. As exemplarily illustrated in fig. 5, the line width of the first layer second metal layer B1 is a preset base line width m1 of the first layer second metal layer B1, and m1 is equal to d 1; the line width of the second layer second metal layer B2 is equal to the predetermined base line width m2 of the second layer second metal layer B2, and m2 is equal to d 2.

In the second power supply network, each layer of second metal layer corresponds to a preset number of base lines, and the preset number of base lines of the second metal layer is specifically the preset number of base lines of the second power supply line of the second metal layer. The number of the preset basic lines respectively corresponding to any two layers of the second metal layers can be the same or different. The number of the second power lines or the number of the predetermined basic lines may be the same as or different from the number of the first power lines or the number of the predetermined basic lines. On the basis, in the embodiment of the present invention, the index of the number of the second metal layers is 1, that is, the number of the second power lines of the second metal layer is equal to the number of the preset basic lines of the layer.

Based on the above, the embodiment of the present invention further provides a method for forming a first power grid of the first component 110, which includes the following main steps: providing a first component 110; providing an isolation unit 120 for the first component 110; arranging other common components, namely a second component 210, at the periphery of the isolation unit 120, wherein the second component 210 and the first component 110 are arranged at the same layer; a power supply network is arranged on one side of the second component 210, wherein the second component 210 is positioned on the lower layer, and the power supply network is positioned on the upper layer; in the same direction, the vertical projections of the second component 210, the isolation unit 120 and the first component 110 are all located in the vertical projection of the set power grid; within the vertical projection of the isolation unit 120, the set power grid is cut accordingly to cut the set power grid into the second power grid in the embodiment of the present invention and the local power grid for the first component 110, and the power line in the local power grid can be used as the first power line in the embodiment; the line width of the power line of at least one metal layer in the local power network is widened above the current line width of the layer and/or increased above the current line number of the layer, so that the first power network of the first component 110 in this embodiment can be formed, where the current line width of the layer is the preset basic line width of the layer in this embodiment of the present invention, and the current line number of the layer is the preset basic line number of the layer in this reverse embodiment.

That is, the first power supply network of the first component 110 and the second power supply network of the second component 210 provided in the embodiment of the present invention may be formed in the same process at an initial manufacturing stage (i.e., a stage before the set power supply network is cut), and the first power supply network may be formed only by widening the line width of the power supply line of at least one metal layer in the local power supply network and/or increasing the number of lines of the power supply line after the second power supply network and the local power supply network are formed by cutting the power supply network. The method for forming the first power grid has the advantages of fewer process steps, simplicity and high practicability.

Fig. 6 is a schematic cross-sectional view of another integrated chip according to an embodiment of the present invention. Referring to fig. 6, on the basis of the foregoing embodiments, optionally, the integrated chip further includes: a third power supply network; the third power supply network is located on a side of the first power supply network away from the first component 110; in the same direction, the vertical projections of the first power supply network and the second power supply network are both positioned in the vertical projection of a third power supply network, and the third power supply network is electrically connected with the first power supply network and the second power supply network; the third power supply network comprises a plurality of third metal layers which are stacked; the third metal layer on the same layer comprises a plurality of third power lines which are parallel to each other, and any two third power lines are insulated from each other; the extending directions of the third power lines of one layer of the third metal layer are staggered with the extending directions of the third power lines of the other layer of the third metal layer, and the two staggered extending directions of the two third power lines are electrically connected at the staggered section;

the line width index and the line number index of the third metal layer are both 1, the line width index of the third metal layer is the ratio of the line width of a third power line of the third metal layer to the preset basic line width of the layer, and the line number index of the third metal layer is the ratio of the number of the third power lines of the third metal layer to the preset basic line number of the layer; the extension directions of the third power line and the second power line are collinear.

In the third power supply network, each layer of the third metal layer corresponds to a preset basic line width, and the preset basic line width of the third metal layer is specifically the preset basic line width of the third power supply line of the third metal layer; the preset basic line widths corresponding to any two layers of the third metal layers can be the same or different. In the third power supply network, each layer of the third metal layer corresponds to a preset basic line number, and the preset basic line number of the third metal layer is specifically the preset basic line number of the third power supply line of the third metal layer; the number of the preset basic lines respectively corresponding to any two layers of the third metal layers can be the same or different. On the basis, in the embodiment of the present invention, the line width index and the line number index of the third metal layer are both 1, that is, the line width of the third power line of the third metal layer is equal to the preset basic line width of the layer, and the number of the third power lines of the third metal layer is equal to the preset basic line number of the layer.

In an embodiment of the present invention, the second component 210 shares a third power network with the first component 110. That is, for the second component 210, the third power network transmits power to the second power network, and the second power network continues to transmit power to the second component 210; for the first component 110, the third power network transmits power to the first power network, and the power is transmitted from the first power network to the first component 110. Illustratively, as shown in fig. 6, the third power line 330 transmits power to the second power line 230 and the first power line 130 at the same time, the second power line 230 transmits power to the second component 210 through the solder tail 400, and the first power line 130 transmits power to the first component 110 through the solder tail 400. In addition, as mentioned previously, of the two power nets (the first power net and the third power net) of the first component 110, the first power net is closest to the first component 110, and therefore, all the first metal layers in the first power net belong to the lower-level metal layers in the power nets that supply power to the first component 110.

On the basis of the above embodiments, optionally, the third power supply network, the second power supply network and the first power supply network are integrally provided.

Specifically, the third power supply network, the second power supply network, and the first power supply network are integrally configured, which means that the whole power supply network of the first component 110 and the whole power supply network of the second component 210 are originally the same power supply network; however, since the first component 110 is a large driving component, and the entire power supply network thereof needs to be set specifically, on the basis that the first component 110 and the second component 210 share the same power supply network, the power supply network is cut according to the vertical projection of the isolation unit 120 to be cut into a local power supply network, a third power supply network in the embodiment of the present invention, and a second power supply network in the embodiment of the present invention, and a power line in the local power supply network can be used as a first power line in the embodiment of the present invention; the line width of the power line of at least one metal layer in the local power network is widened above the current line width of the layer and/or increased above the current line number of the layer, so that the first power network of the first component 110 in this embodiment can be formed, where the current line width of the layer is the preset basic line width of the layer in this embodiment of the present invention, and the current line number of the layer is the preset basic line number of the layer in this reverse embodiment.

Further, for example, originally, the first component 110 and the second component 210 share the same power supply network, the power supply network has fifteen metal layers, and along the direction in which the first component 110 points to the power supply network, the first five metal layers belong to lower-level metal layers for the first component 110, and electromigration and voltage drop on the lower-level metal layers are all obvious. Accordingly, within the vertical projection of the isolation unit 120, the power supply net is cut accordingly, and only the first five metal layers along the direction in which the first component 110 points to the power supply net are cut, thereby forming the third power supply net in this embodiment, the second power supply net in this embodiment, and the local power supply net for the first component 110, and the power supply line in the local power supply net can be used as the first power supply line in this embodiment; the line width of the power line of at least one metal layer in the local power network is widened above the current line width of the local layer and/or increased above the current line number of the local layer, so that the first power network of the first component 110 in this embodiment may be formed, where the first power network includes five first metal layers, the second power network includes five second metal layers, and the third power network includes ten third metal layers. Moreover, it can be obtained that, since the metal layers (i.e., the sixth layer to the fifteenth layer) after the first five metal layers do not belong to the low-level metal, electromigration and voltage drop thereof are less obvious, and thus the first component 110 does not need to be specifically configured, the metal layers after the first five metal layers do not need to be cut, so that the first component 110 and the second component 210 continue to maintain the overall sharing of the metal layers in the metal layers after the first five metal layers.

And if it is observed from practical situations that the first seven metal layers belong to lower-level metal layers for the first component 110 along the direction in which the first component 110 points to the power supply network, within the vertical projection of the isolation unit 120, the power supply network is cut accordingly, and only the first seven metal layers along the direction in which the first component 110 points to the power supply network are cut, thereby forming a third power supply network in the present embodiment, a second power supply network in the present embodiment, and a local power supply network for the first component 110, and a power line in the local power supply network may be used as a first power line in the present embodiment; the line width of the power line of at least one metal layer in the local power network is widened above the current line width of the local power network and/or increased above the current line number of the local power network, so that the first power network of the first component 110 in the present embodiment can be formed, at this time, the first power network includes seven first metal layers, the second power network includes seven second metal layers, the third power network includes eight third metal layers, and the first component 110 and the second component 210 continue to maintain the overall sharing of the metal layers in the metal layers after the first seven metal layers.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims (10)

1. An integrated circuit device structure, comprising:

a first component;

an isolation unit surrounding the first component and disposed at the same layer as the first component;

a first power supply network including a plurality of first metal layers arranged in a stack; the first power grid is positioned on one side of the first component and is electrically connected with the first component;

the first metal layer on the same layer comprises a plurality of first power lines which are parallel to each other, and any two first power lines are insulated from each other;

two adjacent first metal layers, wherein the extending direction of the first power line of one first metal layer is staggered with the extending direction of the first power line of the other first metal layer, and two first power sources with staggered extending directions are electrically connected at staggered sections;

wherein, in the same direction, the vertical projection of the first power grid is located within the vertical projection of the isolation unit; in the first power supply network, the line width index of at least one first metal layer is greater than 1; the line width index of the first metal layer is the ratio of the line width of the first power line of the first metal layer to the preset basic line width of the layer;

the preset base line width is a line width when the first power line satisfies a first base condition, the first base condition including: the first power line can provide current required by the first component, and the first power line is a power line in an integrated circuit power network;

in the same direction, the vertical projection of the isolation unit and the vertical projection of the first power grid are overlapped.

2. The integrated circuit device structure of claim 1, wherein a line width indicator of the first metal layer decreases in a direction from the first component toward the first power net within the first power net; the minimum value of the line width index of each first metal layer is 1.

3. The integrated circuit device structure of claim 1, wherein the first metal layer having a line width index greater than 1 has a line width index in a range from 1.5 to 2.

4. The integrated circuit device structure of any of claims 1 to 3, wherein at least one of said first metal layers within said first power network has a line count index greater than 1; the line number index of the first metal layer is the ratio of the number of the first power lines of the first metal layer to the number of preset basic lines of the layer;

the preset number of basic lines is the number of the first power lines in the first metal layer when the first metal layer satisfies a second basic condition, and the second basic condition includes: the first metal layer is capable of providing the current required by the first element device, and the first metal layer is a metal layer in an integrated circuit power supply network.

5. The integrated circuit device structure of claim 4, wherein a line count index of the first metal layer decreases in a direction in which the first component points toward the first power net within the first power net; the minimum value of the line number index of each first metal layer is 1.

6. The integrated circuit device structure of claim 1, wherein the isolation unit comprises:

a coupling capacitor subunit, disposed around and in contact with the first component, and configured to reduce noise of the first component;

a first boundary subunit disposed around the coupling capacitor subunit and contacting the coupling capacitor subunit;

a second boundary subunit disposed around the first boundary subunit; an isolation strip is arranged between the second boundary subunit and the first boundary subunit;

and in the same direction, the vertical projection of the first power supply network is positioned in the vertical projection of the isolation strip.

7. An integrated chip comprising at least one integrated circuit device structure as claimed in any one of claims 1 to 6; and the integrated circuit device structures are arranged on the same layer.

8. The integrated chip of claim 7, further comprising:

a plurality of second components; the second component and the first component are arranged on the same layer and are positioned on the periphery of the isolation unit;

a second power supply network including a plurality of second metal layers stacked; the second power supply network and the first power supply network are arranged on the same layer and are electrically connected with the second component; the second metal layers correspond to the first metal layers one by one, and the second metal layers and the corresponding first metal layers are arranged on the same layer;

the second metal layer on the same layer comprises a plurality of second power lines which are parallel to each other, and any two second power lines are insulated from each other;

two adjacent second metal layers, wherein the extending direction of the second power line of one second metal layer is staggered with the extending direction of the second power line of the other second metal layer, and two second power sources with staggered extending directions are electrically connected at staggered sections;

the line width index and the line number index of the second metal layer are both 1, the line width index of the second metal layer is the ratio of the line width of the second power line of the second metal layer to the preset basic line width of the layer, and the line number index of the second metal layer is the ratio of the number of the second power lines of the second metal layer to the preset basic line number of the layer; the preset basic line width of the second metal layer is equal to the corresponding preset basic line width of the first metal layer; the first metal layer and the second metal layer are arranged on the same layer, and the extending directions of the first power line and the second power line are collinear or parallel.

9. The integrated chip of claim 8, further comprising:

a third power supply network, which is positioned on one side of the first power supply network far away from the first component; in the same direction, the vertical projections of the first power supply network and the second power supply network are both positioned in the vertical projection of the third power supply network, and the third power supply network is electrically connected with the first power supply network and the second power supply network;

the third power supply network comprises a plurality of third metal layers which are stacked;

the third metal layer on the same layer comprises a plurality of third power lines which are parallel to each other, and any two third power lines are insulated from each other;

two adjacent layers of the third metal layers, wherein the extending direction of the third power line of one layer of the third metal layer is staggered with the extending direction of the third power line of the other layer of the third metal layer, and the two third power lines with staggered extending directions are electrically connected at staggered sections;

the line width index and the line number index of the third metal layer are both 1, the line width index of the third metal layer is the ratio of the line width of the third power line of the third metal layer to the preset basic line width of the layer, and the line number index of the third metal layer is the ratio of the number of the third power lines of the third metal layer to the preset basic line number of the layer; the extension directions of the third power line and the second power line are collinear.

10. The integrated chip of claim 9, wherein the triple power supply net, the second power supply net, and the first power supply net are integrally disposed.

Images