CN114388431A - Method for forming semiconductor structure - Google Patents

Method for forming semiconductor structure Download PDF

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Publication number
CN114388431A
CN114388431A CN202011137111.9A CN202011137111A CN114388431A CN 114388431 A CN114388431 A CN 114388431A CN 202011137111 A CN202011137111 A CN 202011137111A CN 114388431 A CN114388431 A CN 114388431A
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layer
forming
side wall
sacrificial
groove
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金吉松
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to CN202011137111.9A priority Critical patent/CN114388431A/en
Publication of CN114388431A publication Critical patent/CN114388431A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005—Formation and after-treatment of dielectrics
    • H01L2221/101—Forming openings in dielectrics

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

A method for forming a semiconductor structure, the method comprising: providing a substrate comprising a target layer for forming a target pattern; forming a core layer extending in a first direction on a substrate, a direction perpendicular to the first direction being a second direction; forming a side wall on the side wall of the core layer, wherein the core layer and the side wall positioned on the side wall of the core layer form a pattern structure layer; forming a sacrificial layer crossing the pattern structure layer along a second direction on the substrate, wherein the sacrificial layer at least covers part of the top and part of the side wall of the pattern structure layer; forming a flat layer on the substrate exposed by the sacrificial layer and the pattern structure layer; removing the sacrificial layer, and forming first grooves in the flat layer, wherein the first grooves are positioned on two sides of the pattern structure layer; removing the core layer to enable the side walls to form a second groove in a surrounding mode; and etching the target layer below the first groove and the second groove by taking the flat layer and the side wall as masks to form a target pattern. The embodiment of the invention is beneficial to further compressing the pitch between the target graphics.

Description

Method for forming semiconductor structure
Technical Field
The embodiment of the invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure.
Background
With the rapid growth of the semiconductor Integrated Circuit (IC) industry, semiconductor technology is driven by moore's law to move towards smaller process nodes, so that the Integrated circuit is developed towards smaller size, higher circuit precision and higher circuit complexity.
In the development of integrated circuits, as the functional density (i.e., the number of interconnect structures per chip) generally increases, the geometric size (i.e., the minimum component size that can be produced by the process steps) also decreases, which increases the difficulty and complexity of integrated circuit fabrication.
At present, with the shrinking of technology nodes, it is a challenge how to improve the matching between the pattern formed on the wafer and the target pattern.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a method for forming a semiconductor structure, which is beneficial to further compressing the pitch between target patterns.
To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate comprising a target layer for forming a target pattern; forming a core layer extending in a first direction on the substrate, a direction perpendicular to the first direction being a second direction; forming a side wall on the side wall of the core layer, wherein the core layer and the side wall positioned on the side wall of the core layer form a pattern structure layer; forming a sacrificial layer crossing the pattern structure layer along a second direction on the substrate, wherein the sacrificial layer at least covers part of the top and part of the side wall of the pattern structure layer; forming a flat layer on the substrate exposed by the sacrificial layer and the pattern structure layer; removing the sacrificial layer, and forming first grooves in the flat layer, wherein the first grooves are positioned on two sides of the graphic structure layer; removing the core layer to enable the side walls to form a second groove in a surrounding mode; and etching the target layer below the first groove and the second groove by taking the flat layer and the side wall as masks to form a target pattern.
Optionally, the graphic structure layer includes a first sidewall along the second direction, and a second sidewall opposite to the first sidewall and parallel to the first sidewall; in the step of forming the sacrificial layer, the sacrificial layer exposes a first side wall and a second side wall of the pattern structure layer; in the step of removing the sacrificial layer, the first grooves on two sides of the graphic structure layer are spaced.
Optionally, the graphic structure layer includes a first sidewall along the second direction, and a second sidewall opposite to the first sidewall and parallel to the first sidewall; in the step of forming the sacrificial layer, the sacrificial layer covers the first side wall of the pattern structure layer and exposes the second side wall; in the step of removing the sacrificial layer, the first grooves on the two sides of the pattern structure layer are communicated at the position of the first side wall.
Optionally, the graphic structure layer includes a first sidewall along the second direction, and a second sidewall opposite to the first sidewall and parallel to the first sidewall; in the step of forming the sacrificial layer, the sacrificial layer covers the top and the side wall of the graphic structure layer; in the step of removing the sacrificial layer, the first grooves located on two sides of the pattern structure layer are communicated at the positions of the first side wall and the second side wall, and the first grooves surround the side walls of the side walls.
Optionally, the step of forming the sacrificial layer includes: forming a sacrificial material layer covering the graphic structure layer on the substrate; and patterning the sacrificial material layer, and reserving a part of the sacrificial material layer which crosses the pattern structure layer to be used as the sacrificial layer.
Optionally, the step of forming the planarization layer includes: forming a flat material layer covering the sacrificial layer and the graphic structure layer on the substrate; and removing part of the thickness of the flat material layer, wherein the rest flat material layer is used as the flat layer.
Optionally, the material of the sacrificial layer is an organic material.
Optionally, the material of the sacrificial layer includes one or more of spin-on carbon, an organic dielectric layer, a bottom anti-reflection coating, a silicon-containing anti-reflection coating, a deep ultraviolet light absorbing oxide layer, a dielectric anti-reflection coating, and an advanced patterning film.
Optionally, the process for removing the sacrificial layer includes one or both of an ashing process and a wet photoresist removal process.
Optionally, the target layer is a dielectric layer; the target graph is an interconnection groove; the method for forming the semiconductor structure further comprises the following steps: after the forming of the interconnection groove, a metal interconnection line is formed in the interconnection groove.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the method for forming a semiconductor structure provided by the embodiment of the invention, a core layer and a side wall are formed, the core layer and the side wall positioned on the side wall of the core layer form a pattern structure layer, then a sacrificial layer crossing the pattern structure layer along a second direction is formed, the sacrificial layer at least covers part of the top and part of the side wall of the pattern structure layer, therefore, part of the sacrificial layer is positioned at two sides of the pattern structure layer, then the sacrificial layer is removed, first grooves are correspondingly formed at two sides of the pattern structure layer, after a second groove is formed by removing the core layer, the first grooves are positioned at two sides of the second groove, and the first grooves and the second grooves are isolated by the side wall; in the embodiment of the invention, when the sacrificial layer is formed, the sacrificial layer has a larger size and is easy to meet the requirements of the photoetching process conditions, moreover, the part of the sacrificial layer outside the overlapping region of the pattern structure layer is used for defining the shape and the size of the first groove, so that the first groove can realize a smaller size by utilizing the superposition of the sacrificial layer pattern and the pattern structure layer pattern, and the space (space) between the first groove and the second groove is defined by the thickness of the side wall, so that the first groove and the second groove can easily meet the designed minimum space, and further, under the condition of not changing the limit of the photoetching process, the target pattern can be favorable for realizing a smaller key size and further compressing the pitch (pitch) between the target patterns so as to meet the requirements of high density and high integration degree of an integrated circuit, and the existing process is slightly changed, The process complexity is low, and the photoetching process friendliness is high.
Drawings
Fig. 1 to 18 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure according to an embodiment of the present invention;
FIGS. 19-22 are top views of steps in another embodiment of a method of forming a semiconductor structure in accordance with the present invention;
fig. 23 to 26 are top views corresponding to steps in yet another embodiment of the method for forming a semiconductor structure of the present invention.
Detailed Description
As can be seen from the background art, it is a challenge to improve the matching between the pattern formed on the wafer and the target pattern while the technology nodes are being scaled down.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate comprising a target layer for forming a target pattern; forming a core layer extending in a first direction on the substrate, a direction perpendicular to the first direction being a second direction; forming a side wall on the side wall of the core layer, wherein the core layer and the side wall positioned on the side wall of the core layer form a pattern structure layer; forming a sacrificial layer crossing the pattern structure layer along a second direction on the substrate, wherein the sacrificial layer at least covers part of the top and part of the side wall of the pattern structure layer; forming a flat layer on the substrate exposed by the sacrificial layer and the pattern structure layer; removing the sacrificial layer, and forming first grooves in the flat layer, wherein the first grooves are positioned on two sides of the graphic structure layer; removing the core layer to enable the side walls to form a second groove in a surrounding mode; and etching the target layer below the first groove and the second groove by taking the flat layer and the side wall as masks to form a target pattern.
In the method for forming a semiconductor structure provided by the embodiment of the invention, a core layer and a side wall are formed, the core layer and the side wall positioned on the side wall of the core layer form a pattern structure layer, then a sacrificial layer crossing the pattern structure layer along a second direction is formed, the sacrificial layer at least covers part of the top and part of the side wall of the pattern structure layer, therefore, part of the sacrificial layer is positioned at two sides of the pattern structure layer, then the sacrificial layer is removed, first grooves are correspondingly formed at two sides of the pattern structure layer, after a second groove is formed by removing the core layer, the first grooves are positioned at two sides of the second groove, and the first grooves and the second grooves are isolated by the side wall; in the embodiment of the invention, when the sacrificial layer is formed, the sacrificial layer has a larger size and is easy to meet the requirements of the photoetching process conditions, moreover, the part of the sacrificial layer outside the overlapping region of the pattern structure layer is used for defining the shape and the size of the first groove, so that the first groove can realize a smaller size by utilizing the superposition of the sacrificial layer pattern and the pattern structure layer pattern, and the space (space) between the first groove and the second groove is defined by the thickness of the side wall, so that the first groove and the second groove can easily meet the designed minimum space, and further, under the condition of not changing the limit of the photoetching process, the target pattern can be favorable for realizing a smaller key size and further compressing the pitch (pitch) between the target patterns so as to meet the requirements of high density and high integration degree of an integrated circuit, and the existing process is slightly changed, The process complexity is low, and the photoetching process friendliness is high.
In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.
Fig. 1 to 18 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 1 and 2, fig. 1 is a top view, and fig. 2 is a cross-sectional view of fig. 1 taken along a y-y cut line, a substrate 200 is provided, including a target layer 100 for forming a target pattern.
The substrate 200 is used to provide a platform for a process. The target layer 100 is a film layer to be patterned to form a target pattern. The target pattern may be a gate structure, an interconnection trench in a back-end process, a fin in a fin field effect transistor (FinFET), a channel stack in a Gate All Around (GAA) transistor or a fork gate transistor (forkheet), a Hard Mask (HM) layer, or the like.
In this embodiment, the target layer 100 is a dielectric layer. And patterning the dielectric layer, forming a plurality of interconnection grooves in the dielectric layer, and forming metal interconnection lines in the interconnection grooves, wherein the dielectric layer is used for realizing the electrical isolation among the metal interconnection lines. Accordingly, in this embodiment, the target pattern is an interconnection groove.
Thus, the Dielectric layer is an Inter Metal Dielectric (IMD) layer. The dielectric layer is made of low-k dielectric material, ultra-low-k dielectric material, silicon oxide, silicon nitride or silicon oxynitride.
A semiconductor device such as a transistor or a capacitor may be formed in the substrate 200, and a functional structure such as a resistance structure or a conductive structure may be formed in the substrate 200. In this embodiment, the base 200 further includes a substrate 110 located at the bottom of the target layer 110. As an example, the substrate 110 is a silicon substrate.
In this embodiment, the substrate 200 further includes a hard mask material layer 115 on the target layer 100. The hard mask material layer 115 is patterned to form a hard mask layer, and then the target layer 100 is patterned by using the hard mask layer as a mask, which is beneficial to improving the process stability of the patterned target layer 100 and the precision of pattern transfer.
The hard mask material layer 115 is selected to have an etch selectivity with respect to the target layer 100. The material of the hard mask material layer 115 includes one or more of titanium nitride, tungsten carbide, silicon oxide, silicon oxycarbide, and silicon oxycarbonitride. As an example, the material of the hard mask material layer 115 is titanium nitride.
In a specific process, according to actual process requirements, a stress buffer layer can be further disposed between the hard mask material layer 115 and the target layer 100, so as to improve adhesion between the hard mask material layer 115 and the target layer 100 and reduce stress between films. In addition, an etching stop layer can be disposed between the hard mask material layer 115 and the stress buffer layer and on the hard mask material layer 115 to define a stop position of a subsequent etching process, which is beneficial to improving the process effect of the patterning target layer 100. The description of the stress buffer layer and the etch stop layer is not repeated herein.
With continued reference to fig. 1 and 2, a core layer 120 is formed on the substrate 200 to extend in a first direction (shown as the X-direction in fig. 1), and a direction perpendicular to the first direction is a second direction (shown as the Y-direction in fig. 1).
The core layer 120 is used to occupy a spatial location for forming a second groove, thereby defining the shape and location of a subsequent second groove. Compared with the method of directly forming the second groove through the etching process, the core layer 120 is formed firstly, and then the core layer 120 is removed to form the second groove, so that the size and the shape of the second groove can be accurately controlled by adjusting the size and the shape of the core layer 120, the forming difficulty of the second groove is reduced, and the pattern precision of the second groove is guaranteed. Subsequently, a side wall is formed on the side wall of the core layer 120, and the core layer 120 also provides a support for forming the side wall.
In this embodiment, the core layer 120 is a material that is easy to be removed, so as to reduce the difficulty of subsequently removing the core layer 120, and the core layer 120 is also a material having an etching selectivity with the substrate 200, so that the substrate 200 (for example, the target layer 100 or the hard mask material layer 115) is not easy to be etched by mistake in the subsequent step of removing the core layer 120.
The core layer 120 is a single-layer or multi-layer structure, and the material of the core layer 120 includes one or more of amorphous silicon, amorphous carbon, amorphous germanium, polycrystalline silicon, silicon oxide, silicon nitride, silicon oxynitride, carbon nitride, silicon carbide, silicon carbonitride, and silicon oxycarbonitride. As an example, the core layer 120 has a single-layer structure, and the material of the core layer 120 is amorphous silicon.
Referring to fig. 3 and 4, fig. 3 is a top view, and fig. 4 is a cross-sectional view taken along the y-y cut line of fig. 3, a side wall 130 is formed on the side wall of the core layer 120, and the core layer 120 and the side wall 130 on the side wall of the core layer 120 form a pattern structure layer 140.
The sidewall spacers 130 are used as masks for subsequent patterning of the target layer 100
Subsequently, a sacrificial layer crossing the pattern structure layer 140 is formed, and the sacrificial layers on the two sides of the pattern structure layer 140 occupy space for forming the first groove, so that the sidewall 130 is further used for realizing isolation between the first groove and the second groove, and in this embodiment, the first groove and the second groove meet a designed minimum interval in a manner of adjusting the thickness of the sidewall 130, and accordingly, the target pattern easily meets the designed minimum interval.
In this embodiment, a core layer 120 is formed first, and then a side wall 130 is formed on the side wall of the core layer 120, where the side wall 130 is an Outer wall (Outer Spacer); after the second grooves are formed by removing the core layer 120, the distance between the adjacent second grooves along the first direction is defined by the core layer 120, and compared with the first step of forming the grooves and then forming the Inner sidewalls (Inner Spacer) on the sidewalls of the grooves, in this embodiment, the distance between the adjacent second grooves along the first direction is not the sum of the distance between the adjacent core layers 120 and twice the thickness of the Inner sidewalls, which is beneficial To realize a smaller line end distance between the adjacent second grooves at the position of the Head (Head To Head).
In this embodiment, the graphic structure layer 140 includes a first sidewall 41 along the second direction, and a second sidewall 42 opposite to the first sidewall 41 and parallel to the first sidewall 41.
The sidewall 130 is made of a material having an etching selectivity with the core layer 120 and the target layer 100, and the material of the sidewall 130 includes one or more of titanium oxide, silicon nitride, silicon carbide, silicon oxycarbide, aluminum oxide, and amorphous silicon.
In this embodiment, the step of forming the sidewall spacer 130 includes: forming a side wall material layer (not shown) conformally covering the top surface and the side walls of the core layer 120 and the top surface of the substrate 200; and removing the side wall material layers on the top surfaces of the core layer 120 and the substrate 200, and remaining the side wall material layers on the side walls of the core layer 120 to be used as the side walls 130.
In the embodiment, the sidewall material layer is formed by adopting an atomic layer deposition process, so that the thickness uniformity of the sidewall material layer is favorably improved, and the thickness of the sidewall material layer is easily and accurately controlled.
In this embodiment, a dry etching process (e.g., an anisotropic dry etching process) is used to remove the spacer material layer on the top surfaces of the core layer 120 and the substrate 200.
Referring to fig. 5 to 7, a sacrificial layer 160 is formed on the substrate 200 to cross the pattern structure layer 140 along a second direction (as shown in a Y direction in fig. 6), wherein the sacrificial layer 160 covers at least a portion of the top and a portion of the sidewalls of the pattern structure layer 140.
The sacrificial layer 160 crosses the pattern structure layer 140 along the second direction, the sacrificial layer 160 covers at least a portion of the top and a portion of the sidewall of the pattern structure layer 140, so that a portion of the sacrificial layer 160 is located on both sides of the pattern structure layer 140, and then the sacrificial layer 160 is removed, thereby forming first grooves on both sides of the pattern structure layer 140. The sacrificial layer 160 located at the sidewall of the pattern structure layer 140 corresponds to a pattern for defining the first groove.
Therefore, in the embodiment, when the sacrificial layer 160 is formed, the sacrificial layer 160 has a larger size, which is easy to meet the requirement of the photolithography process condition, and the portion of the sacrificial layer 160 outside the overlapping region with the pattern structure layer 140 is used to define the shape and size of the first groove, so that the first groove is made to have a smaller size by overlapping the pattern of the sacrificial layer 160 and the pattern structure layer 140, and thus, the target pattern can be made to have a smaller critical size and the pitch (pitch) between the target patterns can be further compressed without changing the limit condition of the photolithography process, so as to meet the requirement of high density and high integration of the integrated circuit, and the change of the existing process is small, the process complexity is low, and the photolithography process friendliness is high.
In addition, in this embodiment, the sacrificial layers 160 on both sides of the pattern structure layer 140 are isolated from the core layer 120 by the sidewall 130, and accordingly, after the sacrificial layers 160 are subsequently removed to form a first groove and the core layer 120 is removed to form a second groove, the first groove and the second groove are isolated by the sidewall 130, and an interval (Space) between the first groove and the second groove is defined by the thickness of the sidewall 130, so that the first groove and the second groove easily satisfy a Design Minimum interval, and further, the Design Minimum interval (Design Minimum Space) between target patterns is satisfied.
In this embodiment, in the step of forming the sacrificial layer 160, the sacrificial layer 160 exposes the first sidewall 41 and the second sidewall 42 of the pattern structure layer 140. Accordingly, in the subsequent step of removing the sacrificial layer 160, the first grooves on the two sides of the pattern structure layer 120 are spaced apart from each other.
As an example, both sides of the sacrificial layer 160 also expose a portion of the top of the pattern structure layer 140, that is, after the sacrificial layer 160 is formed, an end portion of the pattern structure layer 140 protrudes from the sacrificial layer 160 along the first direction.
In other embodiments, the sidewalls of the sacrificial layer along the second direction may be flush with the first and second sidewalls, respectively, and accordingly, when the first grooves are formed by removing the sacrificial layer, the first grooves on both sides of the pattern structure layer are spaced apart from each other.
The sacrificial layer 160 is made of a material having a high etching selectivity with the target layer 100, the hard mask material layer 115, the core layer 120 and the sidewall 130, so that difficulty in subsequently removing the sacrificial layer 160 to form a first groove is reduced, and in the step of removing the sacrificial layer 160, the target layer 100, the hard mask material layer 115, the core layer 120 and the sidewall 130 are less likely to be damaged, which is accordingly beneficial to ensuring the pattern precision of the first groove and the core layer 120, and is further beneficial to accurately controlling the shape and size of the first groove.
In this embodiment, the material of the sacrificial layer 160 is an organic material. The organic material is suitable for a spin coating process, so as to be beneficial to improving the top surface flatness of the sacrificial layer 160, further beneficial to improving the pattern transfer precision when the sacrificial layer 160 is formed, and reducing the process difficulty of forming the sacrificial layer 160, furthermore, the organic material is easy to remove, and the side effect of the process of removing the organic material is small, and beneficial to improving the process compatibility and reducing the process risk.
In this embodiment, the material of the sacrificial layer 160 includes one or more of Spin-On Carbon (SOC), Organic Dielectric Layer (ODL), Bottom Anti-reflective Coating (BARC), Silicon-containing Anti-reflective Coating (Si-ARC), Deep ultraviolet light absorbing Oxide (DUO), Dielectric Anti-reflective Coating (DARC), and Advanced Patterning Film (APF). As an example, the material of the sacrificial layer 160 is spin-on carbon.
In this embodiment, the step of forming the sacrificial layer 160 includes: as shown in fig. 5, fig. 5 is a cross-sectional view based on fig. 4, a sacrificial material layer 150 is formed on the substrate 200 to cover the pattern structure layer 140; as shown in fig. 6 and 7, fig. 6 is a top view, and fig. 7 is a cross-sectional view taken along a y-y cut line in fig. 6, the sacrificial material layer 150 is patterned, and a portion of the sacrificial material layer 150 that spans the patterned structure layer 140 is remained to serve as the sacrificial layer 160.
In this embodiment, the sacrificial material layer 150 is formed by a spin coating process.
In this embodiment, the sacrificial material layer 150 is patterned by a dry etching process (e.g., an anisotropic dry etching process).
Referring to fig. 8 to 10, a planarization layer 180 is formed on the substrate 200 where the sacrificial layer 160 and the pattern structure layer 140 are exposed.
The planarization layer 180 is used as a mask for patterning the target layer 100 together with the sidewall spacers 130.
The planarization layer 180 is made of a material having an etching selectivity with the materials of the core layer 120 and the sacrificial layer 160. In this embodiment, the material of the planarization layer 180 includes silicon oxide, metal oxide (e.g., titanium oxide), polysilicon, and amorphous silicon. As an example, the material of the planarization layer 180 is silicon oxide.
In this embodiment, the planarization layer 180 covers the sidewalls of the pattern structure layer 140 and a portion of the sidewalls of the sacrificial layer 160. As an example, the top surface of the planarization layer 180 is flush with the top surface of the pattern structure layer 140.
In this embodiment, the step of forming the planarization layer 180 includes: as shown in fig. 8, fig. 8 is a cross-sectional view based on fig. 7, a planarization material layer 170 is formed on the substrate 200 to cover the sacrificial layer 160 and the pattern structure layer 140; as shown in fig. 9 and 10, fig. 9 is a top view, and fig. 10 is a cross-sectional view taken along the y-y cut line of fig. 9, a portion of the thickness of the planarization material layer 170 is removed, and the remaining planarization material layer 170 is used as the planarization layer 180.
In this embodiment, the flat material layer 170 is formed by a spin coating process, which is beneficial to improving the flatness and the height uniformity of the top surface of the flat material layer 170.
In this embodiment, a dry etching process (e.g., an anisotropic dry etching process) is used to remove a portion of the thickness of the planarization material layer 170, which is beneficial to accurately control the removal thickness of the planarization material layer 170.
Referring to fig. 11 and 12, fig. 11 is a top view, and fig. 12 is a cross-sectional view taken along a y-y cut line of fig. 11, in which the sacrificial layer 160 is removed, and first grooves 210 are formed in the planarization layer 180, the first grooves 210 being located at both sides of the pattern structure layer 140.
The first groove 210 is used to define a partial pattern of a target pattern.
In this embodiment, the sacrificial layer 160 crosses the pattern structure layer 140 along the second direction, so that a portion of the sacrificial layer 160 is located at two sides of the pattern structure layer 140, the sacrificial layer 160 located at the sidewall of the pattern structure layer 140 is correspondingly used to define a pattern of first grooves, and in the step of removing the sacrificial layer 160, the first grooves 210 are correspondingly formed at two sides of the pattern structure layer 140.
In this embodiment, the sacrificial layer 160 pattern and the pattern structure layer 140 pattern are stacked, so that the first groove 210 is easy to realize a smaller size, and further, under the limit condition that the photolithography process is not changed, the target pattern can be facilitated to realize a smaller critical size and the pitch (pitch) between the target patterns is further compressed, so as to meet the requirements of high density and high integration of an integrated circuit, and the present process has the advantages of small modification, low process complexity, and high photolithography process friendliness.
In this embodiment, the first groove 210 is isolated from the core layer 120 by the sidewall 130, after the core layer 120 is subsequently removed to form a second groove, the first groove and the second groove are isolated by the sidewall 130, and the space (space) between the first groove and the second groove is defined by the thickness of the sidewall 130, so that the first groove 210 and the second groove are easy to satisfy the designed minimum space.
In this embodiment, the first grooves 210 on both sides of the graphic structure layer 140 are spaced apart from each other. As an example, in the first direction, an end of the pattern structure layer 140 protrudes out of the first groove 210.
In other embodiments, the sidewalls of the first grooves along the second direction may be respectively flush with the first and second sidewalls of the graphic structure layer, and accordingly, the first grooves on both sides of the graphic structure layer are also spaced apart from each other.
In this embodiment, the first groove 210 extends along a first direction and is spaced apart from the core layer 120.
In this embodiment, the graphic structure layer 140 is a rectangular structure extending along a first direction, and the positions at two sides of the graphic structure layer 140 refer to: on the first side and the second side of the graphical structure 140 in the second direction.
In this embodiment, in the step of removing the sacrificial layer 140, the sacrificial layer 140 and the core layer 120, the flat layer 180, or the side wall 130 have a higher etching selectivity, and the process of removing the sacrificial layer 140 has a low probability of causing an erroneous etching to the core layer 120, the flat layer 180, or the side wall 130, thereby being beneficial to ensuring the pattern accuracy of the first groove 210 and the core layer 120.
The process of removing the sacrificial layer 140 includes one or both of an ashing (Asher) process and a wet stripping process.
In this embodiment, the process of removing the sacrificial layer 140 includes an ashing process. The ashing process has a high etching selectivity between the sacrificial layer 140 and the core layer 120, the sidewall 130 or the planarization layer 180, and is simple in operation, less in side effects, and easy to remove the sacrificial layer 140.
Referring to fig. 13 and 14, fig. 13 is a top view, and fig. 14 is a cross-sectional view taken along the y-y cut line of fig. 13, in which the core layer 120 is removed, so that the side wall 130 encloses a second groove 220.
The second groove 220 and the first groove 210 together define a pattern of a target pattern.
The first groove 210 is isolated from the core layer 120 by the side wall 130, and therefore, after the core layer 120 is removed, the second groove 220 is isolated from the first groove 210 by the side wall 130, which is beneficial to meeting the design minimum interval between the second groove 220 and the first groove 210.
Moreover, in this embodiment, the side wall 130 is an outer side wall, after the core layer 120 is removed to form the second groove 220, along the first direction, the distance between the ends of the second groove 220 is defined by the core layer 120, and after the target pattern is formed on the target layer 100 below the subsequent patterned second groove 220, the target pattern is also easy to realize a smaller distance at a head-to-head (HTH) position.
In this embodiment, the core layer 120, the planarization layer 180, the hard mask material layer 115, the target layer 100, or the sidewall 130 have a higher etching selectivity, so that in the step of removing the core layer 120 to form the second groove 220, the probability of Double etching (Double Etch) to the first groove 210 can be reduced, the process risk is correspondingly reduced, and the pattern precision of the first groove 210 is ensured.
As an example, in the first direction, an end of the second groove 220 protrudes from the first groove 210.
The process of removing the core layer 120 includes one or both of wet etching and dry etching. As an example, the core layer 120 is removed using a wet etching process. In this embodiment, the etching solution of the wet etching process includes a TMAH solution (tetramethylammonium hydroxide solution), an SC1 solution, or an SC2 solution. Wherein SC1 solution refers to NH4OH and H2O2The SC2 solution refers to HCl and H2O2The mixed solution of (1).
Referring to fig. 15 to 16, fig. 15 is a top view, and fig. 16 is a cross-sectional view taken along a y-y cut line of fig. 15, wherein the target layer 100 under the first recess 210 and the second recess 220 is etched by using the planarization layer 180 and the sidewall spacers 130 as masks, so as to form a target pattern 230.
As can be seen from the foregoing description, in the embodiment, by overlapping the sacrificial layer 160 pattern and the pattern structure layer 140 pattern, the first groove 210 can realize a smaller size, and the minimum design interval between the first groove 210 and the second groove 220 is easily satisfied, so that under the limit condition of not changing the photolithography process, the target pattern 230 can realize a smaller critical size and further compress the pitch (pitch) between the target patterns 230, so as to satisfy the requirements of high density and high integration of the integrated circuit, and the present process has the advantages of small change, low process complexity, and high photolithography process friendliness, and accordingly, the present process is favorable for improving the matching degree between the target pattern 230 and the design pattern and improving the pattern precision of the target pattern 230.
Further, as can be seen from the foregoing description, it is easy to achieve a smaller line end distance between the first grooves 210 along the first direction, and accordingly, it is advantageous to achieve a smaller distance between the target patterns 230 at the head-to-head positions after the target patterns 230 are formed, thereby improving the flexibility and the degree of freedom in the layout design of the target patterns 230.
In this embodiment, the target layer 100 is a dielectric layer, and therefore, the dielectric layer under the first groove 210 and the second groove 220 is etched by using the sidewall 130 and the planarization layer 180 as masks, so as to form the interconnect Trench (Trench) 30. Accordingly, the target pattern 230 is the interconnect trench 30. The interconnect trench 30 is used to provide space for forming metal interconnect lines.
Specifically, in this embodiment, the hard mask material layer 115 under the first groove 210 and the second groove 220 is etched by using the side wall 130 and the planarization layer 180 as masks, so as to form a hard mask layer 190; and patterning the dielectric layer by taking the hard mask layer 190 as a mask to form the interconnection groove 30.
In this embodiment, in the step of etching the target layer 100 under the first groove 210 and the second groove 220, the planarization layer 180 and the sidewall spacers 130 are also consumed by a portion of the thickness.
Referring to fig. 17 and 18 in combination, fig. 17 is a top view, and fig. 18 is a cross-sectional view taken along a y-y cut line of fig. 17, in this embodiment, the method for forming a semiconductor structure further includes: after the formation of the interconnection trenches 30, metal interconnection lines 240 are formed in the interconnection trenches 30.
In this embodiment, the interconnection grooves 30 can achieve a smaller critical dimension, and the Pitch between the interconnection grooves 30 is further compressed, so that it is beneficial to further compress the Pitch (Pitch) of the metal interconnection lines 240 to meet the requirements of high density and high integration of the integrated circuit.
Moreover, the interconnection grooves 30 can achieve a smaller distance at the head-to-head position, the metal interconnection lines 240 can correspondingly achieve a smaller distance at the head-to-head position, which is beneficial to improving the wire connecting capability of the metal interconnection lines 240 at the head-to-head position, and is also beneficial to improving the freedom and flexibility of the layout design of the metal interconnection lines 240, meanwhile, the minimum design interval is easily met between the interconnection grooves 30, the graphic precision of the interconnection grooves 30 is higher, and accordingly, the minimum design interval between the metal interconnection lines 240 is met, and the graphic precision of the metal interconnection lines 240 is improved, so that the performance of the semiconductor structure is improved.
The metal interconnect lines 240 are used to electrically connect the semiconductor structure to external circuitry or other interconnect structures. In this embodiment, the metal interconnection line 240 is made of copper. In other embodiments, the material of the metal interconnection line can also be a conductive material such as cobalt, tungsten, aluminum, and the like.
In this embodiment, in the step of forming the metal interconnection line 240, the planarization layer 180, the sidewall spacer 130 and the hard mask layer 190 are also removed to prepare for the subsequent processes.
Fig. 19 to 22 are top views corresponding to steps in another embodiment of the method for forming a semiconductor structure of the present invention. The same parts of this embodiment as those of the previous embodiments are not described herein again. The present embodiment differs from the previous embodiments in that:
referring to fig. 19, a sacrificial layer 360 is formed on the substrate 300 to cross the pattern structure layer 340 in a second direction (as shown in a Y direction in fig. 19), wherein the sacrificial layer 360 covers at least a portion of a top and a portion of a sidewall of the pattern structure layer 340.
The graphic structure layer 340 includes a first sidewall 341 along the second direction and a second sidewall 342 opposite to the first sidewall 341 and parallel to the first sidewall 341.
In this embodiment, the sacrificial layer 360 covers the first sidewall 341 of the pattern structure layer 340 and exposes the second sidewall 342.
As an example, the sacrificial layer 360 also exposes a portion of the top of the pattern structure layer 340 near the second sidewall 342.
In other embodiments, the sacrificial layer may further cover the top of the pattern structure layer, and accordingly, a sidewall of the sacrificial layer along the second direction opposite to the first sidewall is flush with a second sidewall of the pattern structure layer.
Referring to fig. 20, a planarization layer 380 is formed on the substrate 300 where the sacrificial layer 360 and the pattern structure layer 340 are exposed.
The step of forming the planarization layer 380 is the same as the previous embodiment, and is not repeated herein. For the description of the material of the planarization layer 380, reference may be made to the corresponding description in the foregoing embodiments, and further description is omitted here.
Referring to fig. 21, the sacrificial layer 360 is removed, and first grooves 410 are formed in the planarization layer 380, the first grooves 410 being located at both sides of the pattern structure layer 340.
In this embodiment, in the step of removing the sacrificial layer 360, the first grooves 410 on the two sides of the pattern structure layer 340 are communicated with each other at the position of the first sidewall 341. The first groove 410 correspondingly exposes a sidewall of the first sidewall 341.
Therefore, in this embodiment, the first groove 410 not only extends along the first direction, but also the first groove 410 located outside the first sidewall 341 extends along the second direction, so that the pattern of the first groove 410 is a two-dimensional pattern by using the superposition of the pattern of the sacrificial layer 360 and the pattern of the pattern structure layer 340, which is beneficial to improving the design freedom of the target pattern, and compared with the realization of the two-dimensional pattern by using the pattern of the mask, the superposition of the pattern of the sacrificial layer 360 and the pattern structure layer 340 is beneficial to reducing the process difficulty and increasing the photolithography process window in this embodiment.
In this embodiment, the target layer (not shown) is a dielectric layer, and after the core layer 320 is subsequently removed to form a second groove, the dielectric layer under the first groove 310 and the second groove is etched by using the planarization layer 380 and the sidewall spacers 330 as masks to form an interconnection trench, where the interconnection trench is used to provide a spatial location for forming a metal interconnection line.
Correspondingly, the metal interconnection line corresponding to the position of the first groove 410 extends in the first direction and also extends in the second direction, so that two-dimensional winding can be realized, the graphic design and layout freedom of the metal interconnection line can be improved, and the connection capacity of the metal interconnection line can be improved.
Referring to fig. 22, the core layer 320 is removed, so that the side walls 330 enclose a second groove 420.
For the related description of the second groove 420 and the removal of the core layer 320, reference may be made to the corresponding description in the foregoing embodiments, and details are not repeated here.
For a detailed description of the method for forming the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.
Fig. 23 to 26 are top views corresponding to steps in yet another embodiment of the method for forming a semiconductor structure of the present invention. The same parts of this embodiment as those of the previous embodiments are not described herein again. The present embodiment differs from the previous embodiments in that:
referring to fig. 23, a sacrificial layer 560 crossing the pattern structure layer 540 in the second direction is formed on the substrate 500, and the sacrificial layer 560 covers at least a portion of the top and a portion of the sidewall of the pattern structure layer 540.
The pattern structure layer 540 includes a first sidewall 541 along the second direction, and a second sidewall 542 opposite to the first sidewall 541 and parallel to the first sidewall 541.
In this embodiment, the sacrificial layer 560 covers the top and the sidewalls of the pattern structure layer 540. Accordingly, the first sidewall 541 and the second sidewall 542 of the pattern structure layer 540 are covered by the sacrificial layer 560.
Referring to fig. 24, a planarization layer 580 is formed on the substrate 500 where the sacrificial layer 560 and the pattern structure layer 540 are exposed.
For a detailed description of the process steps for forming the planarization layer 580 and the material of the planarization layer 580, please refer to the corresponding description in the previous embodiments, which will not be repeated herein.
Referring to fig. 25, the sacrificial layer 560 is removed, and a first groove 610 is formed in the planarization layer 580, the first groove 610 being located at both sides of the pattern structure layer 540.
In this embodiment, in the step of removing the sacrificial layer 560, the first grooves 610 on the two sides of the pattern structure layer 540 are communicated with each other at the positions of the first sidewall 541 and the second sidewall 542. The first groove 610 correspondingly surrounds the sidewall 530, and the first groove 610 is an annular groove.
In this embodiment, the first groove 610 not only extends along the first direction, but also extends along the second direction at the outer sides of the first side wall 541 and the second side wall 542, so that the superposition of the pattern of the sacrificial layer 560 and the pattern structure layer 540 is utilized to make the pattern of the first groove 60 a two-dimensional pattern, which is beneficial to improving the design freedom of the target pattern, and compared with the realization of the two-dimensional pattern by utilizing the pattern of the photomask, the superposition of the pattern of the sacrificial layer 560 and the pattern structure layer 540 is utilized to realize the two-dimensional pattern in this embodiment, which is beneficial to reducing the process difficulty and increasing the photolithography process window.
In this embodiment, the target layer (not shown) is a dielectric layer, after the core layer 520 is subsequently removed to form a second groove, the planar layer 580 and the sidewall spacers 530 are used as masks to etch the target layer under the first groove 610 and the second groove, so as to form an interconnection trench, and the interconnection trench is used for providing a spatial position for forming a metal interconnection line.
Correspondingly, the metal interconnection line corresponding to the first groove 610 extends in the first direction and also extends in the second direction, so that two-dimensional winding can be realized, the graphic design and layout freedom of the metal interconnection line can be improved, and the connection capacity of the metal interconnection line can be improved.
Referring to fig. 26, the core layer 520 is removed, and the sidewall 530 encloses a second groove 620.
The first recess 610 correspondingly surrounds the second recess 620, and the first recess 610 and the second recess 620 are isolated by the sidewall 530.
For a detailed description of the method for forming the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (10)

1. A method of forming a semiconductor structure, comprising:
providing a substrate comprising a target layer for forming a target pattern;
forming a core layer extending in a first direction on the substrate, a direction perpendicular to the first direction being a second direction;
forming a side wall on the side wall of the core layer, wherein the core layer and the side wall positioned on the side wall of the core layer form a pattern structure layer;
forming a sacrificial layer crossing the pattern structure layer along a second direction on the substrate, wherein the sacrificial layer at least covers part of the top and part of the side wall of the pattern structure layer;
forming a flat layer on the substrate exposed by the sacrificial layer and the pattern structure layer;
removing the sacrificial layer, and forming first grooves in the flat layer, wherein the first grooves are positioned on two sides of the graphic structure layer;
removing the core layer to enable the side walls to form a second groove in a surrounding mode;
and etching the target layer below the first groove and the second groove by taking the flat layer and the side wall as masks to form a target pattern.
2. The method of claim 1, wherein the pattern structure layer comprises a first sidewall along the second direction and a second sidewall opposite to and parallel to the first sidewall;
in the step of forming the sacrificial layer, the sacrificial layer exposes a first side wall and a second side wall of the pattern structure layer;
in the step of removing the sacrificial layer, the first grooves on two sides of the graphic structure layer are spaced.
3. The method of claim 1, wherein the pattern structure layer comprises a first sidewall along the second direction and a second sidewall opposite to and parallel to the first sidewall;
in the step of forming the sacrificial layer, the sacrificial layer covers the first side wall of the pattern structure layer and exposes the second side wall;
in the step of removing the sacrificial layer, the first grooves on the two sides of the pattern structure layer are communicated at the position of the first side wall.
4. The method of claim 1, wherein the pattern structure layer comprises a first sidewall along the second direction and a second sidewall opposite to and parallel to the first sidewall; in the step of forming the sacrificial layer, the sacrificial layer covers the top and the side wall of the graphic structure layer;
in the step of removing the sacrificial layer, the first grooves located on two sides of the pattern structure layer are communicated at the positions of the first side wall and the second side wall, and the first grooves surround the side walls of the side walls.
5. The method of forming a semiconductor structure of claim 1, wherein the step of forming the sacrificial layer comprises: forming a sacrificial material layer covering the graphic structure layer on the substrate;
and patterning the sacrificial material layer, and reserving a part of the sacrificial material layer which crosses the pattern structure layer to be used as the sacrificial layer.
6. The method of forming a semiconductor structure of claim 1, wherein forming the planarization layer comprises: forming a flat material layer covering the sacrificial layer and the graphic structure layer on the substrate;
and removing part of the thickness of the flat material layer, wherein the rest flat material layer is used as the flat layer.
7. The method of forming a semiconductor structure of claim 1, wherein a material of the sacrificial layer is an organic material.
8. The method of claim 7, wherein the sacrificial layer comprises one or more of spin-on carbon, an organic dielectric layer, a bottom anti-reflective coating, a silicon-containing anti-reflective layer, a deep ultraviolet light absorbing oxide layer, a dielectric anti-reflective coating, and an advanced patterning film.
9. The method of claim 1, wherein the process of removing the sacrificial layer comprises one or both of an ashing process and a wet stripping process.
10. The method of forming a semiconductor structure of claim 1, wherein the target layer is a dielectric layer; the target graph is an interconnection groove;
the method for forming the semiconductor structure further comprises the following steps: after the forming of the interconnection groove, a metal interconnection line is formed in the interconnection groove.
CN202011137111.9A 2020-10-22 2020-10-22 Method for forming semiconductor structure Pending CN114388431A (en)

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