CN114388414A - Carrier and method for bearing semiconductor assembly - Google Patents
Carrier and method for bearing semiconductor assembly Download PDFInfo
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- CN114388414A CN114388414A CN202111459655.1A CN202111459655A CN114388414A CN 114388414 A CN114388414 A CN 114388414A CN 202111459655 A CN202111459655 A CN 202111459655A CN 114388414 A CN114388414 A CN 114388414A
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- carrier
- semiconductor
- accommodating part
- carrying
- loading
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/677—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations
- H01L21/67763—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for conveying, e.g. between different workstations the wafers being stored in a carrier, involving loading and unloading
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
The invention relates to a carrier and a method for bearing a semiconductor component. The carrier for carrying the semiconductor component comprises a carrier body. The carrier includes: the first containing part of one side of carrier and the second containing part that is located the opposite side of carrier, first containing part and second containing part set up relatively.
Description
Technical Field
The present invention relates to the field of semiconductor technology, and more particularly, to a carrier and a method for supporting a semiconductor device.
Background
In a semiconductor package manufacturing process, as shown in fig. 1a, a die 30 is first formed on a carrier 10; then, as shown in fig. 1b, a molding process is performed on the carrier 10 to form a molding compound 20 encapsulating the plurality of dies 30, and the carrier 10 is removed. Due to the limitations of the machine used for the molding process, the dimension S1 of the carrier 10 is limited to 625mm × 615 mm. But the dimension S2 of the mold compound 20 after removal of the carrier plate 10 is 600mm x 600 mm.
The current method is to transport the two sizes of modules in two separate cases. As shown in fig. 1c, the supporting members 70 in the case correspond to only a single size, and the supporting surfaces with the grooves 40 are all located on the same side, and the grooves 40 on the supporting surfaces are used for placing the components 60. Such a design results in a box body that cannot be shared in practicality, which consumes cost and occupies space.
Disclosure of Invention
In view of the above problems in the related art, the present invention provides a carrier and a method for carrying a semiconductor device.
An embodiment of the present invention provides a carrier for carrying a semiconductor device, including a carrier, the carrier including: the first accommodating part is positioned at one side of the bearing body; and the second accommodating part is positioned on the other side of the carrier body, and the size of the first accommodating part is larger than that of the second accommodating part.
In some embodiments, the first and second receptacles are oppositely disposed.
In some embodiments, the first and second receptacles are each a groove in the carrier.
In some embodiments, the first receiving portion is used for loading a first semiconductor assembly, the second receiving portion is used for loading a second semiconductor assembly, and the size of the first semiconductor assembly is larger than that of the second semiconductor assembly.
In some embodiments, further comprising: a cassette, wherein both ends of the carrier are connected to opposite sidewalls of the cassette, respectively.
In some embodiments, the number of the carriers is multiple, and the multiple carriers are arranged in the loading box in parallel.
Embodiments of the present invention further provide a method for forming a carrier for carrying a semiconductor device, including: providing a carrier body, wherein the carrier body comprises a first accommodating part and a second accommodating part which are positioned at the opposite sides of the carrier body, and the sizes of the first accommodating part and the second accommodating part are different; loading a first semiconductor component corresponding to the size of the first accommodating part in the first accommodating part, and carrying out a first process on the first semiconductor component to form a second semiconductor component; turning over the carrier; and loading a second semiconductor assembly with the size corresponding to that of the second accommodating part in the second accommodating part.
In some embodiments, the first semiconductor component has a size larger than a size of the second semiconductor component.
In some embodiments, a first semiconductor assembly includes a carrier board and a die on the carrier board; the first process comprises the following steps: a molding process is performed to form a molding material on the carrier that encapsulates the die.
In some embodiments, the first process further comprises: and removing the carrier plate to form a second semiconductor component.
In some embodiments, the carrier is disposed within a cassette, and the carrier is flipped by flipping the cassette.
Drawings
Various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or reduced for clarity of discussion.
Fig. 1a to 1c are schematic diagrams of a current process for forming a semiconductor package and a cassette for loading components.
Fig. 2 is a schematic view of a carrier according to an embodiment of the invention.
Fig. 3a and 3b are schematic views of a carrier carrying components of different sizes according to an embodiment of the present invention.
Fig. 4a and 4b are schematic views of a carrier carrying components of different sizes according to another embodiment of the present invention.
Fig. 5a to 5h are schematic diagrams of stages in a method of forming a semiconductor device according to a carrier for carrying semiconductor components to which embodiments of the invention are applied.
DETAILED DESCRIPTION OF EMBODIMENT (S) OF INVENTION
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are in direct contact, as well as embodiments in which additional features are formed between the first and second features such that the first and second features may not be in direct contact. Moreover, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Embodiments of the present invention provide a carrier for carrying a semiconductor device. Fig. 2 is a schematic view of a carrier for carrying a semiconductor device according to an embodiment of the invention. As shown in fig. 2, the carrier 1000 includes a carrier 200. The carrier 200 has a first side 201 and a second side 202 opposite the first side 201. The carrier 200 includes a first receiving portion 210 at the first side 201, and the carrier 200 further includes a second receiving portion 220 at the second side 202. In some embodiments, the first and second receiving parts 210 and 220 may be different in size. In the embodiment shown in fig. 2, the size of the first receiving portion 210 is larger than that of the second receiving portion 220.
In the carrier 1000 of the present invention, the first accommodating portion 210 and the second accommodating portion 220 are respectively disposed on two opposite sides of the carrier 200, so that the first accommodating portion 210 and the second accommodating portion 220 can be designed in different sizes, and thus, the requirements of two different sizes can be satisfied simultaneously for carrying semiconductor devices in different sizes. The semiconductor assemblies with different sizes can share the carrier provided by the invention, so that the production cost is saved.
In some embodiments, the number of carriers 200 is multiple. A plurality of carriers 200 may be arranged in a stack spaced apart from each other in a vertical direction. Each carrier 200 may have the same structure and configuration.
The first receiving portion 210 and the second receiving portion 220 are oppositely disposed on the carrier 200. In other words, the second receiving portion 220 having a smaller size is located below the area defined by the first receiving portion 210. The center of the first receiving part 210 may be aligned with the center of the second receiving part 220.
In some embodiments, the first and second receiving portions 210 and 220 are grooves in the carrier 200. In particular, the carrier 200 may include two support members 230 disposed opposite each other. The two support members 230 may have a space therebetween. The two support members 230 may be located at the same height level. Adjacent partial surfaces of the first sides 201 of the two support members 230 may be recessed by the same depth to form the first receiving part 210. Adjacent partial surfaces of the second sides 202 of the two support members 230 may be recessed by the same depth to form the second receiving part 220.
Fig. 3a shows a schematic view of a first receiving portion to which the carrier of fig. 2 is applied. Fig. 3b shows a schematic view of a second receiving portion to which the carrier of fig. 2 is applied. As shown in fig. 3a, the large-sized first receiving part 210 is used to load the large-sized first semiconductor assembly 310. When the first semiconductor device 310 is loaded, the first side 201 of the carrier 200 and the first receiving portion 210 face upward. The second side 202 of the carrier 200 and the second receiving portion 220 face downward and are not used to carry any components. The first semiconductor assembly 310 is supported by the two support members 230 and is located in the first receiving portion 210. Since the opposite two support members 230 have a space therebetween, the support members 230 support the edge of the first semiconductor assembly 310. A plurality of carriers 200 may simultaneously load a plurality of first semiconductor elements 310.
As shown in fig. 3b, the small-sized second receiving part 220 is used for loading the small-sized second semiconductor device 320. When the second semiconductor device 320 is loaded, the second side 202 of the carrier 200 and the second receiving portion 220 face upward. The first side 201 of the carrier 200 and the first receiving portion 210 face downward without carrying any components. The second semiconductor assembly 320 is supported by the two support members 230 and is located in the second receiving portion 220. A plurality of carriers 200 may simultaneously load a plurality of second semiconductor devices 320.
The size of the first semiconductor element 310 is larger than the size of the second semiconductor element 320. The sizes of the first and second receiving parts 210 and 220 may be configured to correspond to the sizes of the first and second semiconductor assemblies 310 and 320, respectively.
In some embodiments, the first semiconductor device 310 may be a carrier after a molding process in a semiconductor package manufacturing process. The second semiconductor element 320 may be a molding compound after the carrier is removed during the semiconductor package manufacturing process. In some embodiments, the first semiconductor assembly 310 may have a size of 625mm × 615mm, and the second semiconductor assembly 320 may have a size of 600mm × 600 mm. In other embodiments, the first container 210 and the second container 220 having different sizes may be used to load any other type of semiconductor assembly. Also, the sizes of the first and second receiving parts 210 and 220 may be appropriately configured to load two semiconductor modules of any different sizes, respectively.
As shown in fig. 4a and 4b, in some embodiments, the carrier 1000 may further include a stowage box 500. The two supporting members 230 of each carrier 200 are respectively attached to the inner walls of the opposite sides of the loading cassette 500. A plurality of carriers 200 may be stacked in a vertically spaced relationship from each other so that a plurality of semiconductor modules may be loaded simultaneously. In use, the first semiconductor device 310 or the second semiconductor device 320 may be loaded by turning the loading cassette 500 to turn one of the first receiving portion 210 or the second receiving portion 220 upward to switch the plurality of carriers 200 accordingly.
In addition, the loading cassette 500 is provided with a first recognition mark 410. The loading cassette 500 is further provided with a second recognition mark 420. The first and second identifiers 410 and 420 are located on opposite side exterior walls of the cassette 500. As shown in fig. 4a, when the first accommodating portion 210 faces upward, the first identification mark 410 is located above the first accommodating portion 210. The first recognition mark 410 can be used to recognize whether the first receiving portion 210 faces upward. As shown in fig. 4b, when the second accommodating portion 220 faces upward, the second identification mark 420 is located above the second accommodating portion 220. The second recognition mark 420 may be used to recognize whether the second receiving portion 220 faces upward. For example, before loading the first semiconductor device 310, it may be first identified whether the first recognition mark 410 is facing upward, and if so, the first receiving portion 210 is facing upward and the first semiconductor device 310 may be loaded; if the first identification mark 410 is not facing upward, the loading cassette 500 is flipped over such that the first receiving portion 210 faces upward, and the first semiconductor device 310 is loaded. Similarly, the second signature 420 may be identified prior to loading the second semiconductor device 320. Therefore, by providing the first recognition mark 410 and the second recognition mark 420, the large-sized first semiconductor device 310 can be prevented from being misplaced to the small-sized second receiving portion 220 side, and the first semiconductor device 310 can be prevented from being misplaced to hit the top sharp corner of the second receiving portion 220.
Fig. 5a to 5h are schematic diagrams illustrating various stages of a method for forming a semiconductor package according to a carrier to which an embodiment of the invention is applied.
As shown in fig. 5a, a carrier 510 is provided, wherein an adhesive layer 520 is disposed on an upper surface of the carrier 510. In some embodiments, the glue layer 520 may be an adhesive material. As shown in fig. 5b, a die 530 is disposed on the glue layer 520. The glue layer 520 attaches the die 530 and the carrier 510 together and the resulting structure may be referred to as a first semiconductor assembly 310.
A plurality of first semiconductor assemblies 310 may then be loaded onto the carrier 1000, for example, onto the first receiving portion 210 with the larger size of the carrier 200, and the carrier 200 may be disposed in the cassette 500 as described above. (such as shown in fig. 2). The carrier 1000 may be used to transport a plurality of first semiconductor devices 310 for a next process. In some embodiments, before the first semiconductor device 310 is loaded to the carrier 1000, the first identification mark 410 above the first container 210 is identified, and when the first identification mark 410 is identified and the first container 210 is determined to be facing upwards, the first semiconductor device 310 is loaded.
After loading a plurality of first semiconductor elements 310 onto the carrier 1000, one or more first processes may be performed to form second semiconductor elements having different dimensions than the first semiconductor elements 310. In some embodiments, the first process includes a thermal treatment process, a molding process, and a subsequent process of removing the carrier. As shown in fig. 5c, a first thermal treatment process 532 is performed on the plurality of first semiconductor elements 310. The first thermal process 532 can enhance the bonding strength of the adhesive layer 520 to the die 530 and the carrier 510.
As shown in fig. 5d, a molding compound 540 encapsulating the die 530 is formed on the carrier 510 using a molding process. The sidewalls of the mold compound 540 may be aligned with the sidewalls of the carrier plate 510. As shown in fig. 5e, the carrier plate 510 is removed. As shown in fig. 5f, the glue layer 520 is removed.
As shown in fig. 5g, a backside cap 550 may be attached, for example by lamination, to the bottom surfaces of mold compound 540 and die 530, resulting in a structure referred to as a second semiconductor assembly 320. In the process shown in fig. 5b to 5g, the carrier 1000 provided by the present invention may be utilized to transport the first semiconductor element 310, and then the carrier 1000 is removed.
A plurality of second semiconductor elements 320 may then be loaded onto the carrier 1000, for example, into the smaller second receiving portion 210, for subsequent processing. According to an embodiment of the present invention, after a plurality of first semiconductor devices 310 having a larger size are loaded using the carrier 1000, the cassette 500 may be flipped for loading second semiconductor devices 320 having a smaller size. Before the second semiconductor device 320 is loaded on the carrier 200, the second identification mark 420 above the second accommodating portion 220 can be identified, and when the second accommodating portion 220 is determined to be upward, the second semiconductor device 320 is loaded. The carrier 1000 may be used to transport a plurality of second semiconductor devices 320 for subsequent processing.
As shown in fig. 5h, a second thermal treatment process 534 is performed on the second semiconductor element 320, and the second thermal treatment process 534 may cure the backside cap layer 550. The second semiconductor device 320 is then removed from the carrier 1000 to form a semiconductor package using the second semiconductor device 320. It should be understood that the above processes of carrying the first semiconductor element 310 with the carrier 1000 to form the second semiconductor element 320 are only examples. The carrier 1000 may also be used in any other process requiring the carrying of components of different sizes.
In the embodiment of the invention, the first receiving portion 210 and the second receiving portion 220 with different sizes are disposed on two opposite sides of the carrier 200, and are used for loading the first semiconductor device 310 and the second semiconductor device 320 with different sizes, and loading the corresponding first semiconductor device 310 or second semiconductor device 320 to the corresponding first receiving portion 210 or second receiving portion 220 by identifying the first identification mark 410 above the first receiving portion 210 or the second identification mark 420 above the second receiving portion 220, and performing the corresponding process operation on the semiconductor device. The first receiving portion 210 and the second receiving portion 220 can be switched by turning the carrier 200. Compared with the conventional carrier which is only provided with one loading size, the first accommodating part 210 and the second accommodating part 220 which are different in size are arranged on the two opposite sides of the same carrier 200, so that the sharing of the carrier is realized, the production cost is reduced, and the occupied space of the equipment is reduced.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure.
Claims (11)
1. A carrier for carrying a semiconductor assembly, comprising a carrier body, the carrier body comprising:
the first accommodating part is positioned on one side of the carrier;
the second accommodating part is positioned at the other side of the carrier body;
the size of the first receiving portion is larger than that of the second receiving portion.
2. The carrier for carrying semiconductor components as recited in claim 1,
the first accommodating portion and the second accommodating portion are arranged oppositely.
3. The carrier for carrying semiconductor components as recited in claim 1,
the first accommodating part and the second accommodating part are both grooves in the carrier body.
4. The carrier for carrying semiconductor components as recited in claim 1,
the first accommodating part is used for loading a first semiconductor assembly, the second accommodating part is used for loading a second semiconductor assembly, and the size of the first semiconductor assembly is larger than that of the second semiconductor assembly.
5. The carrier for carrying semiconductor components according to claim 1, further comprising:
a cassette, wherein the carriers are connected to opposing inner side walls of the cassette.
6. The carrier for carrying semiconductor components as recited in claim 1,
the number of the bearing bodies is multiple, and the bearing bodies are arranged in the loading box at intervals in a stacked mode.
7. A method of forming a semiconductor package, comprising:
providing a carrier body, wherein the carrier body comprises a first accommodating part and a second accommodating part which are positioned at the opposite sides of the carrier body, and the sizes of the first accommodating part and the second accommodating part are different;
loading a first semiconductor assembly corresponding to a size of the first receiving part in the first receiving part,
carrying out a first process on the first semiconductor component to form a second semiconductor component;
overturning the carrier;
and loading a second semiconductor assembly corresponding to the size of the second accommodating part in the second accommodating part.
8. The method of forming a semiconductor package according to claim 7, wherein the first semiconductor component has a size larger than a size of the second semiconductor component.
9. The method of forming a semiconductor package according to claim 8,
the first semiconductor assembly comprises a carrier plate and a tube core positioned on the carrier plate;
the first process comprises the following steps: and performing a molding process to form a molding material on the carrier plate for encapsulating the die.
10. The method of forming a semiconductor package according to claim 9,
the first process further includes: and removing the carrier plate to form the second semiconductor assembly.
11. The method of forming a semiconductor package according to claim 7,
the carrier is arranged in a loading box, and the carrier is turned over by turning over the loading box.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111459655.1A CN114388414A (en) | 2021-12-02 | 2021-12-02 | Carrier and method for bearing semiconductor assembly |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111459655.1A CN114388414A (en) | 2021-12-02 | 2021-12-02 | Carrier and method for bearing semiconductor assembly |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114388414A true CN114388414A (en) | 2022-04-22 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111459655.1A Pending CN114388414A (en) | 2021-12-02 | 2021-12-02 | Carrier and method for bearing semiconductor assembly |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114388414A (en) |
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2021
- 2021-12-02 CN CN202111459655.1A patent/CN114388414A/en active Pending
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