CN114388016A

CN114388016A - Pulse signal generating circuit and memory

Info

Publication number: CN114388016A
Application number: CN202111492389.2A
Authority: CN
Inventors: 沈一鹤; 黄秋钰; 孙英
Original assignee: China Flash Co Ltd
Current assignee: China Flash Co Ltd
Priority date: 2021-12-08
Filing date: 2021-12-08
Publication date: 2022-04-22
Anticipated expiration: 2041-12-08

Abstract

The invention provides a pulse signal generating circuit and a memory, comprising: the source electrode of the first PMOS tube is connected with power supply voltage, the grid electrode of the first PMOS tube is connected with a counter signal of a clock signal, and the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube; the grid electrode of the first NMOS tube is connected with the inverse signal of the first reset signal, and the source electrode of the first NMOS tube is grounded; the input end of the latch unit is connected with the drain electrode of the first PMOS tube, the output end of the latch unit triggers a signal, and the signal of the drain electrode of the first PMOS tube is latched when the clock signal is at a high level; the first pulse signal generation module sets the first reset signal to be high level when the trigger signal is low level, slowly discharges the first reset signal when the trigger signal is high level, and obtains the first pulse signal based on the AND operation of the first reset signal and the first reset signal. The pulse signal of the invention is not influenced by the external clock frequency, has high stability and can ensure that NOR FLASH data reading work in a wider frequency range.

Description

Pulse signal generating circuit and memory

Technical Field

The present invention relates to the field of semiconductor memories, and more particularly, to a pulse signal generating circuit and a memory.

Background

In the current era, along with the development of science and technology, the application of electronic products is more and more extensive. Due to the fast data reading, NOR false has been widely used in various electronic products, such as cameras, routers, bluetooth headsets, etc. For NOR FLASH, improving the stability of data reading has always been the direction of improvement in NOR FLASH optimization.

Standalone NOR FLASH products mostly apply the SPI interface protocol, where one line is the clock signal needed for input data reading. For the purpose of wider application of stand-alone memory products, the input clock frequency has a wide range. The conventional sense amplifier needs to generate corresponding pulses through an external clock to control the processes of precharge, discharge and data reading of the sense amplifier. Clocks with different frequencies may have certain influence on the use of an internal sense amplifier, so that the clamping voltage of the internal sense amplifier is not stable enough, is higher or lower, and errors are easy to occur in reading data.

Therefore, how to provide a stable pulse control signal for the sense amplifier, which is not affected by the external clock frequency, and which improves the stability of data reading has become one of the problems to be solved by those skilled in the art.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a pulse signal generating circuit and a memory, which are used to solve the problems of the prior art, such as unstable pulse control signal, susceptibility to external clock frequency, and poor data reading stability.

To achieve the above and other related objects, the present invention provides a pulse signal generating circuit for controlling a sense amplifier, the pulse signal generating circuit comprising at least:

the trigger signal generating module and the first pulse signal generating module are connected to the output end of the trigger signal generating module;

the trigger signal generation module comprises a first PMOS (P-channel metal oxide semiconductor) tube, a first NMOS (N-channel metal oxide semiconductor) tube and a latch unit, wherein the source electrode of the first PMOS tube is connected with power supply voltage, the grid electrode of the first PMOS tube is connected with a counter signal of a clock signal, and the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube; the grid electrode of the first NMOS tube is connected with the inverse signal of the first reset signal, and the source electrode of the first NMOS tube is grounded; the input end of the latch unit is connected with the drain electrodes of the first PMOS tube and the first NMOS tube, the output end of the latch unit triggers signals, and when the clock signal is at a high level, the latch unit latches the signals of the drain electrodes of the first PMOS tube and the first NMOS tube;

the first pulse signal generation module receives the trigger signal, sets the first reset signal to be a high level when the trigger signal is at a low level, slowly discharges the first reset signal when the trigger signal is at a high level, and obtains a first pulse signal based on an and operation of the trigger signal and the first reset signal.

Optionally, the latch module includes a first inverter, a second inverter, a third inverter, and a first switch, and an input end of the first inverter is connected to the drains of the first PMOS transistor and the first NMOS transistor; the input end of the second inverter is connected with the output end of the first inverter, and the output end of the second inverter is connected with the input end of the first inverter through the first switch; and the input end of the third phase inverter is connected with the output end of the first phase inverter and the input end of the second phase inverter, and the trigger signal is output.

Optionally, the first pulse signal generating module includes a second PMOS transistor, a second NMOS transistor, a first resistor, a first capacitor, and a first logic unit; the source electrode of the second PMOS tube is connected with the power supply voltage, the grid electrode of the second PMOS tube is connected with the trigger signal, and the drain electrode of the second PMOS tube is connected with the drain electrode of the second NMOS tube through the first resistor; the grid electrode of the second NMOS tube is connected with the trigger signal, and the source electrode of the second NMOS tube is grounded; the upper polar plate of the first capacitor is connected with the drain electrode of the second PMOS tube, and the lower polar plate is grounded; the first input end of the first AND logic unit is connected with the trigger signal, and the second input end of the first AND logic unit is connected with the upper polar plate of the first capacitor and outputs the first pulse signal.

More optionally, the first pulse signal is a discharge control signal.

More optionally, the pulse generating circuit further includes a second pulse signal generating module, where the second pulse signal generating module receives an inverse signal of the first pulse signal, generates a second reset signal at a high level when the inverse signal of the first pulse signal is at a low level, slowly discharges the second reset signal when the inverse signal of the first pulse signal is at a high level, and obtains the second pulse signal based on an and operation of the inverse signal of the first pulse signal and the second reset signal.

More optionally, the second pulse signal generating module includes a third PMOS transistor, a third NMOS transistor, a second resistor, a second capacitor, and a second and logic unit; the source electrode of the third PMOS tube is connected with the power supply voltage, the grid electrode of the third PMOS tube is connected with the inverse signal of the first pulse signal, and the drain electrode of the third PMOS tube is connected with the drain electrode of the third NMOS tube through the second resistor; the grid electrode of the third NMOS tube is connected with the inverse signal of the first pulse signal, and the source electrode of the third NMOS tube is grounded; the upper polar plate of the second capacitor is connected with the drain electrode of the third PMOS tube, and the lower polar plate is grounded; and the first input end of the second AND logic unit is connected with the inverse signal of the first pulse signal, and the second input end of the second AND logic unit is connected with the upper polar plate of the second capacitor to output the second pulse signal.

More optionally, the second pulse signal is a precharge control signal.

More optionally, the pulse generating circuit further includes a third pulse signal generating module, where the third pulse signal generating module receives the inverted signal of the second pulse signal, generates a third reset signal at a high level when the inverted signal of the second pulse signal is at a low level, slowly discharges the third reset signal when the inverted signal of the second pulse signal is at a high level, and obtains the third pulse signal based on an and operation of the inverted signal of the second pulse signal and the third reset signal.

More optionally, the third pulse signal generating module includes a fourth PMOS transistor, a fourth NMOS transistor, a third resistor, a third capacitor, and a third and logic unit; the source electrode of the fourth PMOS tube is connected with the power supply voltage, the grid electrode of the fourth PMOS tube is connected with the inverse signal of the second pulse signal, and the drain electrode of the fourth PMOS tube is connected with the drain electrode of the fourth NMOS tube through the third resistor; the grid electrode of the fourth NMOS tube is connected with the inverse signal of the second pulse signal, and the source electrode of the fourth NMOS tube is grounded; the upper polar plate of the third capacitor is connected with the drain electrode of the fourth PMOS tube, and the lower polar plate is grounded; and the first input end of the third AND logic unit is connected with the inverted signal of the second pulse signal, and the second input end of the third AND logic unit is connected with the upper polar plate of the third capacitor to output the third pulse signal.

More optionally, the third pulse signal is a sense amplifier enable signal.

To achieve the above and other related objects, the present invention provides a memory, comprising at least: NOR FLASH memory array, sensitive amplifier and the above-mentioned pulse generating circuit;

the NOR FLASH memory array is used for storing data;

the sensitive amplifier is connected with the output end of the NOR FLASH storage array and is used for reading out the output signal of the NOR FLASH storage array;

the pulse generating circuit generates a pulse signal for controlling the sense amplifier.

As described above, the pulse signal generating circuit and the memory according to the present invention have the following advantageous effects:

the pulse signal generating circuit and the memory of the invention generate the pulse signal which is not influenced by the external clock frequency, solve the stability problem of the traditional sensitive amplifier which is influenced by the external clock, and can lead the NOR FLASH data to be read and operated in a wider frequency range.

Drawings

Fig. 1 is a schematic structural diagram of a trigger signal generating module according to the present invention.

Fig. 2 is a schematic structural diagram of a first pulse signal generating module according to the present invention.

Fig. 3 is a schematic structural diagram of a second pulse signal generating module according to the present invention.

Fig. 4 is a schematic structural diagram of a third pulse signal generating module according to the present invention.

Fig. 5 is a schematic waveform diagram of the first pulse signal, the second pulse signal, the third pulse signal and the clock signal according to the present invention.

FIG. 6 is a schematic diagram of a memory according to the present invention.

Description of the element reference numerals

1 trigger signal generation module

11 latch module

111 first inverter

112 second inverter

113 third inverter

12 fourth inverter

13 fifth inverter

2 first pulse signal generating module

21 first AND logic cell

3 second pulse signal generating module

31 second AND logic cell

32 sixth inverter

4 third pulse signal generating module

41 third AND logic Unit

42 seventh inverter

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

Please refer to fig. 1 to 6. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.

Example one

As shown in fig. 1 to 5, the present embodiment provides a pulse signal generating circuit for providing a control signal to a sense amplifier, the pulse signal generating circuit including:

a trigger signal generating module 1 and a first pulse signal generating module 2.

As shown in fig. 1, the TRIGGER signal generating module 1 generates a TRIGGER signal TRIGGER _ OUT based on the clock signal CLK and the first reset signal V1 DB.

Specifically, the trigger signal generating module 1 includes a first PMOS transistor PM1, a first NMOS transistor NM1, and a latch unit 11. The source of the first PMOS transistor PM1 is connected to a power supply voltage VDDA, the gate is connected to a clock signal CLKB, and the drain is connected to the drain of the first NMOS transistor NM 1. The gate of the first NMOS transistor NM1 is connected to the inverse signal V1DN of the first reset signal, and the source is grounded GNDA. The latch unit 11 has an input terminal connected to the drains of the first PMOS transistor PM1 and the first NMOS transistor NM1, and an output terminal triggering a signal TRIGGER _ OUT, and latches signals of the drains of the first PMOS transistor PM1 and the first NMOS transistor NM1 when the clock signal CLK is at a high level.

More specifically, the latch module 11 includes, as an example, a first inverter 111, a second inverter 112, a third inverter 113, and a first switch S1. An input end of the first inverter 111 is connected to the drains of the first PMOS transistor PM1 and the first NMOS transistor NM 1. The input terminal of the second inverter 112 is connected to the output terminal of the first inverter 111, and the output terminal is connected to the input terminal of the first inverter 111 via the first switch S1. The input end of the third inverter 113 is connected to the output end of the first inverter 111 and the input end of the second inverter 112, and outputs the TRIGGER signal TRIGGER _ OUT. In this example, the control end of the first switch S1 is connected to the clock signal CLKB, and when the clock signal CLKB is at a low level, the first switch S1 is turned on to implement a latch function.

It should be noted that any circuit structure that can implement a latch function when the clock signal CLK is at a high level is applicable to the present invention, and is not limited to this embodiment.

As another example, the trigger signal generating module 1 further includes a fourth inverter 12, an input end of the fourth inverter 12 is connected to the clock signal CLK, and an output end of the fourth inverter 12 is connected to the gate of the first PMOS transistor PM 1. The trigger signal generating module 1 further includes a fifth inverter 13, an input end of the fifth inverter 13 is connected to the first reset signal V1DB, and an output end of the fifth inverter 13 is connected to the gate of the first NMOS transistor NM 1.

As shown in fig. 2, the first pulse signal generating module 2 is connected to the output terminal of the TRIGGER signal generating module 1, receives the TRIGGER signal TRIGGER _ OUT, sets the first reset signal V1DB to be high when the TRIGGER signal TRIGGER _ OUT is low, slowly discharges the first reset signal V1DB when the TRIGGER signal TRIGGER _ OUT is high, and obtains the first pulse signal DISCH based on the and operation of the TRIGGER signal TRIGGER _ OUT and the first reset signal V1 DB.

Specifically, as an example, the first pulse signal generating module 2 includes a second PMOS transistor PM2, a second NMOS transistor NM2, a first resistor R1, a first capacitor C1, and a first and logic unit 21. The source of the second PMOS transistor PM2 is connected to the supply voltage VDDA, the gate is connected to the TRIGGER signal TRIGGER _ OUT, and the drain is connected to the drain of the second NMOS transistor NM2 via the first resistor R1. The gate of the second NMOS transistor NM2 is connected to the TRIGGER signal TRIGGER _ OUT, and the source is grounded GNDA. The upper polar plate of the first capacitor C1 is connected with the drain of the second PMOS pipe PM2, and the lower polar plate is grounded GNDA. A first input end of the first and logic unit 21 is connected to the TRIGGER signal TRIGGER _ OUT, and a second input end thereof is connected to an upper plate of the first capacitor C1, and outputs the first pulse signal DISCH.

It should be noted that, in this embodiment, the first pulse signal DISCH is a discharge control signal of the sense amplifier, and in practical use, the first pulse signal may be an arbitrary pulse control signal of the sense amplifier. Any circuit structure capable of generating the first pulse signal based on the trigger signal is applicable to the present invention, and is not limited to this embodiment.

As shown in fig. 1, 2 and 5, the principle of generating the first pulse signal DISCH is as follows:

when the chip responds to the read command, the corresponding logic signal in the chip is pulled high, and a clock signal CLK is sent out from the outside of the chip to the inside of the chip. When the pulse signal generating circuit does not operate, the clock signal CLK is at a low level by default, at this time, the inverse signal CLKB of the clock signal is 1(1 is at a high level, namely VDDA, and 0 is at a low level, namely GNDA), the drain output signal LAT of the first PMOS transistor PM1 and the first NMOS transistor NM1 is 0, the input signal LATB of the third inverter 113 is 1, the TRIGGER signal TRIGGER _ OUT is 0, the first reset signal V1DB is 1, the inverse signal V1DN of the first reset signal is 0, and the first pulse signal DISCH is 0.

When the clock signal CLK changes from 0 to 1, the inverse signal CLKB of the clock signal is 0, the first PMOS transistor PM1 is turned on, the first switch S1 is turned on (CLKB is 0, S1 is turned on, CLKB is 1, S1 is turned off), the drain output signal LAT of the first PMOS transistor PM1 and the first NMOS transistor NM1 is pulled high to become 1, the input signal LATB of the third inverter 113 is 0, the TRIGGER signal TRIGGER _ OUT is 1, the second NMOS transistor NM2 is turned on, the second PMOS transistor PM2 is turned off, the first reset signal V1DB is slowly discharged due to the influence of the first resistor R1 and the first capacitor C1 on the discharging speed, and when the first reset signal V1DB slowly turns over to the threshold voltage Vt of the NMOS transistor through the fifth inverter 13, the first NMOS transistor NM1 is turned on, and two situations occur:

in the first case, the clock signal CLK is at a lower frequency, and when the first PMOS transistor PM1 and the first NMOS transistor NM1 are turned on simultaneously, there is a direct path from power to ground, so the first PMOS transistor PM1 and the first NMOS transistor NM1 need to be properly sized to reduce the power consumption of the whole circuit, and due to the action of the latch unit 11, the drain output signal LAT of the first PMOS transistor PM1 and the first NMOS transistor NM1 is still 1, the input signal LATB of the third inverter 113 is 0, and the TRIGGER signal TRIGGER _ OUT is also 1; when the clock signal CLK changes from 1 to 0, the input signal CLKB of the third inverter 113 changes from 0 to 1, the first switch S1 is turned off, only the first NMOS tube NM1 is turned on at this time, the first PMOS tube PM1 is turned off, the drain output signals LAT of the first PMOS tube PM1 and the first NMOS tube NM1 are 0, the input signal LATB of the third inverter 113 is 1, the TRIGGER signal TRIGGER _ OUT is 0, the first reset signal V1DB is 1, and the first pulse signal DISCH changes to 1 when the TRIGGER signal TRIGGER _ OUT changes from 0 to 1. As shown in fig. 5, since the first reset signal V1DB is inputted to one end of the first and logic unit 21, the first reset signal V1DB is slowly discharged until the first pulse signal DISCH becomes 0, and the pulse width of the first pulse signal DISCH is determined by the time when the first reset signal V1DB is discharged through the first resistor R1 and the first capacitor C1.

In the second case, when the frequency of the clock signal CLK is high, the clock signal CLK changes from 1 to 0, the bar signal CLKB of the clock signal changes from 0 to 1, the first PMOS transistor PM1 is turned off, but the voltage of the first reset signal V1DB has not yet reached the switching voltage of the fifth inverter 13, so that the voltage of the first reset signal V1DN is flipped around the threshold voltage Vt of the NMOS transistor, the first NMOS transistor NM1 is also turned off, the bar signal CLKB of the clock signal becomes 1, the first switch S1 is turned off, since the drain output signals LAT of the first PMOS transistor PM1 and the first NMOS transistor NM1 are 1 at the previous time, the LAT signal of the drain output signals of the first PMOS transistor PM1 and the first NMOS transistor NM1 is in a floating state after the first NMOS transistor NM1 is turned off, the voltage value is slightly higher than the power voltage VDDA, so that the TRIGGER signal TRIGGER _ OUT is still 1; as the first reset signal V1DB continues to discharge, the first reset signal V1DB becomes the inverse signal V1DN of the first reset signal through the fifth inverter 13, when the voltage of the inverse signal V1DN of the first reset signal exceeds the threshold voltage Vt of the NMOS transistor, the drain output signal LAT of the first PMOS transistor PM1 and the first NMOS transistor NM1 changes from 1 to 0, the input signal LATB signal of the third inverter 113 changes from 0 to 1, the TRIGGER signal TRIGGER _ OUT changes from 1 to 0, and the first reset signal V1DB changes to 1 again, in which there is no direct path from the power source to the ground, so the circuit power consumption is extremely small compared to the first case, and the pulse width of the first pulse signal DISCH is still determined by the time when the first reset signal V1DB discharges through the first resistor R1 and the first capacitor C1.

It can be seen that, when the clock signal CLK changes from 0 to 1, the pulse signal generating circuit starts to operate, the drain output signal LAT of the first PMOS transistor PM1 and the first NMOS transistor NM1 controls the TRIGGER signal TRIGGER _ OUT, the TRIGGER signal TRIGGER _ OUT controls the turn-off and turn-on of the second PMOS transistor PM2 and the second NMOS transistor NM2, the second PMOS transistor PM2 is turned-off, the second NMOS transistor NM2 is turned-on, the first reset signal V1DB discharges slowly, and the discharge is so slow that the inverse signal V1DN of the first reset signal becomes 1, and the first reset signal V1DB (by the inverse signal V1DN of the first reset signal) in turn controls the inversion of the drain output signal LAT of the first PMOS transistor PM1 and the first NMOS transistor NM 1. The drain output signals LAT of the first PMOS transistor PM1 and the first NMOS transistor NM1 and the TRIGGER signal TRIGGER _ OUT are in the same direction, and if the drain output signals LAT of the first PMOS transistor PM1 and the first NMOS transistor NM1 are 1, the TRIGGER signal TRIGGER _ OUT is 1; the drain output signals LAT of the first PMOS transistor PM1 and the first NMOS transistor NM1 are 0, and the TRIGGER signal TRIGGER _ OUT is 0. The inverse signal CLKB of the clock signal controls the start of the circuit, the first pulse signal DISCH changes from 0 to 1, the first reset signal V1DB controls the inversion of the drain output signal LAT of the first PMOS transistor PM1 and the first NMOS transistor NM1, thereby controlling the reset of the circuit, and the first pulse signal DISCH changes from 1 to 0. Indirectly, the TRIGGER _ OUT controls the reset of the first reset signal V1DB, and the first reset signal V1DB further affects the inversion of the TRIGGER _ OUT every CLK, and the circuit operates every CLK.

As shown in fig. 3, as another implementation manner of the present invention, the pulse generating circuit further includes a second pulse signal generating module 3. The second pulse signal generating module 3 receives the inverse signal DISCHB of the first pulse signal, generates a second reset signal V2DB of a high level when the inverse signal DISCHB of the first pulse signal is at a low level, slowly discharges the second reset signal V2DB when the inverse signal DISCHB of the first pulse signal is at a high level, and obtains a second pulse signal PRCH based on an and operation of the inverse signal DISCHB of the first pulse signal and the second reset signal V2 DB.

Specifically, as an example, the second pulse signal generating module 3 includes a third PMOS transistor PM3, a third NMOS transistor NM3, a second resistor R2, a second capacitor C2, and a second and logic unit 31. The source of the third PMOS transistor PM3 is connected to the power supply voltage VDDA, the gate is connected to the inverse signal DISCHB of the first pulse signal, and the drain is connected to the drain of the third NMOS transistor NM3 via the second resistor R2. The gate of the third NMOS transistor NM3 is connected to the inverse signal DISCHB of the first pulse signal, and the source is grounded GNDA. The upper polar plate of the second capacitor C2 is connected with the drain of the third PMOS pipe PM3, and the lower polar plate is grounded GNDA. The first input terminal of the second and logic unit 31 is connected to the inverse signal DISCHB of the first pulse signal, and the second input terminal is connected to the upper plate of the second capacitor C2 to output the second pulse signal PRCH.

As another example, the second pulse signal generating module 3 further includes a sixth inverter 32, an input end of the sixth inverter 32 is connected to the first pulse signal DISCH, and an output end of the sixth inverter 32 is connected to the gate of the third PMOS transistor PM 3.

In this embodiment, the second pulse signal PRCH is a precharge control signal of the sense amplifier, and in practical use, the second pulse signal PRCH can be used as an arbitrary pulse control signal of the sense amplifier. Any circuit structure capable of generating the second pulse signal based on the first pulse signal is applicable to the present invention, and is not limited to this embodiment.

As shown in fig. 3 and 5, the principle of generating the second pulse signal PRCH is as follows:

when the pulse signal generating circuit does not operate, the first pulse signal DISCH is 0, the inverse signal DISCHB of the first pulse signal is 1, the second reset signal V2DB is 0, and the second pulse signal PRCH is 0. When the first pulse signal DISCH changes from 0 to 1, the inverse signal DISCHB of the first pulse signal changes from 1 to 0, at which time the third PMOS transistor PM3 is turned on, the third NMOS transistor NM3 is turned off, the second reset signal V2DB changes from 0 to 1, and the second pulse signal PRCH is 0. When the first pulse signal DISCH is changed from 1 to 0, the inverse signal DSICHB of the first pulse signal is changed from 0 to 1, the second pulse signal PRCH is changed from 0 to 1, the third PMOS transistor PM3 is turned off, the third NMOS transistor NM3 is turned on, the input terminal of the second and logic unit 31 is connected to the second reset signal V2DB and the inverse signal DISCHB of the first pulse signal, respectively, after the second reset signal V2DB is slowly discharged to a certain voltage, the second pulse signal PRCH is changed to 0, and the pulse width of the second pulse signal PRCH is determined by the discharge time of the second resistor R2 and the second capacitor C2.

As shown in fig. 4, as another implementation manner of the present invention, the pulse generating circuit further includes a third pulse signal generating module 4. The second pulse signal generating module 4 receives the inverted signal PRCHB of the second pulse signal, generates a high-level third reset signal V3DB when the inverted signal PRCHB of the second pulse signal is at a low level, slowly discharges the third reset signal V3DB when the inverted signal PRCHB of the second pulse signal is at a high level, and obtains a third pulse signal SAEN based on an and operation of the inverted signal PRCHB of the second pulse signal and the third reset signal V3 DB.

Specifically, as an example, the third pulse signal generating module 4 includes a fourth PMOS transistor PM4, a fourth NMOS transistor NM4, a third resistor R3, a third capacitor C3, and a third and logic unit 41. The source of the fourth PMOS transistor PM4 is connected to the power supply voltage VDDA, the gate is connected to the inverse signal PRCHB of the second pulse signal, and the drain is connected to the drain of the fourth NMOS transistor NM4 via the third resistor R3. The gate of the fourth NMOS transistor NM4 is connected to the inverse PRCHB of the second pulse signal, and the source is grounded GNDA. The upper polar plate of the third capacitor C3 is connected to the drain of the fourth PMOS transistor PM4, and the lower polar plate is grounded GNDA. The third and logic unit 41 has a first input end connected to the inverse signal PRCHB of the second pulse signal, and a second input end connected to the upper plate of the third capacitor C3, and outputs the third pulse signal SAEN.

As another example, the third pulse signal generating module 4 further includes a seventh inverter 42, an input end of the seventh inverter 42 is connected to the second pulse signal PRCH, and an output end of the seventh inverter 42 is connected to the gate of the fourth PMOS transistor PM 4.

It should be noted that, in this embodiment, the third pulse signal SAEN is an enable signal of the sense amplifier, and in practical use, the third pulse signal SAEN can be used as an arbitrary pulse control signal of the sense amplifier. Any circuit structure capable of generating the third pulse signal based on the second pulse signal is applicable to the present invention, and is not limited to this embodiment.

As shown in fig. 4 and 5, the principle of generating the third pulse signal SAEN is as follows:

when the pulse signal generating circuit does not work, the second pulse signal PRCH is 0, the inverted signal PRCHB of the second pulse signal is 1, the third reset signal V3DB is 0, and the third pulse signal SAEN is 0. When the second pulse signal PRCH changes from 0 to 1, the inverse signal PRCHB of the second pulse signal changes from 1 to 0, at this time, the fourth PMOS transistor PM4 is turned on, the fourth NMOS transistor NM4 is turned off, the third reset signal V3DB changes from 0 to 1, and the third pulse signal SAEN is 0. When the second pulse signal PRCH changes from 1 to 0, the inverse signal PRCHB of the second pulse signal changes from 0 to 1, the third pulse signal SAEN changes from 0 to 1, at this time, the fourth PMOS transistor PM4 is turned off, the fourth NMOS transistor NM4 is turned on, the input end of the third and logic unit 41 is connected to the third reset signal V3DB and the inverse signal PRCHB of the second pulse signal, respectively, after the third reset signal V3DB slowly discharges to a certain voltage, the third pulse signal SAEN changes to 0, and the pulse width of the third pulse signal SAEN is determined by the discharge time of the third resistor R3 and the third capacitor C3.

As shown in fig. 5, 3 pulse waveforms which are not affected by an external clock and are pulled up sequentially are generated by the external clock signal CLK, and it should be noted that the sum of the RC discharge times in the first pulse signal generation module 2, the second pulse signal generation module 3 and the third pulse signal generation module 4 may not exceed the clock period of a single clock signal CLK at the fastest using frequency; meanwhile, the first PMOS transistor PM1 and the first NMOS transistor NM1 need to be set to a reasonable size to reduce the power consumption of the circuit when the clock signal CLK is at a low frequency.

Example two

As shown in fig. 6, the present embodiment provides a memory, including: NOR FLASH memory array, sense amplifier and pulse generation circuit of embodiment one.

Specifically, the NOR FLASH memory array is used for storing data; the sensitive amplifier is connected with the output end of the NOR FLASH storage array and is used for reading out the output signal of the NOR FLASH storage array; the pulse generating circuit receives an external clock signal CLK and generates a pulse signal for controlling the sense amplifier.

Specifically, the speed of reading data from the memory is determined by the frequency of the external clock, which varies from 1KHZ to 133MHZ, with a duty cycle of typically fifty percent.

It should be noted that the control signals provided by the pulse generating circuit include, but are not limited to, a discharge control signal DISCH, a precharge control signal PRCH, and an enable signal SAEN.

In summary, the present invention provides a pulse signal generating circuit and a memory, including: the trigger signal generating module and the first pulse signal generating module are connected to the output end of the trigger signal generating module; the trigger signal generation module comprises a first PMOS (P-channel metal oxide semiconductor) tube, a first NMOS (N-channel metal oxide semiconductor) tube and a latch unit, wherein the source electrode of the first PMOS tube is connected with power supply voltage, the grid electrode of the first PMOS tube is connected with a counter signal of a clock signal, and the drain electrode of the first PMOS tube is connected with the drain electrode of the first NMOS tube; the grid electrode of the first NMOS tube is connected with the inverse signal of the first reset signal, and the source electrode of the first NMOS tube is grounded; the input end of the latch unit is connected with the drain electrodes of the first PMOS tube and the first NMOS tube, the output end of the latch unit triggers signals, and when the clock signal is at a high level, the latch unit latches the signals of the drain electrodes of the first PMOS tube and the first NMOS tube; the first pulse signal generation module receives the trigger signal, sets the first reset signal to be a high level when the trigger signal is at a low level, slowly discharges the first reset signal when the trigger signal is at a high level, and obtains a first pulse signal based on an and operation of the trigger signal and the first reset signal. The pulse signal generating circuit and the memory provide a pulse waveform which is not influenced by the frequency of an external clock for the sensitive amplifier in the chip, the pulse width of the pulse signal used by the sensitive amplifier in the chip is not changed under different frequencies, the problem that the clamping voltage of the traditional sensitive amplifier is not stable enough when the chip works under different frequencies and the data reading is possibly wrong is solved, the working frequency of the chip is wider, and the application of the chip is wider. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims

1. A pulse signal generating circuit for controlling a sense amplifier, the pulse signal generating circuit comprising at least:

2. The pulse signal generating circuit according to claim 1, wherein: the latch module comprises a first phase inverter, a second phase inverter, a third phase inverter and a first switch, wherein the input end of the first phase inverter is connected with the drain electrodes of the first PMOS tube and the first NMOS tube; the input end of the second inverter is connected with the output end of the first inverter, and the output end of the second inverter is connected with the input end of the first inverter through the first switch; and the input end of the third phase inverter is connected with the output end of the first phase inverter and the input end of the second phase inverter, and the trigger signal is output.

3. The pulse signal generating circuit according to claim 1, wherein: the first pulse signal generating module comprises a second PMOS tube, a second NMOS tube, a first resistor, a first capacitor and a first logic unit; the source electrode of the second PMOS tube is connected with the power supply voltage, the grid electrode of the second PMOS tube is connected with the trigger signal, and the drain electrode of the second PMOS tube is connected with the drain electrode of the second NMOS tube through the first resistor; the grid electrode of the second NMOS tube is connected with the trigger signal, and the source electrode of the second NMOS tube is grounded; the upper polar plate of the first capacitor is connected with the drain electrode of the second PMOS tube, and the lower polar plate is grounded; the first input end of the first AND logic unit is connected with the trigger signal, and the second input end of the first AND logic unit is connected with the upper polar plate of the first capacitor and outputs the first pulse signal.

4. The pulse signal generation circuit according to any one of claims 1 to 3, wherein: the first pulse signal is a discharge control signal.

5. The pulse signal generation circuit according to any one of claims 1 to 3, wherein: the pulse generating circuit further comprises a second pulse signal generating module, wherein the second pulse signal generating module receives the inverted signal of the first pulse signal, generates a second reset signal with a high level when the inverted signal of the first pulse signal is at a low level, slowly discharges the second reset signal when the inverted signal of the first pulse signal is at a high level, and obtains the second pulse signal based on the AND operation of the inverted signal of the first pulse signal and the second reset signal.

6. The pulse signal generating circuit according to claim 5, wherein: the second pulse signal generating module comprises a third PMOS tube, a third NMOS tube, a second resistor, a second capacitor and a second AND logic unit; the source electrode of the third PMOS tube is connected with the power supply voltage, the grid electrode of the third PMOS tube is connected with the inverse signal of the first pulse signal, and the drain electrode of the third PMOS tube is connected with the drain electrode of the third NMOS tube through the second resistor; the grid electrode of the third NMOS tube is connected with the inverse signal of the first pulse signal, and the source electrode of the third NMOS tube is grounded; the upper polar plate of the second capacitor is connected with the drain electrode of the third PMOS tube, and the lower polar plate is grounded; and the first input end of the second AND logic unit is connected with the inverse signal of the first pulse signal, and the second input end of the second AND logic unit is connected with the upper polar plate of the second capacitor to output the second pulse signal.

7. The pulse signal generating circuit according to claim 5, wherein: the second pulse signal is a precharge control signal.

8. The pulse signal generation circuit according to any one of claims 1 to 3, wherein: the pulse generating circuit further comprises a third pulse signal generating module, wherein the third pulse signal generating module receives the inverted signal of the second pulse signal, generates a high-level third reset signal when the inverted signal of the second pulse signal is at a low level, slowly discharges the third reset signal when the inverted signal of the second pulse signal is at a high level, and obtains the third pulse signal based on the and operation of the inverted signal of the second pulse signal and the third reset signal.

9. The pulse signal generating circuit according to claim 8, wherein: the third pulse signal generation module comprises a fourth PMOS tube, a fourth NMOS tube, a third resistor, a third capacitor and a third AND logic unit; the source electrode of the fourth PMOS tube is connected with the power supply voltage, the grid electrode of the fourth PMOS tube is connected with the inverse signal of the second pulse signal, and the drain electrode of the fourth PMOS tube is connected with the drain electrode of the fourth NMOS tube through the third resistor; the grid electrode of the fourth NMOS tube is connected with the inverse signal of the second pulse signal, and the source electrode of the fourth NMOS tube is grounded; the upper polar plate of the third capacitor is connected with the drain electrode of the fourth PMOS tube, and the lower polar plate is grounded; and the first input end of the third AND logic unit is connected with the inverted signal of the second pulse signal, and the second input end of the third AND logic unit is connected with the upper polar plate of the third capacitor to output the third pulse signal.

10. The pulse signal generating circuit according to claim 8, wherein: the third pulse signal is a sense amplifier enable signal.

11. A memory, characterized in that the memory comprises at least:

a NOR FLASH memory array, a sense amplifier and a pulse generating circuit according to any of claims 1-10;

the NOR FLASH memory array is used for storing data;

the sensitive amplifier is connected with the output end of the NOR FLASH storage array and is used for reading out the output signal of the NORFLASH storage array;