CN114384731B

CN114384731B - Array substrate and liquid crystal display panel

Info

Publication number: CN114384731B
Application number: CN202111640564.8A
Authority: CN
Inventors: 杨艳娜; 袁海江
Original assignee: HKC Co Ltd; Chongqing HKC Optoelectronics Technology Co Ltd
Current assignee: HKC Co Ltd; Chongqing HKC Optoelectronics Technology Co Ltd
Filing date: 2021-12-29
Publication date: 2024-06-28
Anticipated expiration: 2041-12-29

Abstract

The application relates to an array substrate and a liquid crystal display panel. The liquid crystal display panel comprises a display area and a non-display area located on the periphery of the display area, wherein a plurality of conductive pads are arranged on the non-display area of the array substrate at intervals, each conductive pad comprises a first metal layer, an insulating layer and a conductive layer which are sequentially formed on the substrate, the first metal layer is connected with a first public electrode located in the display area in a same layer and is electrically connected with the first public electrode, a plurality of through holes are formed in the insulating layer, so that the conductive layer is electrically connected with the first public electrode, the through holes are arranged in a slit shape, a preset included angle is formed between each through hole and a first direction, and the first direction is the direction of the non-display area surrounding the display area. The array substrate can prevent the liquid drops of the alignment film from accumulating in a non-display area, avoid the problem that poor conduction occurs because conductive particles in the frame glue cannot puncture the alignment film, and improve the display effect.

Description

Array substrate and liquid crystal display panel

Technical Field

The present application relates to the field of display technologies, and in particular, to an array substrate and a liquid crystal display panel.

Background

The Liquid crystal display panel (LCD) includes an array substrate, a color film substrate, and a Liquid crystal layer disposed between the array substrate and the color film substrate. The array substrate and the color film substrate are respectively provided with an alignment film on the inner sides thereof for guiding the arrangement direction of the liquid crystal molecules. In addition, the array substrate and the color film substrate are mechanically and electrically connected through frame glue positioned in the frame area.

Because the topography of the frame glue bonding pads at the side of the array substrate are staggered and form a grid shape, the alignment film liquid is difficult to diffuse and is accumulated to form a thicker film layer, so that conductive particles in the frame glue are difficult to pierce the alignment film layer and cannot conduct the array substrate and the color film substrate, and the problems of poor frame glue conduction and abnormal display of the liquid crystal display panel occur.

Disclosure of Invention

The application aims to provide an array substrate and a liquid crystal display panel, wherein the array substrate can promote alignment film liquid drops to rapidly diffuse at a conductive bonding pad of a non-display area, so that the problem that conductive particles in frame glue cannot puncture an alignment film due to accumulation of the alignment film liquid drops can be solved, and the problem of abnormal display can be solved.

In a first aspect, an embodiment of the present application provides an array substrate, including a display area and a non-display area located at a periphery of the display area, where the array substrate is provided with a plurality of conductive pads distributed at intervals in the non-display area, the conductive pads include a first metal layer, an insulating layer and a conductive layer sequentially formed on a first substrate, the first metal layer is in the same layer as and electrically connected with a first common electrode located in the display area, the insulating layer is formed with a plurality of vias so that the conductive layer is electrically connected with the first common electrode, the vias are in a slit-shaped arrangement, and are arranged at a predetermined included angle with a first direction, and the first direction is a direction in which the non-display area encloses the display area.

In one possible implementation manner, the value range of the predetermined included angle α between the via hole and the first direction is: alpha is more than or equal to 0 and less than 90 degrees.

In one possible embodiment, the spacing between two adjacent vias is S, the width of the via is W, and S/(W+S) > 30%.

In one possible embodiment, the spacing S between two adjacent vias is > 5.5 μm; and/or the width W of the via is > 14.5 μm.

In one possible embodiment, the via includes a first via and a second via, the first via and the second via being symmetrically disposed with respect to a centerline of the conductive pad along a second direction, the second direction being perpendicular to the first direction.

In one possible embodiment, the via further includes a third via and a fourth via, and the third via and the first via are symmetrically disposed with respect to a centerline of the conductive pad in the first direction, and the fourth via and the second via are symmetrically disposed with respect to a centerline of the conductive pad in the first direction.

In one possible embodiment, the conductive pad includes a plating region and an edge region on at least one side of the plating region, the insulating layer and the conductive layer are located in the plating region, the first metal layer is laid on the plating region and the edge region, and a side of the via hole facing the edge region communicates with the edge region.

In one possible embodiment, the conductive pad includes a plating region and an edge region on at least one side of the plating region, the insulating layer and the conductive layer are located in the plating region, and the first common electrode extends from the display region to the edge region of the non-display region and is electrically connected to the first metal layer exposed by the via hole.

In a possible implementation manner, the array substrate further includes a first alignment film and a frame glue, the first alignment film is located on one side of the conductive layer away from the first substrate, conductive particles are formed in the frame glue, the conductive particles are contained in the through holes, one end of each conductive particle is electrically connected with the first common electrode through the first alignment film, and the other end of each conductive particle is electrically connected with the second common electrode through the second alignment film on the color film substrate side of the liquid crystal display panel.

In a second aspect, an embodiment of the present application further provides a liquid crystal display panel, including an array substrate as described above; the color film substrate is arranged opposite to the array substrate; the liquid crystal layer is arranged between the array substrate and the color film substrate.

According to the array substrate and the liquid crystal display panel provided by the embodiment of the application, the conductive bonding pad of the non-display area is subjected to patterning design, namely, a plurality of slit-shaped through holes are arranged on the insulating layer of the conductive bonding pad at intervals, and the through holes and the non-display area are arranged at a preset included angle around the enclosing direction of the display area, so that the alignment film liquid drops can be promoted to rapidly diffuse at the conductive bonding pad of the non-display area, the problem that poor conduction occurs due to the fact that the conductive particles in the frame glue cannot puncture the alignment film due to accumulation of the alignment film liquid drops at the through holes is solved, and the problem of abnormal display is improved.

Drawings

Features, advantages, and technical effects of exemplary embodiments of the present application will be described below with reference to the accompanying drawings. In the drawings, like parts are designated with like reference numerals. The drawings are not drawn to scale, but are merely for illustrating relative positional relationships, and the layer thicknesses of certain portions are exaggerated in order to facilitate understanding, and the layer thicknesses in the drawings do not represent the actual layer thickness relationships.

Fig. 1 is a schematic top view of a liquid crystal display panel according to an embodiment of the present application;

Fig. 2 shows a cross-sectional view of the liquid crystal display panel of fig. 1 along the B-B direction;

fig. 3 is a schematic structural diagram of a conductive pad of an array substrate according to a first embodiment of the present application;

Fig. 4 is a schematic structural diagram of a conductive pad of an array substrate according to a second embodiment of the present application;

Fig. 5 is a schematic structural diagram of a conductive pad of an array substrate according to a third embodiment of the present application;

Fig. 6 is a schematic structural diagram of a conductive pad of an array substrate according to a fourth embodiment of the present application;

Fig. 7 is a schematic structural diagram of a conductive pad of an array substrate according to a fifth embodiment of the present application;

fig. 8 is a schematic structural diagram of a conductive pad of an array substrate according to a sixth embodiment of the present application.

Reference numerals illustrate:

1. an array substrate; AA. A display area; NA, non-display area; px-subpixels;

10. a conductive pad; 101. a plating region; 102. an edge region; 11. a first substrate base plate;

12. A first metal layer; 121. a first common electrode;

13. an insulating layer; 13a, a gate insulating layer; 13b, a passivation layer; 131. a via hole; 131a, first via holes; 131b, second via holes; 131c, a third via; 131d, fourth via holes;

14. A conductive layer; 15. a first alignment film;

16. frame glue; 161. conductive particles;

2. A color film substrate; 21. a second substrate base plate; 22. a second common electrode; 23. a second alignment film; 3. and a liquid crystal layer.

Detailed Description

Features and exemplary embodiments of various aspects of the application are described in detail below. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the application. It will be apparent, however, to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the application by showing examples of the application. In the drawings and the following description, at least some well-known structures and techniques have not been shown in detail in order not to unnecessarily obscure the present application; also, the size of the region structures may be exaggerated for clarity. Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

Fig. 1 is a schematic top view of a liquid crystal display panel according to an embodiment of the present application, and fig. 2 is a cross-sectional view of the liquid crystal display panel in fig. 1 along a B-B direction.

Referring to fig. 1 and 2, an embodiment of the present application provides a liquid crystal display panel, including: the liquid crystal display comprises an array substrate 1, a color film substrate 2 arranged opposite to the array substrate 1 and a liquid crystal layer 3 arranged between the array substrate 1 and the color film substrate 2. The liquid crystal layer 3 comprises a plurality of liquid crystal molecules, typically rod-shaped, which both flow like a liquid and have certain crystal characteristics. When the liquid crystal molecules are in an electric field, the alignment direction thereof is changed according to the change of the electric field.

The liquid crystal display panel comprises a display area AA and a non-display area NA positioned at the periphery of the display area AA, and a plurality of conductive pads 10 which are distributed at intervals are formed in the non-display area NA of the array substrate 1 along the enclosing direction. In the process of forming a box of a liquid crystal display panel, a first alignment film 15 and a second alignment film 23 are generally manufactured on opposite surfaces of an array substrate 1 and a color film substrate 2, the first alignment film 15 and the second alignment film 23 are used for limiting the orientation of liquid crystal molecules in a liquid crystal layer 3, then a sealed frame glue 16 is coated on a plurality of conductive pads 10 of the array substrate 1, liquid crystal is dripped, the array substrate 1 and the color film substrate 2 are attached under vacuum, and finally the frame glue 16 is cured through ultraviolet irradiation, so as to complete the encapsulation of the array substrate 1 and the color film substrate 2.

As shown in fig. 2, the color film substrate 2 includes a second common electrode 22 and a second alignment film 23 sequentially formed on a second substrate 21, conductive particles 161 are formed in the frame glue 16, the conductive particles 161 are accommodated in the via holes 131 of the conductive pads 10, one end of the conductive particles 161 is electrically connected with the first common electrode 121 through the first alignment film 15, and the other end is electrically connected with the second common electrode 22 through the second alignment film 23 on one side of the color film substrate 2.

Alternatively, the frame adhesive 16 includes an ultraviolet curable resin such as an epoxy resin, and a plurality of conductive particles 161 and glass fibers as conductive materials are dispersed and mixed. The outer diameter of the conductive particles 161 is generally about 5 μm, and the diameter of the glass fibers is generally about 4 μm. The line width of the frame adhesive 16 is generally, for example, about 0.5 mm.

In the related art, the conductive pads 10 are provided with grid-shaped through holes with staggered heights, so that alignment film liquid is difficult to diffuse outwards through the through holes to form a thicker film layer in a stacked manner, and conductive particles 161 in the frame glue 16 are difficult to pierce the alignment film and cannot conduct the array substrate 1 and the color film substrate 2, so that the problems of poor frame glue conduction and abnormal display of the display panel occur.

Therefore, the embodiment of the application provides an array substrate 1, which can promote the rapid diffusion of alignment film droplets at the conductive pad 10 of the non-display area NA, improve the problem of poor conduction caused by the failure of the conductive particles 161 in the frame glue 16 to pierce the alignment film due to the accumulation of the alignment film droplets, and improve the problem of abnormal display

The following describes in detail the specific structure of the array substrate provided in each embodiment of the present application with reference to the accompanying drawings.

First embodiment

Fig. 3 is a schematic structural diagram of a conductive pad of an array substrate according to a first embodiment of the present application.

As shown in fig. 2 and 3, a first embodiment of the present application proposes an array substrate 1, in which a plurality of conductive pads 10 are formed at intervals in a non-display area NA, the conductive pads 10 include a first metal layer 12, an insulating layer 13 and a conductive layer 14 sequentially formed on a first substrate 11, the first metal layer 12 is in the same layer as and electrically connected to a first common electrode 121 located in the display area AA, and the insulating layer 13 is formed with a plurality of vias 131 to electrically connect the conductive layer 14 to the first common electrode 121.

The via hole 131 is disposed in a slit shape, and a predetermined angle is formed between the via hole 131 and a first direction, where the first direction is a direction in which the non-display area NA encloses the display area AA. The conductive particles 161 in the sealant 16 are accommodated in the through holes 131 to conduct the array substrate 1 and the color film substrate 2.

Alternatively, the display area AA of the array substrate 1 is rectangular in shape, and the non-display area NA is disposed around the periphery of the display area AA. When the conductive pad 10 is located in the length direction of the array substrate 1, the enclosing direction is the length direction of the array substrate 1; when the conductive pads 10 are located in the width direction of the array substrate 1, the enclosing direction is the width direction of the array substrate 1.

In the display area AA, the array substrate 1 includes a first metal layer 12, a gate insulating layer 13a, a semiconductor layer, a second metal layer, a passivation layer 13b, a conductive layer 14, and a first alignment film 15 sequentially formed on a first substrate 11. The first metal layer 12 is formed with a scan line, a gate electrode of a thin film transistor, and a first common electrode 121, and the second metal layer is formed with a data line, a source electrode of a thin film transistor, and a drain electrode of a thin film transistor. The conductive layer 14 is formed with a pixel electrode, one of a source electrode and a drain electrode is electrically connected to the data line, and the other of the source electrode and the drain electrode is electrically connected to the pixel electrode.

In order to simplify the manufacturing process, the film layers of the plurality of conductive pads 10 of the non-display area NA of the array substrate 1 are simultaneously manufactured with the display area AA. Wherein the first metal layer 12 of the conductive pad 10 is in the same layer and electrically connected with the first common electrode 121, the insulating layer 13 of the conductive pad 10 may include a gate insulating layer 13a and a passivation layer 13b, and the conductive layer 14 may be electrically connected with the first common electrode 121 by providing a via hole 131 on the insulating layer 13.

Since the first alignment film 15 and the second alignment film 23 have fluidity, they are formed by adding a solvent to a resin material such as polyimide to reduce the viscosity thereof. Taking the process of the first alignment film 15 as an example, there are mainly two manufacturing methods of the first alignment film 15, one is to transfer the first alignment film 15 using a Printing plate, and the other is to manufacture the first alignment film 15 by a coating method of ink jet Printing (ink jet Printing). Taking an inkjet printing method as an example, firstly inputting the graph of the first alignment film 15 into a computer, then spraying the solution of the first alignment film 15 onto the array substrate 1 through a spray head, and curing to form the first alignment film 15.

In order to promote the rapid diffusion of the droplets of the first alignment film 15 at the plurality of conductive pads 10, in this embodiment, the conductive pads 10 are patterned, that is, a plurality of slit-shaped vias 131 are disposed on the insulating layer 13 at intervals, and the insulating layer 13 between two adjacent vias 131 easily diffuses the droplets of the first alignment film 15 due to the flat topography and fills the non-display area NA, as shown by the arrow direction in fig. 3. Because the via hole 131 and the non-display area NA enclose the first direction of the display area AA to form a predetermined angle therebetween, the first alignment film 15 does not directly enter the display area AA after being diffused from the insulating layer 13 with a flat topography, and the first alignment film 15 is prevented from being stacked at the edge of the display area AA.

In addition, the droplets of the first alignment film 15 may be directly diffused from the conductive pad 10 along the slit of the slit-shaped via 131, and no other film layer is blocked and not accumulated in the flowing process of the droplets, so that a thinner film layer is formed after curing, and the conductive particles in the frame glue 16 can pierce the thinner first alignment film 15 formed on the via 131, so that the first common electrode 121 on one side of the array substrate 1 is electrically connected with the second common electrode 22 on one side of the color film substrate 2.

According to the array substrate 1 provided by the embodiment of the application, the conductive pad 10 of the non-display area NA is subjected to patterning design, namely, the insulating layer 13 is provided with the plurality of slit-shaped through holes 131, and the through holes 131 and the first direction of the non-display area NA surrounding the display area AA are arranged at the preset included angle, so that the liquid drops of the first alignment film 15 can be promoted to rapidly spread at the conductive pad 10 of the non-display area NA, the problem that poor conduction occurs because the conductive particles 161 in the frame glue 16 cannot puncture the first alignment film 15 due to the accumulation of the liquid drops of the first alignment film 15 at the through holes is solved, and the display effect is improved.

In some embodiments, the predetermined angle α between the via 131 and the first direction is in the range of: alpha is more than or equal to 0 and less than 90 degrees. When the conductive pad 10 is located in the length direction of the array substrate 1, the first direction is the length direction of the array substrate 1, and the via 131 forms a predetermined angle α with the length direction of the array substrate 1. When the conductive pad 10 is located in the width direction of the array substrate 1, the first direction is the width direction of the array substrate 1, and the via 131 forms a predetermined angle α with the width direction of the array substrate 1.

The value range of the preset included angle alpha satisfies the condition that alpha is less than or equal to 90 degrees, the diffusion path of the through holes 131 can be longer, so that a diffusion channel formed between two adjacent through holes 131 is paved with the whole conductive bonding pad 10, meanwhile, the first alignment film 15 liquid drops are prevented from directly flowing to the display area AA, the first alignment film 15 liquid drops are enabled to be rapidly diffused in the non-display area AA, and the first alignment film 15 liquid drops are prevented from being accumulated at the through holes 131.

In some embodiments, the spacing between two adjacent vias 131 is S, the width of the via 131 is W, and S/(W+S) > 30%.

As shown in fig. 3 and 4, since the sealant 16 is applied on the conductive pad 10 and is required to be cured by irradiation of ultraviolet rays, the width of the via 131 is required to satisfy the curing requirement of the ultraviolet rays of the sealant 16. If the via 131 is too narrow, ultraviolet light cannot be irradiated into the via 131, and thus the frame cement 16 cannot be sufficiently cured. If the via 131 is too wide, a short circuit may occur between the conductive layer 14 and the first metal layer 12, affecting the normal use of the conductive pad 10. Optionally, the width W of the via 131 is > 14.5 μm.

In addition, the space S between two adjacent vias 131 needs to meet the process requirements. Too large a space S, too small a number of vias 131 may affect the conductivity between the first common electrode 121 on the side of the array substrate 1 and the second common electrode 22 on the side of the color film substrate 2; too small a spacing S increases the difficulty of the process. Alternatively, the spacing S between two adjacent vias 131 is > 5.5 μm.

Further, when S/(W+S) is not less than 30%, not only the requirements of the process technology but also the light curing requirements of the frame glue 16 can be met.

In some embodiments, the conductive pad 10 includes a plating region 101 and an edge region 102 located on at least one side of the plating region 101, the insulating layer 13 and the conductive layer 14 are located on the plating region 101, the first metal layer 12 is laid on the plating region 101 and the edge region 102, and a side of the via 131 facing the edge region 102 communicates with the edge region 102.

As shown in fig. 2 and 4, the conductive pad 10 includes a plating region 101 and an edge region 102 located on the outer peripheral side of the plating region 101, wherein the conductive layer 14 is laid on the plating region 101 and the edge region 102, and the conductive layer 14 is not shown in the present embodiment for the convenience of viewing the via hole 131. The first metal layer 12 is laid on the plating region 101 and the edge region 102, and since the first metal layer 12 of the plating region 101 is covered with the insulating layer 13 and the conductive layer 14, only the first metal layer 12 of the edge region 102, that is, the portion filled with diagonal hatching in fig. 4 is exposed. The insulating layer 13 is filled with dot hatching, and a via 131 is formed by digging out a bar-shaped insulating block on the insulating layer 13. The side of the via hole 131 facing the edge region 102 communicates with the edge region 102, i.e., the via hole 131 exposes the first metal layer 12, and the first metal layer 12 is electrically connected to the first common electrode 121 of the display area AA in the same layer, so that the conductive particle 161 contained in the via hole 131 contacts the first metal layer 12 and is electrically connected to the first common electrode 121. The other side of the conductive particles 161 is electrically connected to the second common electrode 22 through the second alignment film 23 on one side of the color film substrate 2, thereby turning on the liquid crystal display panel.

In addition, the smaller the number of the via holes 131, the smaller the contact area between the conductive particles 161 in the frame glue 16 and the first metal layer 12, the larger the resistance value, which may affect the conductivity of the conductive pad 10. The number of the vias 131 needs to consider factors such as the width of the vias 131, and is determined according to specific design requirements, and will not be described again.

Second embodiment

Fig. 4 is a schematic structural diagram of a conductive pad of an array substrate according to a second embodiment of the present application.

As shown in fig. 4, a second embodiment of the present application proposes a conductive pad 10 of an array substrate 1, which is similar to the conductive pad 10 of the array substrate 1 provided in the first embodiment, except that the edge structure of the conductive pad 10 is different.

Specifically, the conductive pad 10 includes a plating region 101 and an edge region 102 located at least one side of the plating region 101, and the insulating layer 13 and the conductive layer 14 are located at the plating region 101, and the first common electrode 121 extends from the display region AA to the edge region 102 of the non-display region NA and is electrically connected to the first metal layer 12 exposed by the via hole 131.

As shown in fig. 4, the conductive pad 10 includes a plating region 101 and an edge region 102 located on the outer peripheral side of the plating region 101, wherein the conductive layer 14 is laid on the plating region 101 and the edge region 102, and the conductive layer 14 is not shown in the present embodiment for the convenience of viewing the via hole 131. The first metal layer 12 is laid on the plating region 101 and the edge region 102, and since the first metal layer 12 of the plating region 101 is covered with the insulating layer 13 and the conductive layer 14, only the first common electrode 121 of the edge region 102, that is, the portion filled with diagonal hatching in fig. 4 is exposed. The insulating layer 13 is filled with dot hatching, via holes 131 are formed by digging out stripe-shaped insulating blocks on the insulating layer 13, and the unfilled portion is the first substrate 11. The first metal layer 12 is disposed on the plating region 101, and the edge region 102 is provided with a first common electrode 121 extending from the display region AA to the non-display region NA, and the first common electrode 121 is electrically connected to the first metal layer 12 of the via hole 131 exposed on the plating region 101, so that the conductive particle 161 contained in the via hole 131 is directly electrically connected to the first common electrode 121. The other side of the conductive particles 161 is electrically connected to the second common electrode 22 through the second alignment film 23 on one side of the color film substrate 2, thereby turning on the liquid crystal display panel.

Third embodiment

Fig. 5 is a schematic structural diagram of a conductive pad of an array substrate according to a third embodiment of the present application.

As shown in fig. 5, a third embodiment of the present application provides a conductive pad 10 of an array substrate 1, which is similar to the conductive pad 10 of the array substrate 1 provided in the first embodiment, and is different in that the shape of the via hole of the conductive pad 10 is different, that is, the via hole 131 is arranged in a V-shaped structure.

Specifically, the via hole 131 includes a first via hole 131a and a second via hole 131b, and the first via hole 131a and the second via hole 131b are symmetrically disposed with respect to a center line of the conductive pad 10 along a second direction, which is perpendicular to the first direction.

In this embodiment, the second direction of the conductive pad 10 is a direction perpendicular to the surrounding direction of the non-display area NA around the display area AA, and when the conductive pad 10 is located in the length direction of the array substrate 1, the first direction is the length direction of the array substrate 1, and the second direction is the width direction of the array substrate 1. When the conductive pads 10 are located in the width direction of the array substrate 1, the first direction is the width direction of the array substrate 1, and the second direction is the length direction of the array substrate 1. That is, the second direction, i.e., the direction in which the array substrate 1 is directed from the display area AA to the non-display area NA.

In preparing the first alignment film 15, the liquid droplets of the first alignment film 15 may be dropped at the center of the conductive pad 10, and then spread along the first via 131a, the second via 131b, the first channel formed between adjacent first vias 131a, and the second channel formed between adjacent second vias 131b, respectively, as shown by the arrow direction in fig. 5, so that the flow speed of the liquid droplets and the spreading uniformity of the liquid droplets may be increased, preventing the liquid droplets of the first alignment film 15 from being blocked and accumulated in the first via 131a and the second via 131 b.

Fourth embodiment

Fig. 6 is a schematic structural diagram of a conductive pad of an array substrate according to a fourth embodiment of the present application.

As shown in fig. 6, a fourth embodiment of the present application proposes a conductive pad 10 of an array substrate 1, which is similar to the conductive pad 10 of the array substrate 1 provided in the third embodiment, except that the edge structure of the conductive pad 10 is different.

As shown in fig. 6, the conductive pad 10 includes a plating region 101 and an edge region 102 located on the outer peripheral side of the plating region 101, wherein the conductive layer 14 is laid on the plating region 101 and the edge region 102, and the conductive layer 14 is not shown in the present embodiment for the convenience of viewing the via hole 131. The first metal layer 12 is laid on the plating region 101 and the edge region 102, and since the first metal layer 12 of the plating region 101 is covered with the insulating layer 13 and the conductive layer 14, only the first common electrode 121 of the edge region 102, that is, the portion filled with diagonal hatching in fig. 6 is exposed. The insulating layer 13 is filled with dot hatching, via holes 131 are formed by digging out stripe-shaped insulating blocks on the insulating layer 13, and the unfilled portion is the first substrate 11. The first metal layer 12 is laid on the plating area 101, and the edge area 102 is provided with a first common electrode 121 extending from the display area AA to the non-display area NA. The via hole 131 includes a first via hole 131a and a second via hole 131b, and the first via hole 131a and the second via hole 131b are symmetrically disposed with respect to a center line of the conductive pad 10 in the second direction.

The first common electrode 121 is electrically connected to the first metal layer 12 of the first and second vias 131a and 131b, respectively, exposed at the plating region 101, so that the conductive particles 161 received in the vias 131 are directly conducted to the first common electrode 121. The other side of the conductive particles 161 is electrically connected to the second common electrode 22 through the second alignment film 23 on one side of the color film substrate 2, thereby turning on the liquid crystal display panel.

Fifth embodiment

Fig. 7 is a schematic structural diagram of a conductive pad of an array substrate according to a fifth embodiment of the present application.

As shown in fig. 7, a fifth embodiment of the present application provides a conductive pad 10 of an array substrate 1, which is similar to the conductive pad 10 of the array substrate 1 provided in the third embodiment, and is different in that the shape of the via hole of the conductive pad 10 is different, that is, the via hole 131 is arranged in a "m" structure.

Specifically, as shown in fig. 7, the via hole 131 includes a first via hole 131a, a second via hole 131b, a third via hole 131c, and a fourth via hole 131d, where the first via hole 131a and the second via hole 131b are symmetrically disposed with respect to a center line of the conductive pad 10 in the second direction, the third via hole 131c and the first via hole 131a are symmetrically disposed with respect to a center line of the conductive pad 10 in the first direction, and the fourth via hole 131d and the second via hole 131b are symmetrically disposed with respect to a center line of the conductive pad 10 in the first direction.

In this embodiment, the first direction of the conductive pad 10 is the enclosing direction of the non-display area NA around the display area AA, and the first direction is perpendicular to the second direction. I.e. the second direction is the direction in which the array substrate 1 is directed from the display area AA to the non-display area NA.

In preparing the first alignment film 15, the droplet of the first alignment film 15 may be dropped at the center of the conductive pad 10, and then the droplet may be spread along the first via 131a, the second via 131b, the third via 131c, the fourth via 131d, the first channel formed between adjacent first vias 131a, the second channel formed between adjacent second vias 131b, the third channel formed between adjacent third vias 131c, and the fourth channel formed between adjacent fourth vias 131d, respectively, as shown by arrow directions in fig. 7, so that the flow speed of the droplet and the spreading uniformity of the droplet may be further accelerated, and the droplet of the first alignment film 15 may be prevented from being blocked and accumulated in the first via 131a and the second via 131 b.

Sixth embodiment

As shown in fig. 8, a sixth embodiment of the present application proposes a conductive pad 10 of an array substrate 1, which is similar to the conductive pad 10 of the array substrate 1 provided in the fifth embodiment, except that the edge structure of the conductive pad 10 is different.

Specifically, the conductive pad 10 includes a plating region 101 and an edge region 102 located on at least one side of the plating region 101. Wherein the conductive layer 14 is laid on the plating area 101 and the edge area 102, the conductive layer 14 is not shown in this embodiment for facilitating the view of the via 131. The first metal layer 12 is laid on the plating region 101 and the edge region 102, and since the first metal layer 12 of the plating region 101 is covered with the insulating layer 13 and the conductive layer 14, only the first common electrode 121 of the edge region 102, that is, the portion filled with diagonal hatching in fig. 4 is exposed. The insulating layer 13 is filled with dot hatching, via holes 131 are formed by digging out stripe-shaped insulating blocks on the insulating layer 13, and the unfilled portion is the first substrate 11. The insulating layer 13 and the conductive layer 14 are located in the plating region 101, and the edge region 102 is provided with a first common electrode 121 extending from the display region AA to the non-display region NA, the first common electrode 121 being electrically connected to the first metal layer 12 exposed by the via hole 131.

The via hole 131 includes a first via hole 131a, a second via hole 131b, a third via hole 131c, and a fourth via hole 131d, where the first via hole 131a and the second via hole 131b are symmetrically disposed with respect to a middle line of the conductive pad 10 along the first direction, the third via hole 131c and the first via hole 131a are symmetrically disposed with respect to a middle line of the conductive pad 10 along the second direction, and the fourth via hole 131d and the second via hole 131b are symmetrically disposed with respect to a middle line of the conductive pad 10 along the second direction.

The first common electrode 121 is electrically connected to the first metal layer 12 of the first, second, third and fourth vias 131a, 131b, 131c and 131d, respectively, exposed at the plating region 101, so that the conductive particles 161 received in the vias 131 are directly conducted to the first common electrode 121. The other side of the conductive particles 161 is electrically connected to the second common electrode 22 through the second alignment film 23 on one side of the color film substrate 2, thereby turning on the liquid crystal display panel.

It can be understood that the technical solution of the array substrate 1 provided In the embodiments of the present application can be widely used for various liquid crystal display panels, such as TN (TWISTED NEMATIC ) display panel, IPS (In-PLANESWI TCHING ) display panel, VA (VERTICALALIGNMENT, vertical alignment) display panel, MVA (Multi-Domain VERTICAL ALIGNMENT ) display panel.

It should be readily understood that the terms "on … …", "above … …" and "above … …" in this disclosure should be interpreted in the broadest sense so that "on … …" means not only "directly on something" but also includes "on something" with intermediate features or layers therebetween, and "above … …" or "above … …" includes not only the meaning "on something" or "above" but also the meaning "above something" or "above" without intermediate features or layers therebetween (i.e., directly on something).

The term "substrate base" as used herein refers to a material to which subsequent layers of material are added. The substrate itself may be patterned. The material added atop the substrate base plate may be patterned or may remain unpatterned. In addition, the substrate base may comprise a wide range of materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate base plate may be made of a non-conductive material (e.g., glass, plastic, or sapphire wafer, etc.).

The term "layer" as used herein may refer to a portion of material that includes regions having a certain thickness. The layer may extend over the entire underlying or overlying structure, or may have a range that is less than the range of the underlying or overlying structure. Further, the layer may be a region of a continuous structure, either homogenous or non-homogenous, having a thickness less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure or between any pair of lateral planes at the top and bottom surfaces. The layers may extend laterally, vertically and/or along a tapered surface. The substrate base may be a layer, may include one or more layers therein, and/or may have one or more layers located thereon, and/or thereunder. The layer may comprise a plurality of layers. For example, the interconnect layer may include one or more conductors and contact layers (within which contacts, interconnect lines, and/or vias are formed) and one or more dielectric layers.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the application.

Claims

1. An array substrate for a liquid crystal display panel, the liquid crystal display panel comprising a display area and a non-display area at the periphery of the display area, characterized in that,

The array substrate is provided with a plurality of conductive pads which are distributed at intervals in the non-display area, each conductive pad comprises a first metal layer, an insulating layer and a conductive layer which are sequentially formed on a first substrate, the first metal layer is in same layer and is electrically connected with a first public electrode positioned in the display area, each insulating layer of each conductive pad is provided with a plurality of through holes so that the conductive layer is electrically connected with the first public electrode, the through holes are arranged in a slit shape, a preset included angle is formed between each through hole and a first direction, and the first direction is the direction of the non-display area surrounding the display area;

The conductive bonding pad comprises a plating layer area and an edge area positioned on at least one side of the plating layer area, the insulating layer and the conductive layer are positioned in the plating layer area, the first metal layer is laid in the plating layer area and the edge area, and one side of the via hole, which faces the edge area, is communicated with the edge area.

2. The array substrate according to claim 1, wherein the value range of the preset included angle α between the via hole and the first direction is: 0. alpha is less than or equal to 90 degrees.

3. The array substrate of claim 1, wherein a spacing between two adjacent vias is S, a width of the via is W, and S/(w+s) is equal to or greater than 30%.

4. The array substrate of claim 3, wherein a spacing S between two adjacent vias is > 5.5 μm;

and/or the width W of the via hole is more than 14.5 μm.

5. The array substrate of claim 1, wherein the via hole comprises a first via hole and a second via hole, the first via hole and the second via hole are symmetrically arranged with respect to a center line of the conductive pad along a second direction, and the second direction is perpendicular to the first direction.

6. The array substrate of claim 5, wherein the via further comprises a third via and a fourth via, the third via and the first via are symmetrically disposed with respect to a centerline of the conductive pad along the first direction, and the fourth via and the second via are symmetrically disposed with respect to a centerline of the conductive pad along the first direction.

7. The array substrate of any one of claims 1 to 6, wherein the conductive pad includes a plating region and an edge region located at least one side of the plating region, the insulating layer and the conductive layer are located at the plating region, and the first common electrode extends from the display region to the edge region of the non-display region and is electrically connected to the first metal layer exposed by the via hole.

8. The array substrate of claim 1, further comprising a first alignment film and a frame adhesive, wherein the first alignment film is located at a side of the conductive layer away from the first substrate, conductive particles are formed in the frame adhesive, the conductive particles are contained in the via holes, one end of the conductive particles is electrically connected with the first common electrode through the first alignment film, and the other end of the conductive particles is electrically connected with the second common electrode through a second alignment film on a color film substrate side of the liquid crystal display panel.

9. A liquid crystal display panel, comprising:

the array substrate of any one of claims 1 to 8;

The color film substrate is arranged opposite to the array substrate;

The liquid crystal layer is arranged between the array substrate and the color film substrate.