CN114371816A - Data storage method and electronic equipment - Google Patents

Data storage method and electronic equipment Download PDF

Info

Publication number
CN114371816A
CN114371816A CN202111525592.5A CN202111525592A CN114371816A CN 114371816 A CN114371816 A CN 114371816A CN 202111525592 A CN202111525592 A CN 202111525592A CN 114371816 A CN114371816 A CN 114371816A
Authority
CN
China
Prior art keywords
data
sector
areas
storing
area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202111525592.5A
Other languages
Chinese (zh)
Inventor
苏祺云
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen Kaadas Intelligent Technology Co Ltd
Original Assignee
Shenzhen Kaadas Intelligent Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shenzhen Kaadas Intelligent Technology Co Ltd filed Critical Shenzhen Kaadas Intelligent Technology Co Ltd
Priority to CN202111525592.5A priority Critical patent/CN114371816A/en
Publication of CN114371816A publication Critical patent/CN114371816A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G06F3/0611—Improving I/O performance in relation to response time
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G06F3/0619—Improving the reliability of storage systems in relation to data integrity, e.g. data losses, bit errors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G06F3/0644—Management of space entities, e.g. partitions, extents, pools
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
    • G06F3/0647—Migration mechanisms
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
    • G06F3/0652—Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

The embodiment of the application provides a data storage method and electronic equipment, wherein the method comprises the following steps: storing first data on a first data block of a first sector, wherein the first sector is divided into a plurality of data areas, the plurality of data areas include a plurality of first data areas and a plurality of second data areas, the first data areas are used for storing data, and the second data areas are used for storing modification data of the data stored on the first data areas; and if the first data is updated, storing the updated data of the first data into the idle second data areas in the plurality of second data areas. By adopting the embodiment of the application, the problems of low data writing efficiency and permanent data loss caused by power failure can be solved.

Description

Data storage method and electronic equipment
Technical Field
The present application relates to the field of data storage, and in particular, to a data storage method and an electronic device.
Background
The high-speed development of the information age makes the requirements of related electronic equipment developed by science and technology on data storage become larger and larger, the functions and the types of products become more and more, and more data need to be stored, and the key for solving the storage problem is to select a proper memory to store data. The general Memory uses two storage media, namely an Electrically Erasable Programmable Read-Only Memory (EEPROM) and a Flash Memory (Flash Memory) to store related information, but the EEPROM has a small capacity, is expensive and has a long service life, cannot solve the capacity problem and cannot meet the storage requirement, the Flash has a large capacity and a low price, and can solve the capacity and cost problems, but the data must be erased before the Flash data is written, usually, the erase is performed by the smallest sector, if the data storage space is smaller than one sector, the erase still needs to be performed by the smallest unit of erase, the erase of the whole sector consumes very much time, the erase service life is low, and the data needs to be Read and backed up before the data is erased, so that the data writing efficiency is very low. In the process of writing data, if the system is powered off just after erasing, the backup read whole sector data can be lost, the write data loses the whole sector, the power failure causes permanent data loss, and the data storage is very unfavorable.
Disclosure of Invention
The embodiment of the application discloses a data storage method and electronic equipment, which can improve the data writing efficiency and the data storage function in case of power failure in a general scene, improve the data storage efficiency and save the data storage cost.
In a first aspect, an embodiment of the present application provides a data storage method, where the method includes:
storing first data on a first data area of a first sector, wherein the first sector is divided into a plurality of data areas, the plurality of data areas include a plurality of first data areas and a plurality of second data areas, the first data areas are used for storing data, and the second data areas are used for storing modification data of the data stored on the first data areas;
and if the first data is updated, storing the updated data of the first data into the idle second data areas in the plurality of second data areas.
In the method, the storage space is divided into a plurality of data areas, so that a large storage space is divided into a plurality of small storage spaces of the data areas, if a data block written in a certain first data area in a plurality of first data areas needs to be modified, the large storage space does not need to be written after being erased integrally, instead, the modified data of the data stored in a certain first data area is written into the free storage positions in a plurality of second data areas, that is, the modified data does not need to erase the whole storage space, does not need to be overwritten, but find the idle data block to write the modified data, so that the data before modification and the modified data are not lost in power failure, which is beneficial to data storage, and the original one-time rewriting of the erasing is changed into the multiple rewriting of the free areas of the plurality of second data areas, so that the storage efficiency is improved.
In an optional aspect of the first aspect, the method further comprises:
if no idle second data area exists in the plurality of second data areas, storing the latest data corresponding to each logical address in the first sector to a second sector;
erasing data on the first sector.
In the method, if no idle second data area exists, the modified latest data corresponding to each logical address in the first sector is written into the second sector, that is, the erasing and writing of the first sector are performed once only by the number of times of rewriting corresponding to the plurality of second data areas, so that the use erasing and writing times of the sectors are reduced, the efficiency of data storage is improved, the service life of the storage device can be prolonged by reducing the erasing and writing times of the storage device due to the limited number of times of erasing and writing of the storage device, and the original sector is erased after another sector is written, so that the loss of power-down data can be avoided, and the efficiency of data storage is improved.
In yet another optional aspect of the first aspect, the storing the latest data corresponding to each logical address in the first sector to the second sector includes:
replacing the data in the first data area with the same logical address in the plurality of first data areas with the data in the second data area which is updated last time with the same logical address in the plurality of second data areas;
storing data in the plurality of first data regions onto a second sector.
In the method, after each power-on, the latest physical address corresponding to the logical address is searched, and the value corresponding to the latest physical address is used as the latest rewriting value to replace the original data of the same logical address in the plurality of first data areas.
In yet another optional aspect of the first aspect, the method is applied to a memory, where the memory includes at least one main sector and at least one spare sector, where the main sector is used to store data and modification data for the data, and the spare sector is used to store updated data migrated on the main sector, and the first sector belongs to the main sector and the second sector belongs to the spare sector.
In the method, a spare sector which does not store any data is added besides the first sector, the purpose is to store the latest data corresponding to the logical addresses in the plurality of first data areas on the second sector, the second sector is used as a free sector to store the latest data of the first sector after being rewritten for a plurality of times, the data which needs to be modified can be written only by originally reading the data of the whole sector and erasing the data of the whole sector, and the data is changed into one-time reading and one-time erasing after the plurality of rewriting of the free areas of the plurality of second data areas, namely, the plurality of rewriting corresponds to one-time erasing and one-time reading, so that the efficiency of data storage is improved.
In yet another optional aspect of the first aspect, the plurality of data areas further include one or more management areas, and the management areas are used for recording the migration times and the logical addresses. It should be noted that the management area includes a sector migration number (ID, or referred to as a sector migration ID), a sector logical address, and the like, and every time a sector migration is performed, the sector migration ID is incremented by 1 (indicating that the logical address of the sector is from the first sector to the second sector), the migration can record the number of times of the sector migration.
In a second aspect, an embodiment of the present application provides an electronic device for data storage, where the electronic device includes a processor and a memory; wherein the memory is configured to store program code, and the processor calls the program code to perform the following operations:
storing first data on a first data area of a first sector, wherein the first sector is divided into a plurality of data areas, the plurality of data areas include a plurality of first data areas and a plurality of second data areas, the first data areas are used for storing data, and the data areas are used for storing modification data of the data stored on the first data areas;
and if the first data is updated, storing the updated data of the first data into the idle second data areas in the plurality of second data areas.
It can be seen that, the storage space is divided into several data areas, so that the large storage space is divided into several small storage spaces, if the data block written in one of the first data areas needs to be modified, the large storage space does not need to be erased and then written in the whole data block, instead, the modified data of the data stored in a certain first data area is written into the free storage positions in a plurality of second data areas, that is, the modified data does not need to erase the whole storage space, does not need to be overwritten, but find the idle data block to write the modified data, so that the data before modification and the modified data are not lost in power failure, which is beneficial to data storage, and the original one-time rewriting of the erasing is changed into the multiple rewriting of the free areas of the plurality of second data areas, so that the storage efficiency is improved.
In yet another optional aspect of the second aspect, the processor is further configured to:
if no idle second data area exists in the plurality of second data areas, storing the latest data corresponding to each logical address in the first sector to a second sector;
erasing data on the first sector.
It can be seen that, if there is no idle second data area, the modified data corresponding to each logical address in the first sector is written into the second sector, that is, the erasing and writing times of the first sector are performed once after the number of times corresponding to the plurality of second data areas is rewritten, so that the number of times of erasing and writing the sectors is reduced, and the efficiency of data storage is improved.
In yet another optional scenario of the second aspect, in storing the latest data corresponding to each logical address in the first sector to the second sector, the processor is specifically configured to:
replacing the data in the first data area with the same logical address in the plurality of first data areas with the data in the second data area which is updated last time with the same logical address in the plurality of second data areas;
storing data in the plurality of first data regions onto a second sector.
It can be seen that after each power-on, the latest physical address corresponding to the logical address is searched, and the value corresponding to the latest physical address is used as the latest rewritten value to replace the original data of the same logical address in the plurality of first data areas.
In yet another alternative of the second aspect, the memory includes at least one main sector and at least one spare sector, where the main sector is used for storing data and storing modified data of the stored data, the spare sector is used as an empty sector without data to wait for data writing, the first sector belongs to the main sector, and the second sector belongs to the spare sector.
It can be seen that, besides the first sector, a spare sector is added which does not store any data, and the purpose is to store the latest data corresponding to the logical addresses in the plurality of first data areas on the second sector, and the second sector is used as a free sector to store the latest data after the first sector is rewritten for a plurality of times.
In a third aspect, an embodiment of the present application provides a computer-readable storage medium, where the computer-readable storage medium is used to store a computer program, and when the computer program is executed by a processor, the computer program implements the first aspect of the present application and a method for storing data of the first aspect.
In a fourth aspect, the present application provides a computer program product, which when run on an electronic device, causes the electronic device to execute the method for storing data of the first aspect of the present application and any one of the first aspect.
In a fifth aspect, an embodiment of the present application provides an electronic device, where the electronic device includes a device or a method for performing the method or the method described in any embodiment of the present application. The electronic device is, for example, a chip.
It should be appreciated that the description of technical features, solutions, benefits, or similar language in this application does not imply that all of the features and advantages may be realized in any single embodiment. Rather, it is to be understood that the description of a feature or advantage is intended to include the specific features, aspects or advantages in at least one embodiment. Therefore, the descriptions of technical features, technical solutions or advantages in the present specification do not necessarily refer to the same embodiment. Furthermore, the technical features, technical solutions and advantages described in the present embodiments may also be combined in any suitable manner. One skilled in the relevant art will recognize that an embodiment may be practiced without one or more of the specific features, aspects, or advantages of a particular embodiment. In other instances, additional features and advantages may be recognized in certain embodiments that may not be present in all embodiments.
Drawings
The drawings used in the embodiments of the present application are described below.
Fig. 1 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure;
FIG. 2 is a flow chart of a method for processing data according to an embodiment of the present disclosure;
fig. 3 is a schematic diagram of a sector division structure provided in an embodiment of the present application;
fig. 4 is an internal structure diagram of an effective data area according to an embodiment of the present application;
fig. 5 is an internal structure diagram of a free data area according to an embodiment of the present application;
fig. 6 is an internal structure diagram of a management area according to an embodiment of the present application;
FIG. 7 is a schematic diagram of a data storage scenario illustrated in the present application;
fig. 8 is a schematic structural diagram of another sector partition according to an embodiment of the present application.
Fig. 9 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be described in detail and clearly with reference to the accompanying drawings. The terminology used in the description of the embodiments herein is for the purpose of describing particular embodiments herein only and is not intended to be limiting of the application.
Referring to fig. 1, fig. 1 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure. The electronic device 10 comprises a processor 101 and a memory 102, wherein the memory 102 stores relevant computer programs or data thereon, and the processor 101 executes the relevant computer programs or processes the relevant data stored on the memory 102. The present application is directed to a method for storing a data storage space in a Memory 102, if the data needs to be modified, an entire block (for example, a sector) of the storage space in the Memory 102 needs to be read out into a Random Access Memory (RAM) buffer, then the entire block of the storage space is erased, and then the data needs to be modified is written into the entire block, where it usually takes 40ms to erase the storage space of a sector, 32ms to write data of a sector, and it takes a lot of time to erase and read out the entire storage space, and each time a data (if it occupies 1 byte), the entire storage space (for example, 1 sector 4096 bytes) needs to be erased, so that the data writing efficiency is very low, and in the process of writing data, if the system is just powered off after erasing, the entire data of the backed-up read sector will be lost, data read after a power loss is lost, resulting in very inefficient data storage.
In order to solve the problems of low data storage efficiency and permanent data loss caused by power failure, the memory 102 of the electronic device 10 is improved by the present application, the storage area of the memory 102 is divided into a plurality of data areas, it should be noted that the storage type of the memory can be various, wherein, in the case of a FLASH memory, the minimum unit of erasing is one sector (4096 bytes), the sector is divided into a plurality of storage areas, for example, when the memory 102 is a FLASH memory, the storage space in the memory 102 is divided into a plurality of data areas, the plurality of data areas include a plurality of first data areas (valid data areas for storing data) and a plurality of second data areas (free data areas for storing modified data of the first data areas) and a management area, the sector is divided into a plurality of storage areas, and one-time erasing is changed from one-time-rewriting to one-time-erasing, if the minimum erasing unit of the other types of memories is also large, the minimum erasing unit can be divided into a plurality of storage areas according to the method, in the method, the erasing times are reduced in a mode of management in a sub-module mode, and the data writing efficiency is improved.
In some embodiments, when the data in the first data area needs to be modified, the processor 102 first reads the modified data into the RAM buffer for data processing, and then writes the modified data buffered in the RAM into the free data area of the second data area, at this time, writing one data (for example, 1 byte) only needs to be modified in the free areas of the plurality of second data areas, and the entire sector (4096 bytes) does not need to be erased, thereby improving the efficiency of data rewriting.
In other embodiments, when there is no free area in the plurality of second data areas, the processor 101 first reads the data of the rewritten first data area and the data of the management area in the first sector to the RAM cache for data processing, the processor 101 then writes the relevant data cached in the RAM into the second sector, and after writing the second sector, the processor then performs a bulk erase on the data stored in the first sector. That is to say, the processor 101 processes and stores the relevant data in the RAM (power failure), and then writes the data into the FLASH memory (power failure does not occur), even in the process of writing data, if the system is powered off in the process of writing the original sector (for example, the first sector) into another sector (the second sector), the data of the original sector still does not cause data loss, if the system is powered off just after erasing, the data of the whole backup read sector cannot be lost, and the data can be stored in case of power failure, so that the reliability of data storage is improved.
Referring to fig. 2, fig. 2 is a flowchart of a data processing method according to an embodiment of the present disclosure. The method may be implemented based on the electronic device 10 shown in fig. 1, and includes, but is not limited to, the following steps;
s201: first data is stored on a first data area of the first sector.
The storage unit of the memory is a sector, the first sector is divided into a plurality of data areas, the plurality of data areas comprise a plurality of first data areas and a plurality of second data areas, and one or more management areas, the first data areas are used for storing data, the data areas are used for storing modification data of the data stored in the first data areas, and the management areas are used for verifying erasing times and logical addresses.
The data storage space is divided into a plurality of first data areas, a plurality of second data areas and one or more management areas, in some embodiments, assuming that the data storage is FLASH data storage, the minimum unit of erasure is 1 sector, and the application is described with reference to the above method:
the FLASH memory has 1 sector of 4096 bytes, and if the size of the data to be rewritten is 28 bytes, the 1 sector can be divided into 128 data areas, and at this time, one data area occupies 32 bytes, and if the size of the data to be rewritten is 52 bytes, the 1 sector can be divided into 64 data areas, and at this time, one data area occupies 64 bytes, that is, the number of the divided areas can be adjusted according to the size of data to be rewritten (first data), and bytes close to the first data storage bytes are selected to divide the number of the data areas, and it should be noted that the number of the divided data areas is the number of the second power of 2. In this embodiment, a division manner of 128 data areas is selected for explanation, and the remaining number of data areas may be used, which is not limited in this application.
As shown in fig. 3, fig. 3 is a schematic view of a sector division structure according to an embodiment of the present application. 1 sector is divided into 128 data areas, one data area is 32 bytes in size, wherein the data areas 0-63 are 64 first data areas, the data areas 64-126 are 63 second data areas, and the data area 127 is 1 management area, wherein the 64 first data areas store valid data, for example, the data area 0 stores a password a, the data area 1 stores a password b, the data area 2 stores a key a, the data area 3 stores a key b, etc., and can also store other data, that is, each first data area can store one type of valid data, if the valid data in one of the plurality of first data areas needs to be rewritten, the rewritten data is written into one of the free sectors in the 63 second data areas through the RAM buffer, which needs to be explained, in this embodiment of the present application, the manner of writing the modified data in the second data area may be to write the modified data in the second data area according to the time sequence of the operation, that is, write 64 and then write 65, and so on, and it should be noted that the manner of writing the modified data may also be to write in any free data area in the second data area (that is, write the modified data if there is a free area), in this embodiment of the present application, the manner of writing in the time sequence may also be to write in any free data area in the second data area, which is not limited in this application, and in this embodiment, the manner of writing in the second data area according to the time sequence is selected for analysis.
In some embodiments, the number of the first data regions and the number of the second data regions of the sector and the number of the management regions are not fixed, and the number of the first data regions may be the remaining number according to the number and kind of the valid data. For example, when the valid data of sector 0 is 10, the number of the first data regions may be 10, and in this case, the number of the second data regions may be 117, and the number of the management regions may be 1, and for example, when the valid data is 80, the number of the first data regions may be 80, and in this case, the number of the second data regions may be 46, and the number of the management regions may be 2, that is, the number of the first data regions and the second data regions and the number of the management regions are not determined, and may be adjusted according to the actual situation of the type and the number of the valid data.
As shown in fig. 4, fig. 4 is an internal structure diagram of an effective data area according to an embodiment of the present application. Each first data area comprises 32 bytes, wherein 30 bytes are valid data fields for storing valid data, a block ground value is 1 byte for storing a logical address of the first data area, and a CHECK is 1 byte for storing a CHECK value after checking the valid data fields and the block ground value (the CHECK value is obtained by relevant calculation of the CHECK). The number of specific function partitions of the bytes performed on each first data area is not limited, for example, the effective data area may be 28 bytes, the block area value may be 2 bytes, the CHECK may be 2 bytes, and the like, and may also be a remaining number of partition modes.
As shown in fig. 5, fig. 5 is an internal structure diagram of a free data area according to an embodiment of the present application. A second data area includes 32 bytes, wherein the valid data area is 30 bytes for storing valid data (modified data of the first data area), the block size value is 1 byte for storing the logical address of the first data area, and the CHECK is 1 byte for storing a CHECK value after checking the valid data area and the block size value (the CHECK value is calculated by the CHECK). The number of the specific function division of the bytes performed on each second data area is not limited, and is not described in detail. In the embodiment of the present application, the division manner shown in fig. 5 is selected for analysis.
As shown in fig. 6, fig. 6 is an internal structure diagram of a management area shown in an embodiment of the present application, where one management area includes 32 bytes, a logical address of a sector is 1 byte and is used to store a logical address corresponding to the sector, a sector migration ID is 4 bytes and is used to record the number of times of migration, and 1 is added to the sector migration ID every time a sector migrates between sectors. The reservation module is 25 bytes and can be used for storing the rest of the extended functions, such as storing the reservation factor and the like. The CHECK occupies 2 bytes, and is used to store a CHECK value (the CHECK value is obtained by the correlation calculation of the CHECK) after the sector logical address, the sector migration ID and the reservation module are checked, and the number of specific function partitions of the bytes performed on the management area is not limited, which is not described herein again. In the embodiment of the present application, the division manner shown in fig. 6 is selected for analysis.
If there are 512 logical spaces corresponding to related data to be stored, the remaining number of logical spaces may be used, and the present application is not limited thereto, and the description will be given in this embodiment with the number of the logical spaces being 512.
As shown in fig. 7, fig. 7 is a schematic diagram of a data storage scenario shown in the present application. In this case, the present embodiment will be described when there are 512 logical spaces in which data are stored, and 1 sector is divided into 128 data areas, 64 first data areas, 63 second data areas, and 1 management area:
the 512 logical spaces are correspondingly stored in 8 sectors, 1 sector is added as an idle sector, eight sectors from the sector 0 to the sector 7 are called as a first sector and are used as a main sector to store data and modified data aiming at the first data area to store the data, and the sector 8 is used as a second sector and is used as a spare sector to store updated data migrated on the main sector. In detail, the logical spaces 0-63 are stored in the first data areas 0-63 of the sector 0, and the logical spaces 64-127 are stored in the first data areas 128-191 of the sector 1, and so on, which are not described again. The ninth sector, that is, the sector 8, is a free sector, the first data areas of the sector 8 do not have any data, the second data areas do not have any data overwriting data, and the management area does not store any data, that is, all of the 32 bytes of each data area of the sector 8 are 1, that is, 64F (16 th system).
It should be noted that the FLASH memory can only change 1 to 0, but cannot change 0 to 1, and the erasing process is a process of changing all bytes in the data storage area to 1, that is, if the sector is an idle sector, each bit of 4096 bytes in the sector is 1.
As shown in fig. 8, fig. 8 shows a schematic structural diagram of another sector division. If the data area 0 of the sector 0 stores the password a, the data area 1 stores the password b, the data area 2 stores the key a, the data area 3 stores the key b, and the data area 4 stores the fingerprint a, the embodiment of the present application will be described with reference to the storage content of the data:
in some embodiments, the modified data stored in the second data area may be sequentially stored in the order of the modified data (e.g., 64 followed by 65, and so on) and, during the process of storing the modified data in the first data area into the free second data area, the processor 101 shown in fig. 1 is required to read the modified data into the RAM buffer and then write the modified data in the RAM buffer into the second data area. For example, if the stored password a of the sector 0 is modified, the remaining part of the stored password a to be modified and the newly modified part are read into the RAM memory buffer, and the modified data of the stored password a is stored into a free area of the second plurality of data areas (which may be stored in the order in which the stored data are modified), specifically, the data area 0 of the sector 0 stores the data area of the stored password a having a value of 30 bytes of ABFC (hexadecimal) +28 bytes of the valid data area, which needs to be modified into AAAF (hexadecimal) +28 bytes of the remaining data, the 28 bytes of the remaining part of the stored password a to be modified are extracted into the RAM buffer, and the part of the AAAF (hexadecimal) to be modified and written is combined with the remaining 28 bytes to become AAAF (hexadecimal) +28 bytes of the remaining data, and writing the modified data into any free area of the plurality of second data areas.
In some embodiments, the CHECK value of 1 byte in the data area 0 is obtained by calculation, specifically, a correlation calculation (such as an exclusive or operation or a summation operation) is performed on the valid data field of 30 bytes and the block location value of 1 byte in the RAM buffer, the obtained data is the data stored in the CHECK, the calculation is performed in the RAM buffer, and then the valid data field of 30 bytes and the block location value of 1 byte and the CHECK value obtained by calculation are written into the data area 0 together.
In some embodiments, the modified data of the first data stored in the first data area is written into the second data area, and the logical address of the first data area is not changed. Every time the power is on, the index table in the RAM corresponds the physical address and the logical address, and the fixed RAM storage space occupied by the index table is 1024 bytes. Specifically, as shown in fig. 8, after the modified data in the data area 0 is written into the second data area 64, the block values of the data area 0 and the data area 64 are not changed, that is, the logical addresses are consistent, but only the physical addresses are changed (from the data area 0 to the data area 64), when the power is turned on, the index table in the RAM can find out the corresponding different physical addresses of the same logical address, and before and after the data is rewritten, the logical addresses are consistent, so that the related data with the same logical address can be better identified, and the data storage efficiency is improved.
In some embodiments, the modified data of the first data stored in the first data area is written into the second data area, the first data area is marked as an invalid module, and the second data area in which the modified data is stored is marked as a valid module. For example, in the case of keeping power off and damage free, as shown in fig. 8, the modified data of the data area 0 is written into the data area 64 of the second data area, at this time, the data area 0 is marked as an invalid module, the data area 64 is marked as a valid module for checking the data correctly, specifically, the modified data has a new CHECK value calculated according to the modified data in the RAM cache, the modified data, the block ground value and the new CHECK value are simultaneously stored into the data area 64, after the modified data, the block ground value and the new CHECK value are written into the data area 64, at this time, the CHECK is performed on the data area 64, the calculated value is consistent with the value calculated in the cache, the CHECK is successful, the data area 64 is marked as a valid module, and the data area 0 is marked as an invalid module.
If the data area 0 is rewritten again and written into the free second data area, the rewritten data is still the valid block with correct verification, but the rewritten valid data with correct verification belongs to the latest valid data compared with the last rewritten valid data with correct verification, that is, the valid block refers to the block with correct writing, and if the writing is incorrect, the block is called the invalid block.
It should be noted that, in this embodiment, in the process of marking the invalid module and the valid module, the mark does not occupy the storage space in 32 bytes of each data area, that is, in this embodiment, when the sequence of storing the modified data in the second data area can be sequentially stored according to the time sequence of the modified data (for example, 64 is stored in the second data area and 65 is stored in the second data area, and so on), in the process of traversing from bottom to top by powering on the RAM each time, the processor selects the latest physical address corresponding to the data area of the same logical address as the modified data for replacing the original first data area, and then the latest modified data is the latest and valid modified data compared with the modified data of the remaining same logical address, that is, in this embodiment, the valid and invalid modules do not occupy the storage space of each data area by the mark, instead, the latest modified data is defaulted to the latest "valid" data by each power up of the RAM going from bottom to top.
In some embodiments, if the modified data is written in any free data area in the second data area (i.e. if there is a free area, the modified data is written), the sequence is a random sequence, and if there is no free data area in the second data area, i.e. the migration sector is performed, then the latest modified data cannot be defaulted to be the latest "valid" data according to the traversal of the RAM from bottom to top, that is, a valid-invalid flag function needs to be added to the 25-byte retention module in the management area, a few bytes (e.g. 1 byte) are taken out of 32 bytes in each of the first data area or the second data area, and a valid-invalid module function needs to be added, and if the modified data is written in any free data area in the second data area and the sequence is a random sequence, the valid and invalid modules need to be marked, and the marking process needs to occupy byte storage space in the modules, namely, data at the latest time is marked as valid, original data of the same logic address with the latest data and other modified data except the latest data are marked as invalid. It should be noted that, by adding valid and invalid flag storage spaces in corresponding management areas or data areas, a function of identifying the latest data when modified data is in a random sequence is achieved, and a recording time module (for example, selecting the latest time, the time module occupying byte storage space in an area) and a recording modification number module (for example, selecting the data area with the largest modification number as the latest data area, and the modification number module occupying byte storage space in the area) may be added, that is, the flag manner of identifying the latest data area may be multiple, which is not limited in the embodiment of the present application.
It should be noted that, in the present embodiment, it is selected that the modification orders in the second data area are sequentially stored according to a time sequence, so that the above method of occupying a storage space to "label" the latest data is not needed, and the latest modification data is defaulted to be the latest "valid" data by a way of traversing the RAM from bottom to top every time the RAM is powered on.
In some embodiments, since the RAM buffer may lose data when power is lost, if half of the modified data stored in the RAM buffer for data area 0, the block location value, and the CHECK value are written into data area 64, when the system is powered down and powered up again, the RAM buffer will receive the modified data value and the corresponding calculated CHECK value again, only half of the modified data will be written in the data area 64, the CHECK value calculated from the modified data written in half of the data area 64 is not identical to the CHECK value calculated from the complete modified data in the RAM, that is, the CHECK value calculation result is performed on the data in the data area 64, inconsistent with the CHECK value in data region 64, at which point data region 64 fails the verification, then data area 0 is still a valid module and data area 64 is an invalid module for which the check failed. It should be noted that, in this example, in the case of power failure after half of the data is written, half of the modified data is written in the data area 64, and power-up again may select to continue to write the remaining data, or the data area 64 may be discarded, and the free data area is reselected for writing, which is not limited in this embodiment of the present application.
S202: and if the first data is updated, storing the updated data of the first data into the idle second data areas in the plurality of second data areas.
In some embodiments, if the same data region is modified multiple times, the latest modified data region is selected as replacement data at the time of sector migration. For example, as shown in fig. 8, after the password a stored in the data area 0 of the first data area is modified once, the data of the password a after modification is stored in the data area 64, at this time, the data of the password a for the first modification stored in the data area 64 is valid data for verifying correctness, after the password a stored in the data area 0 of the first data area is modified twice, the data of the password a after modification is stored in the data area 65, at this time, the data of the password a for the second modification stored in the data area 65 is also valid data for verifying correctness. After the key a stored in the data area 2 of the first data area is modified once, the data of the modified key a is stored in the data area 66, at this time, the data of the first modified key a stored in the data area 66 is valid data for checking correctness, after the key a stored in the data area 2 of the first data area is modified twice, the data of the modified key a is stored in the data area 67, and at this time, the data of the second modified key a stored in the data area 67 is also valid data for checking correctness.
In some embodiments, each time the processor is powered on, the processor traverses the data of the plurality of second data areas from bottom to top in the RAM cache, and traverses an entire sector, which requires that 4096 bytes of the RAM are fixedly occupied, and the logical address corresponds to the physical address according to the fixed 1024-byte index table in the RAM, that is, the latest physical address of the same logical address is found, valid data that is correctly verified for the cipher a closest to the traversal time (i.e., the latest modification) is used as the data of the replacement data area 0, for example, the data area 65 is used as the latest data of the replacement data area 0, and valid data that is correctly verified for the cipher a closest to the traversal time (i.e., the latest modification) is also used as the data of the replacement data area 2, for example, the data area 67 is used as the latest data of the replacement data area 2. It should be noted that, in this embodiment, when the writing mode of writing in the second data region is writing according to a time sequence, the traversal mode is from bottom to top, and if the writing mode is a random writing mode, the traversal mode may be from top to bottom, also may be from bottom to top, and also may be the remaining traversal modes.
It should be noted that, in the process that the processor traverses data of the plurality of second data regions from bottom to top in the RAM cache, the processor may identify the type of modified data according to the logical address stored in the block location value, traverse the latest modified data of the same logical address as that of the first data region in the second data region according to the block location value, and use the data as replacement data of the first data region. For example, the logical address of the password a is 00 (hexadecimal), the logical address of the key a is 02 (hexadecimal), the logical addresses of the data area 64 and the data area 65 are both 00 (hexadecimal), the logical addresses of the data area 66 and the data area 67 are both 02 (hexadecimal), therefore, the system can identify the modified data of the same data type according to the same logical address in the block region value, and traverse the latest data of the modified data of the same data from bottom to top on the basis of the same data type, for example, the latest modification data of the password a is on the data area 65, the latest modification data of the key a is on the data area 67, the data of the data area 65 is the latest modification data regarding the password a replacing the data area 0, and the data of the data area 67 is the latest modification data regarding the key a replacing the data area 2.
In some embodiments, during the sector migration, the latest modified data area is selected as the replacement data during the sector migration, that is, when there is no free data area in the second data areas of the first sector, the processor selects the latest modified data area as the replacement data during the sector migration, and during the sector migration, the data of the first sector also needs to be read into the RAM cache before being written into the second sector. As shown in fig. 8, modified latest data and self-unmodified data having the same logical address in the 0-63 data area (for example, the unmodified data area 4 is not replaced) and the value of the management area are stored in the RAM buffer, the sector migration ID value of the management area is added by 1 in the RAM, and the data replaced in the RAM is written into the free sector 8 as shown in fig. 7, at this time, 64 data areas of 896 and 959 in the sector 8 store the modified latest data and self-unmodified data having the same logical address in the first data area, and the data area 1023 stores the management area.
In some embodiments, the sector migration ID is incremented by 1 every time a sector is migrated. For example, in the process of writing the sector 0 data into the sector 8, the management area of the data area 1023 of the sector 8 is added with 1 compared to the ID value of the management area in the data area 127 of the sector 0, that is, if the sector migration ID of the sector 0 is 0 (hexadecimal), the sector migration ID of the sector 8 is 1. Under the condition of no power failure, after the latest modified data of a plurality of first data areas in the sector 0 and the data of the management area are written into the sector 8 through the RAM buffer, the processor starts to erase all the data in the sector 0, all 4096 bytes included in the sector 0 are reset to be 1, and the sector migration ID occupying 4 bytes is also in an all-1 state, namely FFFF (16-system), namely, the sector 0 is an idle sector at this time, and the sector 8 is a non-idle sector in which the data is stored.
It should be noted that, if there is no free sector in the second data area of the sector 8, at this time, if the sector 8 is migrated to the free sector 7, at this time, the processor selects the latest modified data area as the replacement data during sector migration, stores the modified latest data (for example, the data area 963 replacing data area 959) having the same logical address as the first data area 896 and 959, the unmodified data (for example, the unmodified data area 900 is not replaced) and the value of the management area in the RAM buffer, adds 1 to the sector migration ID value of the management area in the RAM, writes the modified data in the RAM into the free sector 7 as shown in fig. 7, at this time, the sector migration ID of the sector 7 is 02 (hexadecimal), that is, 2 times, and, in the case of no power loss, after the above-mentioned data of the sector 8 is written into the sector 7, the processor erases the sector 8, at this time, all 4096 bytes included in the sector 8 are reset to 1, and the sector migration ID occupying 4 bytes is also in an all-1 state, i.e., ffffff (16-ary), that is, at this time, the sector 8 is an idle sector, and the sector 7 is a non-idle sector in which data is stored.
In some embodiments, if two sectors of the same logical address are found and both are verified correctly, the sector with the smaller sector migration ID value is marked as a free sector (erased). For example, if the processor does not have time to erase the sector 0 after the latest modified data corresponding to the same logical address of the sector 0, the unmodified data and the management block are all written into the sector 8, and the system is powered down at this time, then the system will have two identical sectors storing the same logical address when powered on again, but the sector migration ID of the sector 8 is 1 greater than the sector migration ID of the sector 0 at this time, so the processor selects the sector with a small sector migration ID (i.e., the sector 0) as a free sector to erase the free sector, and can identify the sector to be erased when powered on once, thereby greatly improving the efficiency of data storage.
The method of the embodiments of the present application is described above, and the apparatus of the embodiments of the present application is described next.
Fig. 9 is a schematic structural diagram of an electronic device according to an embodiment of the present application. The electronic device 20 comprises a storage unit 901 for storing program code, which is called by the processor for performing the following operations, and an update unit 902:
a storage unit 901, which stores first data in a first data block region of a first sector, wherein the first sector is divided into a plurality of data regions, the plurality of data regions include a plurality of first data regions and a plurality of second data regions, the first data region is used for storing data, the data regions are used for storing modified data of the data stored in the first data region, and one or more management regions are used for verifying erasure number and logical address;
if the first data has an update, the updating unit 902 stores the updated first data in a spare second data area of the plurality of second data areas.
It can be seen that, the storage space is divided into several data areas, so that the large storage space is divided into several small storage spaces, if the data block written in one of the first data areas needs to be modified, the large storage space does not need to be erased and then written in the whole data block, instead, the modified data of the data stored in a certain first data area is written into the free storage positions in a plurality of second data areas, that is, the modified data does not need to erase the whole storage space, does not need to be overwritten, but find the idle data block to write the modified data, so that the data before modification and the modified data are not lost in power failure, which is beneficial to data storage, and the original one-time rewriting of the erasing is changed into the multiple rewriting of the free areas of the plurality of second data areas, so that the storage efficiency is improved.
In one possible implementation form of the method,
if no idle second data area exists in the plurality of second data areas, storing the latest data corresponding to each logical address in the first sector to a second sector;
erasing data on the first sector.
It can be seen that, if there is no idle second data area, the modified latest data corresponding to each logical address in the first sector is written into the second sector, that is, the erasing and writing times of the first sector are performed for the number of times corresponding to the plurality of second data areas, so that the number of erasing and writing times of the sectors is reduced, and the efficiency of data storage is improved.
In a possible implementation manner, in terms of storing the latest data corresponding to each logical address in the first sector onto the second sector, the updating unit 902 is specifically configured to:
replacing the data in the first data area with the same logical address in the plurality of first data areas with the data in the second data area which is updated last time with the same logical address in the plurality of second data areas;
storing data in the plurality of first data regions onto a second sector.
It can be seen that after each power-on, the latest physical address corresponding to the logical address is searched, and the value corresponding to the latest physical address is used as the latest rewritten value to replace the original data of the same logical address in the plurality of first data areas.
In a possible implementation manner, the memory includes at least one main sector and at least one spare sector, where the main sector is used to store data and to store modified data of the stored data, the spare sector is used as an empty sector without data to wait for data writing, the first sector belongs to the main sector, and the second sector belongs to the spare sector.
It can be seen that, besides the first sector, a spare sector is added which does not store any data, and the purpose is to store the latest data corresponding to the logical addresses in the plurality of first data areas on the second sector, and the second sector is used as a free sector to store the latest data after the first sector is rewritten for a plurality of times.
An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, and when the computer program is executed on a processor, the computer program implements the method flow shown in fig. 2.
An embodiment of the present invention further provides a computer program product, which when running on a processor, implements the method flow shown in fig. 2.
In summary, by implementing the embodiments of the present application, the storage space is divided into a plurality of data areas, the large storage space is divided into a plurality of small storage spaces of the data areas, if the data block written in one of the first data areas needs to be modified, the large storage space does not need to be written after being erased integrally, instead, the modified data of the data stored on a certain first data area is written to free storage locations in a plurality of second data areas, that is to say without overwriting, but the spare data block is searched for writing the modified data, the original once-rewriting is changed into the multiple-rewriting in the spare area of the plurality of second data areas, the storage efficiency is improved, and the original sector is erased after the other sector is written, so that the power failure data can be prevented from being lost, and the data storage efficiency is improved.
One of ordinary skill in the art will appreciate that all or part of the processes in the methods of the above embodiments can be implemented by hardware associated with a computer program that can be stored in a computer-readable storage medium, and when executed, can include the processes of the above method embodiments. And the aforementioned storage medium includes: various media that can store computer program codes, such as a read-only memory ROM or a random access memory RAM, a magnetic disk, or an optical disk.

Claims (10)

1. A method of storing data, comprising:
storing first data on a first data area of a first sector, wherein the first sector is divided into a plurality of data areas, the plurality of data areas include a plurality of first data areas and a plurality of second data areas, the first data areas are used for storing data, and the second data areas are used for storing modification data of the data stored on the first data areas;
and if the first data is updated, storing the updated data of the first data into the idle second data areas in the plurality of second data areas.
2. The method of claim 1, further comprising:
if no idle second data area exists in the plurality of second data areas, storing the latest data corresponding to each logical address in the first sector to a second sector;
erasing data on the first sector.
3. The method of claim 2, wherein storing the latest data corresponding to each logical address in the first sector onto a second sector comprises:
replacing the data in the first data area with the same logical address in the plurality of first data areas with the data in the second data area which is updated last time with the same logical address in the plurality of second data areas;
storing data in the plurality of first data regions onto a second sector.
4. The method according to any one of claims 1 to 3, wherein the method is applied to a memory, the memory comprising at least one main sector and at least one spare sector, wherein the main sector is used for storing data and modification data for the data, the spare sector is used for storing updated data migrated on the main sector, the first sector belongs to the main sector, and the second sector belongs to the spare sector.
5. The method according to any one of claims 1 to 3, wherein the plurality of data areas further include one or more management areas for recording the number of migrations and the logical address.
6. An electronic device for data storage, the electronic device comprising a processor and a memory; wherein the memory is configured to store program code, and the processor calls the program code to perform the following operations:
storing first data on a first data area of a first sector, wherein the first sector is divided into a plurality of data areas, the plurality of data areas include a plurality of first data areas and a plurality of second data areas, the first data areas are used for storing data, and the data areas are used for storing modification data of the data stored on the first data areas;
and if the first data is updated, storing the updated data of the first data into the idle second data areas in the plurality of second data areas.
7. The electronic device of claim 6, wherein the processor is further configured to:
if no idle second data area exists in the plurality of second data areas, storing the latest data corresponding to each logical address in the first sector to a second sector;
erasing data on the first sector.
8. The electronic device of claim 7, wherein, in storing the latest data corresponding to each logical address in the first sector onto the second sector, the processor is specifically configured to:
replacing the data in the first data area with the same logical address in the plurality of first data areas with the data in the second data area which is updated last time with the same logical address in the plurality of second data areas;
storing data in the plurality of first data regions onto a second sector.
9. The electronic device according to any of claims 6-8, wherein the memory comprises at least one main sector and at least one spare sector, wherein the main sector is used for storing data and storing modification data of the stored data, the spare sector is used as an empty data-free sector waiting for data writing, the first sector belongs to the main sector, and the second sector belongs to the spare sector.
10. A computer-readable storage medium, characterized in that the computer-readable storage medium is used to store a computer program which, when executed by a processor, implements the method of any one of claims 1-5.
CN202111525592.5A 2021-12-14 2021-12-14 Data storage method and electronic equipment Pending CN114371816A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111525592.5A CN114371816A (en) 2021-12-14 2021-12-14 Data storage method and electronic equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111525592.5A CN114371816A (en) 2021-12-14 2021-12-14 Data storage method and electronic equipment

Publications (1)

Publication Number Publication Date
CN114371816A true CN114371816A (en) 2022-04-19

Family

ID=81140185

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111525592.5A Pending CN114371816A (en) 2021-12-14 2021-12-14 Data storage method and electronic equipment

Country Status (1)

Country Link
CN (1) CN114371816A (en)

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07295763A (en) * 1994-04-22 1995-11-10 Internatl Business Mach Corp <Ibm> Disk, array device and method of storing data
JP2001075744A (en) * 1999-06-30 2001-03-23 Quantum Corp Method and device for driving data storage system stored with data in data storage area and stored with redundant information for applying error protection to data in redundant sector inside redundant storage area
US20060031657A1 (en) * 2002-11-27 2006-02-09 Fujitsu Limited Storage control device having restoration function to initial status, control method of storage device, and program
JP2009217293A (en) * 2008-03-06 2009-09-24 Seiko Epson Corp Nonvolatile memory controller, printer and nonvolatile memory control method
JP5982025B1 (en) * 2015-02-27 2016-08-31 京セラドキュメントソリューションズ株式会社 Information processing apparatus and memory management program
CN106293532A (en) * 2016-08-10 2017-01-04 广东佳禾声学科技有限公司 A kind of Flash data storage method
US20170192715A1 (en) * 2015-12-30 2017-07-06 Thomson Licensing Method and device for saving data
US20170206006A1 (en) * 2016-01-20 2017-07-20 EpoStar Electronics Corp. Memory management method, memory storage device and memory control circuit unit
CN109508255A (en) * 2018-07-26 2019-03-22 郑州云海信息技术有限公司 A kind of method and device of data processing

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07295763A (en) * 1994-04-22 1995-11-10 Internatl Business Mach Corp <Ibm> Disk, array device and method of storing data
JP2001075744A (en) * 1999-06-30 2001-03-23 Quantum Corp Method and device for driving data storage system stored with data in data storage area and stored with redundant information for applying error protection to data in redundant sector inside redundant storage area
US20060031657A1 (en) * 2002-11-27 2006-02-09 Fujitsu Limited Storage control device having restoration function to initial status, control method of storage device, and program
JP2009217293A (en) * 2008-03-06 2009-09-24 Seiko Epson Corp Nonvolatile memory controller, printer and nonvolatile memory control method
JP5982025B1 (en) * 2015-02-27 2016-08-31 京セラドキュメントソリューションズ株式会社 Information processing apparatus and memory management program
US20170192715A1 (en) * 2015-12-30 2017-07-06 Thomson Licensing Method and device for saving data
US20170206006A1 (en) * 2016-01-20 2017-07-20 EpoStar Electronics Corp. Memory management method, memory storage device and memory control circuit unit
CN106293532A (en) * 2016-08-10 2017-01-04 广东佳禾声学科技有限公司 A kind of Flash data storage method
CN109508255A (en) * 2018-07-26 2019-03-22 郑州云海信息技术有限公司 A kind of method and device of data processing

Similar Documents

Publication Publication Date Title
US6081878A (en) Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices
US6757800B1 (en) Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices
US8078797B2 (en) Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices
KR101613678B1 (en) Recovery for non-volatile memory after power loss
US6381176B1 (en) Method of driving remapping in flash memory and flash memory architecture suitable therefor
US7480760B2 (en) Rotational use of memory to minimize write cycles
US20020085433A1 (en) Data management system and data management method
EP0615184A2 (en) Nonvolatile memory
JPH08235028A (en) Data management method for flash memory and data processor using the data management method
CN112596668A (en) Bad block processing method and system for memory
US20090164869A1 (en) Memory architecture and configuration method thereof
EP2264602A1 (en) Memory device for managing the recovery of a non volatile memory
KR100692982B1 (en) NAND type flash memory for recording bad block information
CN114371816A (en) Data storage method and electronic equipment
JP2003036209A (en) Nonvolatile memory and data rewriting method thereof
CN110633056B (en) Page management method and storage device of Flash chip at operating system level
CN113918485A (en) Method, device, equipment and storage medium for preventing flash memory data from being lost
JPH1031611A (en) File system for nonvolatile memory storage medium
CN111949198A (en) Bad block management method and device and storage equipment
CN115373607A (en) Data storage method and device
KR19990012215A (en) Flash memory
CN114385084A (en) Bad block table inheritance method and storage device thereof
CN115469802A (en) Data storage device
CN115981560A (en) High-reliability file system design method based on NAND flash
JPH01107400A (en) Setting method for switch system by eeprom

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination