CN114361000B - Semiconductor process chamber and semiconductor process equipment - Google Patents
Semiconductor process chamber and semiconductor process equipment Download PDFInfo
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- CN114361000B CN114361000B CN202210003575.3A CN202210003575A CN114361000B CN 114361000 B CN114361000 B CN 114361000B CN 202210003575 A CN202210003575 A CN 202210003575A CN 114361000 B CN114361000 B CN 114361000B
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Abstract
The invention provides a semiconductor process chamber, which comprises a cavity, a lower electrode assembly, a base and a lining assembly, wherein the base and the lining assembly are arranged in the cavity, the base comprises a chuck, the lining assembly is arranged around the base, the lower electrode assembly is used for providing radio frequency for the chuck, the lining assembly comprises an upper lining, a lower lining and an isolation structure, the top of the upper lining is electrically connected with the top wall of the cavity, the bottom of the upper lining is electrically connected with the top of the lower lining through the isolation structure, and the bottom of the lower lining is electrically connected with the bottom of the cavity. In the invention, the lining component is of a split design, a capacitance structure is formed between the upper lining and the lower lining, so that a capacitance exists on a path of the plasma sheath layer connected with the cavity through the lining component, and the ratio between the power participating in plasma ionization and the power generating bias voltage in the power of the lower electrode can be changed by adjusting the capacitance, thereby realizing the improvement of the self bias voltage of the lower electrode. The invention also provides semiconductor process equipment.
Description
Technical Field
The present invention relates to the field of semiconductor processing equipment, and in particular, to a semiconductor processing chamber and a semiconductor processing apparatus including the same.
Background
The patterning sapphire Substrate (PATTERNED SAPPHIRE Substrate, PSS) etching process refers to a process of growing a mask for dry etching on a sapphire Substrate, etching a pattern on the mask by using a photolithography process, etching sapphire by using a reactive coupling plasma (Inductively Coup Plasma, ICP) etching technique and removing the mask, and then growing a gallium nitride (GaN) material thereon, so that the longitudinal epitaxy of the gallium nitride material is changed into lateral epitaxy.
On one hand, the dislocation density of the gallium nitride epitaxial material can be effectively reduced, so that the non-radiative recombination of an active region is reduced, the reverse leakage current is reduced, and the service life of a light-emitting diode (LED) is prolonged; on the other hand, the light emitted by the active region is scattered for multiple times through the interface of the gallium nitride and the sapphire substrate, so that the emergence angle of total reflection light can be changed, the emergence probability of light of the flip LED from the sapphire substrate is increased, and the light extraction efficiency is improved. With the development of the process technology in the field of light emitting diodes and the rapid growth of the whole light emitting diode industry, the research on patterned sapphire substrates of gallium nitride-based light emitting diode devices is also gradually increasing. Various manufacturers now adopt patterned sapphire substrate technology in order to improve the light extraction efficiency of the light emitting diode device. The patterned sapphire substrate has a plurality of patterns, and a pattern similar to a cone is commonly used at present, wherein the pattern period is about 3 mu m and the height is about 1.5 mu m.
The patterned sapphire substrate series etching machine consists of a transmission system module, a process system module, a radio frequency system module and the like. The patterned sapphire substrate etching process uses an aluminum (Al) tray, a quartz cover plate is covered on the tray, and the size of the tray is 380mm. The etching depth of the patterned sapphire substrate etching process is deeper, the etching rate is slower, and the etching time is longer (10-30 min), so that a 13.56MHz radio frequency power source is usually adopted as an upper electrode of a radio frequency system module and is used for generating high-density plasma to excite particles with more ion forms; the lower electrode adopts a 2MHz radio frequency power source to generate higher radio frequency self-bias voltage on a bias (bias) electrode (namely on a Chuck), and the radio frequency self-bias voltage acts on ion acceleration to enable the ions to have higher kinetic energy and higher bombardment capacity.
However, in the actual process mass production process, the power of the 2MHz power of the lower electrode on the chuck is often represented as a state of large current and small voltage, which results in relatively low 2MHz rf self-bias voltage on the surface of the chuck, and further results in low ion energy and poor bombardment capability, so that adhesion occurs at the bottom of the Wafer (Wafer) edge, and the Wafer edge area is not available.
Therefore, how to provide a semiconductor process chamber capable of improving the self-bias of the bottom electrode is a technical problem to be solved in the art.
Disclosure of Invention
The present invention is directed to a semiconductor process chamber and semiconductor process apparatus that enables adjustment of a bottom electrode self-bias voltage.
To achieve the above object, as one aspect of the present invention, there is provided a semiconductor process chamber including a chamber body, a susceptor, a lower electrode assembly, and a liner assembly, the susceptor and the liner assembly being disposed in the chamber body, the susceptor including a chuck having a carrying surface for carrying a wafer, the liner assembly being disposed around the susceptor, the lower electrode assembly being for providing radio frequency to the chuck, the liner assembly including an upper liner, a lower liner, and an isolation structure, a top of the upper liner being electrically connected to a top wall of the chamber body, a bottom of the upper liner being electrically connected to a top of the lower liner through the isolation structure, and a bottom of the lower liner being electrically connected to a bottom of the chamber body.
Optionally, the upper liner comprises a guide plate and a connecting cylinder, the guide plate is arranged at the bottom of the connecting cylinder, the guide plate is arranged on the outer side of the base in a surrounding mode, the guide plate is lower than the bearing surface and is arranged in parallel with the bearing surface, and the top of the connecting cylinder is connected with the top of the cavity;
the lower lining is cylindrical, the lower lining surrounds the base, and the isolation structure is located between the lower lining and the guide plate.
Optionally, the base further includes an edge insulating ring and a bottom insulating ring, the bottom insulating ring is disposed at the bottom of the chuck, and the edge insulating ring is disposed at the outer side of the chuck and is disposed on the bottom insulating ring;
The isolation structure is located between the top surface and the bottom surface of the edge insulating ring at the axial position.
Optionally, the isolation structure includes a dielectric isolation ring detachably disposed between the baffle and the lower liner.
Optionally, a connecting ring is arranged at the top of the lower liner, and a plurality of mounting holes are correspondingly arranged on the guide plate, the medium isolation ring and the connecting ring along the circumferential direction;
the isolation structure further comprises a plurality of fasteners and a plurality of isolation sleeves, the isolation sleeves respectively penetrate through the corresponding mounting holes in sequence, the fasteners penetrate through the isolation sleeves in a one-to-one correspondence mode, and the guide plate, the medium isolation ring and the connecting ring are fixed.
Optionally, the dielectric spacer ring comprises: at least one of quartz, ceramic, polytetrafluoroethylene and epoxy resin.
Optionally, an axial gap is provided between the baffle and the lower liner, the axial gap forming the isolation structure.
Optionally, the semiconductor process chamber further comprises a lifting structure, wherein a driving end of the lifting structure is connected with the lower liner and used for changing the distance of the axial gap.
Optionally, the connecting cylinder comprises an upper cylinder and a lower cylinder, the top of the upper cylinder is connected with the cavity, the bottom of the upper cylinder and the top of the lower cylinder are radially spaced and arranged in a superposition manner, and the bottom of the lower cylinder is connected with the guide plate.
Optionally, the superposition height between the upper cylinder and the lower cylinder is less than or equal to 3mm, the interval distance between the upper cylinder and the lower cylinder is less than or equal to 1.5mm, and the distance between the lower cylinder and the inner wall of the cavity is more than or equal to 12mm.
Optionally, the base further includes a land, the land being disposed between the bottom insulating ring and the chuck;
An insulating groove is formed in the central area of the top surface of the connecting disc, the edge area of the top surface of the connecting disc is in contact with the bottom of the chuck, and the edge area surrounds the periphery of the central area;
the lower electrode assembly is electrically connected with the bottom surface of the land to be electrically connected with the base through the land.
Optionally, the lower electrode assembly includes a power supply, a matcher and a coaxial cable, and the power supply feeds radio frequency to the base through the matcher and the coaxial cable in sequence;
the coaxial cable passes through the surrounding area of the bottom insulating ring and is electrically connected with the connecting disc;
A preset gap is arranged between the bottom insulating ring and the coaxial cable, and a gas medium exists in the preset gap.
As a second aspect of the present invention, there is provided a semiconductor process apparatus comprising the semiconductor process chamber as described above.
In the semiconductor process chamber and the semiconductor process equipment provided by the invention, the lining component is of a split type design and comprises an upper lining, a lower lining and an isolation structure in insulating connection between the upper lining and the lower lining, wherein the upper lining and the lower lining are respectively and electrically connected with the top and the bottom of the cavity, so that a capacitance structure is formed between the upper lining and the lower lining, and further, the capacitance is increased on the path of the plasma sheath layer connected with the cavity through the lining component. The capacitance value of the capacitance structure formed by the upper lining, the lower lining and the isolation structure is adjusted, so that the ratio between the power participating in plasma ionization and the power generating bias voltage in the power of the lower electrode can be adjusted, and the self bias voltage of the lower electrode is improved.
Drawings
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate the invention and together with the description serve to explain, without limitation, the invention. In the drawings:
FIG. 1 is a schematic diagram of a prior art semiconductor processing chamber;
FIG. 2 is a schematic diagram of an equivalent circuit of two corresponding branches of the power fed to the bottom electrode of the susceptor in the semiconductor process chamber shown in FIG. 1;
FIG. 3 is a schematic view of a semiconductor process chamber according to an embodiment of the present invention;
FIG. 4 is a schematic view of a liner assembly in a semiconductor processing chamber according to an embodiment of the present invention;
FIG. 5 is a schematic illustration of the mounting relationship between a liner assembly and a chamber body in a semiconductor processing chamber according to an embodiment of the present invention;
FIG. 6 is a schematic view of a spacer sleeve 504 in a semiconductor processing chamber according to an embodiment of the present invention;
fig. 7 is an equivalent circuit schematic diagram of two branches corresponding to power fed to a bottom electrode of a susceptor in a semiconductor process chamber according to an embodiment of the present invention;
fig. 8 is a schematic diagram showing the effect of adjusting the surface voltage of the susceptor by using the semiconductor process chamber provided by the present invention.
Reference numerals illustrate:
100: upper liner 110: deflector plate
120: The connecting cylinder 121: upper cylinder
122: Lower cylinder 200: lower lining
210: The connection ring 220: connecting ring
300: Isolation structure 310: dielectric spacer ring
320: Fastener 330: isolation sleeve
331: First sleeve segment 332: second sleeve section
333: Transition section 510: chuck
513: Tray 520: edge insulating ring
530: Bottom insulating ring 600: connecting disc
10: Cavity 20: upper electrode coil shielding cavity
31: Power supply 32: matcher
33: Coaxial cable 40: dielectric window
41: Nozzle 51: radio frequency power supply
52: Matcher 53: upper electrode coil
60: Shielding plate 106: outer conductor layer
107: Inner core 302: cavity body
303: Liner 304: screw bolt
306: Shielding structure 402: art tray
403: Chuck 405: support spacer
Detailed Description
The following describes specific embodiments of the present invention in detail with reference to the drawings. It should be understood that the detailed description and specific examples, while indicating and illustrating the invention, are not intended to limit the invention.
The inventor of the present invention found after research that the inner liner of the process chamber in the prior art scheme only considers the convenience of maintaining the by-product of the chamber, and does not consider the condition of the transmission path of the 2MHz radio frequency power. As shown in fig. 1, the existing liner 303 employs a monolithic liner scheme to protect the sidewalls of the entire chamber from sputtering and deposition of process byproducts onto the chamber walls.
An equivalent circuit diagram corresponding to the lower electrode structure in the prior art is shown in fig. 2, wherein R represents an equivalent series resistance value of the shielding structure 306 of the lower electrode, the inner core 107 of the coaxial cable and the outer conductor layer 106, C stray represents an equivalent capacitance value between the chuck 403 and the shielding structure 306 and the inner liner 303 of the lower electrode, L chamber represents an equivalent inductance value of the shielding structure 306 of the lower electrode and the inner core 107 of the coaxial cable, C tray-base represents an equivalent capacitance value between the chuck 403 and the process tray 402, an equivalent circuit model of the plasma sheath layer in a process area range of the chamber in a left dashed box, and the overall sheath capacitance value of the plasma (plasma) in the prior art is in the order of nF (nano method), since the integral inner liner 303 is adopted in the prior art chamber structure, and the inner liner 303 is fixedly mounted by using the screw 304, the power of the inner liner 303 is a lossless conduction circuit for a 2MHz plasma path, and the impedance on the path of the 2MHz power propagating to the chamber 302 through the inner liner 303 is zero as shown in a right box in fig. 2.
Therefore, this integral liner scheme results in very little impedance of the 2MHz power fed from the lower electrode over the liner during the process, such that the 2MHz plasma path variable sheath impedance is less than the inherent impedance of the lower electrode itself, and the proportion of the 2MHz power fed to the chuck that participates in plasma ionization is greater than the power that generates the bias voltage. The plasma above the chuck cannot form a high impedance condition for 2MHz power, so that more power participates in plasma ionization, and finally the power on the chuck is in a state of large current and small voltage, so that the 2MHz radio frequency self-bias voltage on the surface of the chuck is relatively low, the ion energy is low and the bombardment capacity is poor.
To solve the above-mentioned problems, as an aspect of the present invention, there is provided a semiconductor process chamber, as shown in fig. 3, which includes a chamber body 10, a susceptor, a lower electrode assembly and a liner assembly, wherein the susceptor and the liner assembly are disposed in the chamber body 10, the susceptor includes a chuck 510, the chuck 510 has a carrying surface for carrying a wafer, the liner assembly is disposed around the susceptor, the lower electrode assembly is used for providing radio frequency to the chuck, wherein the liner assembly includes an upper liner 100, a lower liner 200 and an isolation structure 300, a bottom of the upper liner 100 is connected with a top of the lower liner 200 in an insulating manner by the isolation structure 300, and a bottom of the lower liner 200 is electrically connected with a bottom of the chamber body 10.
In the semiconductor process chamber provided by the invention, the liner assembly is of a split type design, and comprises an upper liner 100, a lower liner 200 and an isolation structure 300 connected between the upper liner 100 and the lower liner 200 in an insulating manner, wherein the upper liner 100 and the lower liner 200 are respectively and electrically connected with the top and the bottom of the cavity 10, so that a capacitance structure is formed between the upper liner 100 and the lower liner 200, and further, the capacitance is increased on the path of the plasma sheath layer connected with the cavity 10 through the liner assembly. The capacitance value of the capacitance structure formed by the upper liner 100, the lower liner 200 and the isolation structure 300 is adjusted, so that the ratio between the power involved in plasma ionization and the power generating bias voltage in the power of the lower electrode can be adjusted, and the self bias voltage of the lower electrode can be improved.
Specifically, as shown in fig. 7, an equivalent circuit schematic diagram of two branches corresponding to the power fed to the lower electrode of the base is shown, where R represents equivalent series resistance values corresponding to the inner core 33a and the outer conductor layer 33b of the coaxial cable and the shielding plate 60, C stray represents equivalent capacitance values between the chuck 510, the shielding plate 60 and the liner component, L chamber represents equivalent inductance values of the inner core 33a and the shielding plate 60 of the lower electrode coaxial cable, C tray-base represents capacitance values between the chuck 510 and the tray 513, C liner represents capacitance values between the liner component and the chamber 10, and Plasma (Plasma) is an equivalent circuit model of the Plasma sheath layer within the Plasma process area in the dashed line frame.
In the invention, the capacitance C liner on the path of the plasma sheath connected with the cavity 10 through the lining component is adjustable, so that the total impedance of the branch corresponding to the power participating in plasma ionization in the lower electrode power can be changed by changing the size of the capacitance C liner, and the ratio between the power participating in plasma ionization and the power generating bias voltage in the lower electrode power is further adjusted, thereby realizing the improvement of the self bias voltage of the lower electrode.
As an alternative embodiment of the present invention, as shown in fig. 3, the upper liner 100 includes a baffle 110 and a connecting cylinder 120, the baffle 110 is disposed at the bottom of the connecting cylinder 120, and the baffle 110 is disposed around the outer side of the base, the baffle 110 is lower than the bearing surface and is disposed parallel to the bearing surface, and the top of the connecting cylinder 120 is connected with the top of the cavity 10;
The lower liner 200 is cylindrical, the lower liner 200 is disposed around the base, and the isolation structure 300 is located between the lower liner 200 and the baffle 110.
In the embodiment of the present invention, the upper liner 100 includes a baffle 110 and a connecting cylinder 120 which are horizontally disposed, the cylindrical lower liner 200 is surrounded around the periphery of the susceptor (the size corresponds to the peripheral size of the susceptor), the height of the baffle 110 corresponds to the height of the susceptor, so that Plasma (Plasma) is maintained above the susceptor and the baffle 110, the isolation structure 300 and the lower liner 200 form a capacitor structure.
As an alternative embodiment of the present invention, as shown in fig. 3, the susceptor further includes an edge insulating ring 520 and a bottom insulating ring 530, the bottom insulating ring 530 is disposed at the bottom of the chuck 510, and the edge insulating ring 520 is disposed at the outer side of the chuck 510 and is disposed on the bottom insulating ring 530; the spacer structure 300 is positioned axially between the top and bottom surfaces of the edge insulator ring 520.
In an embodiment of the present invention, edge insulator ring 520 and bottom insulator ring 530 are used together to isolate the rf power on chuck 510 such that the desired rf bias is generated on the load-bearing surface of chuck 510. Alternatively, the material of the edge insulating ring 520 and the bottom insulating ring 530 may be ceramic.
As an alternative embodiment of the present invention, as shown in fig. 3, the susceptor further includes a cooling passage provided inside the chuck 510 for circulating a cooling medium to cool the chuck 510.
To facilitate processing multiple wafers simultaneously, as an alternative embodiment of the present invention, as shown in fig. 3, the susceptor may further include a tray 513 and a pressing ring 514, where after the tray 513 carries the wafers and is placed on the chuck 510, the pressing ring 514 descends and presses the tray 513 to position the wafers. By adding tray 513 to process multiple wafers simultaneously or by processing only a single wafer without tray 513, it may be selected according to specific process requirements.
Optionally, as shown in fig. 3, the base further includes a focusing ring 512, and a focusing groove is formed on a top surface of the chuck 510, and the focusing ring 512 is correspondingly disposed in the focusing groove. The focus ring 512 is ceramic for adjusting process uniformity at the edge of the tray.
In order to facilitate adjustment of the capacitance value of the capacitor structure formed by the baffle 110, the isolation structure 300 and the lower liner 200, as an alternative embodiment of the present invention, the isolation structure 300 may be an annular member made of a dielectric material, and the adjustment of the size of the C liner is achieved by replacing the isolation structure 300, specifically, as shown in fig. 4, the isolation structure 300 includes a dielectric isolation ring 310, where the dielectric isolation ring 310 is detachably disposed between the baffle 110 and the lower liner 200.
In the embodiment of the present invention, the isolation structure 300 includes the dielectric isolation ring 310 detachably disposed between the baffle 110 and the lower liner 200, so that the capacitance between the connection ring 210 and the baffle 110 can be adjusted in a large range by changing the dielectric material or the dielectric thickness between the baffle 110 and the lower liner 200 by changing the dielectric isolation ring 310, thereby improving the adjustment efficiency of the self-bias voltage of the lower electrode.
Optionally, the dielectric spacer 310 may be made of at least one of quartz, ceramic, polytetrafluoroethylene, and epoxy.
In order to ensure the stability of the position of the baffle 110 and the circumferential uniformity of the capacitance between the connection ring 210 and the baffle 110, as a preferred embodiment of the present invention, as shown in fig. 3 to 5, the top of the lower liner 200 is provided with the connection ring 210, and the baffle 110, the dielectric spacer 310 and the connection ring 210 are correspondingly provided with a plurality of mounting holes along the circumferential direction;
The isolation structure 300 further includes a plurality of fasteners 320 and a plurality of isolation sleeves 330, the plurality of isolation sleeves 330 sequentially pass through the corresponding mounting holes, respectively, the plurality of fasteners 320 pass through the plurality of isolation sleeves 330 in a one-to-one correspondence, fixing the baffle 110, the dielectric isolation ring 310, and the connection ring 210.
In the embodiment of the invention, the baffle 110, the medium isolation ring 310 and the connection ring 210 are fastened and connected by the fastener 320, and the isolation sleeve 330 is sleeved outside the fastener 320, so that the stability of the position of the baffle 110 is improved while the insulativity between the baffle 110 and the connection ring 210 is ensured, and the circumferential uniformity of the capacitance between the connection ring 210 and the baffle 110 is ensured.
As an alternative embodiment of the present invention, as shown in fig. 4 to 6, the fastener 320 includes a set screw, the isolation sleeve 330 includes a first sleeve section 331, a second sleeve section 332, and a transition section 333, the inner hole of the first sleeve section 331 has a larger diameter than the inner hole of the second sleeve section 332, the bottom end of the first sleeve section 331 is connected to the top end of the second sleeve section 332 through the transition section 333, and the inner hole of the first sleeve section 331 is in communication with the inner hole of the second sleeve section 332.
As shown in fig. 4, when the baffle 110, the dielectric spacer 310 and the connection ring 210 are fixed, the bottom end of the second sleeve section 332 is first sequentially passed through the corresponding mounting holes downwards until the bottom of the transition section 333 contacts with the top surface of the baffle 110, then the fixing screw is penetrated through the inner hole of the first sleeve section 331 until the head of the fixing screw falls into the first sleeve section 331, and then the fixing screw is matched with the tail of the fixing screw through nuts and other parts, so as to compress the baffle 110, the dielectric spacer 310 and the connection ring 210 from the upper side and the lower side (the upper side and the lower side refer to the upper direction and the lower direction in the drawing).
Alternatively, as shown in fig. 6, the wall thickness h1 of the first sleeve section 331 and the wall thickness h2 of the second sleeve section 332 are about 2mm, and the thickness h3 of the transition section 333 in the vertical direction is about 2.5 mm.
In the case that the lower liner 200 is fixed in position, if the thickness of the medium spacer ring 310 is changed when the medium spacer ring 310 is replaced, the height of the baffle 110 needs to be adjusted correspondingly up and down, and in order to ensure the protection effect of the liner assembly on the inner wall of the cavity 10, as shown in fig. 3 and 5, as a preferred embodiment of the present invention, the connecting cylinder 120 includes an upper cylinder 121 and a lower cylinder 122, the top of the upper cylinder 121 is connected with the cavity 10, and the bottom of the upper cylinder 121 and the top of the lower cylinder 122 are radially spaced and axially overlapped, and the bottom of the lower cylinder 122 is connected with the baffle 110.
In the embodiment of the present invention, the connecting cylinder 120 is designed in a sectional manner, the bottom of the upper cylinder 121 and the top of the lower cylinder 122 are radially spaced and axially overlapped, so that the upper cylinder 121 can be fixed, the lower cylinder 122 can vertically lift along with the baffle 110, and the flexibility of the position of the baffle 110 is improved while the inner liner component covers the inner wall of the cavity 10.
To further secure the protection effect of the liner assembly on the inner wall of the cavity 10, as a preferred embodiment of the present invention, as shown in fig. 3 to 5, the upper cylinder 121 includes an upper cylinder section, a transition section and a lower cylinder section which are sequentially connected to each other from top to bottom, the diameter of the upper cylinder section is greater than the diameter of the lower cylinder 122, and the diameter of the lower cylinder 122 is greater than the diameter of the lower cylinder section.
In the embodiment of the invention, the lower end of the upper cylinder 121 comprises a transition section and a lower cylinder section, namely, the top end of the lower cylinder 122 is shielded by bending the lower part of the upper cylinder 121, so that the plasma flow in the plasma region is further prevented from leaking from the interval between the upper cylinder 121 and the lower cylinder 122 in the process, and the protection effect of the liner assembly on the cavity 10 is further ensured.
It should be noted that, since there are opposite portions between the two sides of the lower cylinder 122 and the grounded upper cylinder 121 and the grounded side wall of the cavity 10, three parallel power paths exist between the plasma sheath and the cavity 10 in the process area of the cavity, wherein the first one is the plasma sheath→the lower cylinder 122→the side wall of the cavity 10, the second one is the plasma sheath→the lower cylinder 122→the upper cylinder 121→the cavity 10, and the third one is the plasma sheath→the lower cylinder 122→the baffle 110→the connecting ring 210→the cavity 10.
Since the self-bias voltage of the lower electrode needs to be adjusted by adjusting the capacitance of the third path (i.e., the capacitance between the connection ring 210 and the baffle 110), the capacitance of the remaining two paths (i.e., the capacitance between the lower cylinder 122 and the sidewall of the chamber 10 and the capacitance between the lower cylinder 122 and the upper cylinder 121) needs to be small enough, and the capacitance of the third path is large enough to ensure the adjustment effect. For example, alternatively, the capacitance on the remaining two paths may be equal to or less than (1/10) C liner (the total capacitance between the liner assembly and the chamber 10, C liner, may be selected according to design criteria), and the capacitance between the connecting ring 210 and the baffle 110 may be equal to or greater than (4/5) C liner.
For example, as shown in fig. 5, for the first path, in order to ensure that the capacitance between the lower barrel 122 and the side wall of the cavity 10 is less than or equal to (1/10) C liner, the distance d1 between the lower barrel 122 and the inner wall of the cavity 10 needs to be greater than or equal to 12mm; for the second path, in order to ensure that the capacitance between the lower cylinder 122 and the upper cylinder 121 is equal to or less than (1/10) C liner, the distance d2 between the lower cylinder 122 and the upper cylinder 121 needs to be equal to or less than 1.5mm, and the overlapping height L between the lower cylinder 122 and the upper cylinder 121 should be equal to or less than 3mm.
In order to ensure the stability of the position of the lower liner 200 and the good grounding condition of the lower end thereof, preferably, the bottom end of the lower liner 200 is fixedly connected with the grounding member on the bottom wall of the chamber 10 by means of fastening connection. Specifically, as shown in fig. 3 to 5, the bottom end of the lower liner 200 is further connected with a connection ring 220, a bottom connection cylinder 410 surrounding the base is provided on the bottom wall of the cavity 10, an annular bottom connection plate 420 is fixedly connected to the top of the bottom connection cylinder 410, and the connection ring 220 is fastened and connected with the annular bottom connection plate 420 through a plurality of fasteners 430 (for example, may be fastening screws).
As another alternative embodiment of the present invention, there is an axial gap (gap spaced along the axial direction of the cavity) between the baffle 110 and the lower liner 200, which forms the isolation structure 300.
In the embodiment of the present invention, the capacitor structure is directly formed by the baffle 110 and the (connection ring 210 of the) lower liner 200 at intervals, and the size of the capacitor C liner can be adjusted only by adjusting the distance between the baffle 110 and the connection ring 210.
To improve the convenience of adjusting the size of the capacitor C liner, as a preferred embodiment of the present invention, the semiconductor process chamber further includes a lifting structure (not shown), the driving end of which is connected to the lower liner 200 for changing the distance of the axial gap.
In the embodiment of the present invention, the lower liner 200 can be driven by the lifting structure of the semiconductor process chamber to move up and down, so that the capacitor C liner between the baffle 110 and the connection ring 210 can be automatically adjusted in real time without disassembling the chamber 10.
The inventors of the present invention have also found in research that in prior art semiconductor process chambers, as shown in fig. 1, the inner core 107 of the lower electrode coaxial cable is typically directly connected to the chuck 403, the power transmission path is too short, and thus the electromagnetic field distribution on the upper surface of the susceptor or the surface of the process tray 402 is not uniform.
To solve the above technical problem, as a preferred embodiment of the present invention, as shown in fig. 3, the base further includes a connection pad 600, the connection pad 600 being disposed between the bottom insulating ring 530 and the chuck 510;
an insulation groove is formed in the central area of the top surface of the connection disc 600, the edge area of the top surface of the connection disc 600 is in contact with the bottom of the chuck 510, and the edge area surrounds the periphery of the central area;
The lower electrode assembly is electrically connected to the bottom surface of the land 600 to be electrically connected to the base through the land 600.
In the embodiment of the present invention, the lower electrode assembly is indirectly electrically connected to the base through the connection pad 600, and the top surface of the connection pad 600 is in contact with the bottom surface of the base only at the edge region, so that the electromagnetic field is distorted at the connection point, thereby making the distribution of the electromagnetic field transmitted to the upper surface of the base or the surface of the tray 513 more uniform.
As an alternative embodiment of the present invention, as shown in fig. 3, the lower electrode assembly includes a power supply 31 (RF Generator), a matcher 32, and a Coaxial cable 33 (Coaxial line), and the power supply 31 feeds radio frequency to the susceptor through the matcher and the Coaxial cable in this order.
To further enhance the effect of adjusting the bias voltage of the lower electrode, as a preferred embodiment of the present invention, as shown in fig. 3, a coaxial cable 33 passes through the surrounding area of the bottom insulating ring 530 and is electrically connected to the land 600; there is a predetermined gap between the bottom insulating ring 530 and the coaxial cable 33, and a gaseous medium exists in the predetermined gap.
Optionally, a shielding plate 60 is further disposed below the bottom insulating ring 530, and is used for shielding the pulse signal of the base, a avoidance hole penetrating through the shielding plate 60 along the vertical direction is formed in the center of the shielding plate 60, and the coaxial cable 33 sequentially penetrates through the avoidance hole of the shielding plate 60 and is electrically connected with the inner hole of the bottom insulating ring 530 and the bottom surface of the connecting disc 600.
In the prior art, the isolation structure under the chuck is generally a plate-like structure, and as shown in fig. 1, the shielding structure 306 and the supporting spacer 405 are both plate-like structures, and only through holes having a size corresponding to the coaxial cable are reserved at positions where the coaxial cable needs to pass through. In the embodiment of the present invention, the supporting spacer 405 below the chuck is changed to the bottom insulating ring 530, a preset gap is formed between the sidewall of the inner hole of the bottom insulating ring 530 and the coaxial cable 33, and a gas medium (such as air) is present in the preset gap, so that the dielectric constant of the gas is small, and the corresponding capacitance value is also small, thereby reducing the capacitance value below the base, so that the intrinsic capacitance path of the lower electrode power on the base is mainly laterally and the intrinsic capacitance path of the bottom of the base is mainly assisted, and the intrinsic capacitance path of the upper electrode power and the lower electrode power of the lower electrode base mainly goes through the lower liner 200. In a specific implementation, the inner ring radius of the bottom insulating ring 530 is between 100mm and 140 mm.
Fig. 8 is a schematic diagram showing the effect of adjusting the surface voltage of the susceptor by using the semiconductor process chamber provided by the present invention, wherein the abscissa is the bottom electrode power (Bias power), the ordinate is the voltage value (V chuck) of the susceptor surface, and different curves correspond to different capacitances C liner between the liner assembly and the chamber 10. As can be seen from fig. 8, the regulation of the pedestal surface voltage V chuck can be achieved by varying C liner while maintaining a consistent 2MHz power, with the pedestal surface voltage V chuck decreasing non-linearly as C liner increases (e.g., the pedestal surface voltage V chuck at C liner at 100pF and at C liner at 950Vpk and at C liner at 400pF at 650Vpk, at 400W power).
From the relationship between the capacitance value C liner and the base surface voltage V chuck in fig. 8, it can be seen that the scheme of the present invention can effectively adjust the base surface voltage, so as to meet the requirement of more processes.
As an alternative embodiment of the present invention, as shown in fig. 3, the semiconductor process chamber further includes an upper electrode coil shielding cavity 20, a dielectric window 40, and an upper electrode assembly, the dielectric window 40 is fixedly connected with the top of the cavity 10 and closes an opening at the top of the cavity 10, and the upper electrode coil shielding cavity 20 is disposed above the dielectric window 40.
The semiconductor process chamber may further include a nozzle 41 disposed on the dielectric window 40, and a gas supply line connected to the nozzle 41 through the upper electrode coil shielding chamber 20 for supplying a process gas into the chamber 10 through the dielectric window 40 by the nozzle 41.
As shown in fig. 3, the upper electrode assembly includes a radio frequency power supply 51, a matcher 52, and an upper electrode coil 53 disposed in the upper electrode coil shielding chamber 20, the radio frequency power supply 51 is configured to supply radio frequency power to the upper electrode coil 53 through the matcher 52, so that the upper electrode coil 53 feeds an incident frequency signal into the chamber 10 through the dielectric window 40 to ionize the process gas in the chamber 10 to form plasma.
As a second aspect of the present invention, there is provided a semiconductor processing apparatus comprising a semiconductor processing chamber provided by an embodiment of the present invention.
In the semiconductor processing apparatus provided by the present invention, the liner assembly of the semiconductor processing chamber is of a split type design, and comprises an upper liner 100, a lower liner 200 and an isolation structure 300 connected between the upper liner 100 and the lower liner 200 in an insulating manner, wherein the upper liner 100 and the lower liner 200 are respectively electrically connected with the top and the bottom of the chamber 10, so that a capacitance structure is formed between the upper liner 100 and the lower liner 200, and a capacitance is further added on a path of the plasma sheath layer connected with the chamber 10 through the liner assembly. The capacitance value of the capacitance structure formed by the upper liner 100, the lower liner 200 and the isolation structure 300 is adjusted, so that the ratio between the power involved in plasma ionization and the power generating bias voltage in the power of the lower electrode can be adjusted, and the self bias voltage of the lower electrode can be improved.
It is to be understood that the above embodiments are merely illustrative of the application of the principles of the present invention, but not in limitation thereof. Various modifications and improvements may be made by those skilled in the art without departing from the spirit and substance of the invention, and are also considered to be within the scope of the invention.
Claims (12)
1. The semiconductor process chamber comprises a cavity, a base, a lower electrode assembly and a lining assembly, wherein the base and the lining assembly are arranged in the cavity, the base comprises a chuck, the chuck is provided with a bearing surface for bearing a wafer, the lining assembly is circumferentially arranged around the base, and the lower electrode assembly is used for providing radio frequency for the chuck, the semiconductor process chamber is characterized in that the lining assembly comprises an upper lining, a lower lining and an isolation structure, the top of the upper lining is electrically connected with the top wall of the cavity, the bottom of the upper lining is electrically connected with the top of the lower lining through the isolation structure in an insulating manner, and the bottom of the lower lining is electrically connected with the bottom of the cavity;
The upper lining comprises a guide plate and a connecting cylinder, the guide plate is arranged at the bottom of the connecting cylinder, the guide plate is arranged on the outer side of the base in a surrounding mode, the guide plate is lower than the bearing surface and is arranged in parallel with the bearing surface, and the top of the connecting cylinder is connected with the top of the cavity;
the lower lining is cylindrical, the lower lining surrounds the base, and the isolation structure is located between the lower lining and the guide plate.
2. The semiconductor process chamber of claim 1, wherein the susceptor further comprises an edge insulator ring and a bottom insulator ring, the bottom insulator ring disposed at the bottom of the chuck, the edge insulator ring disposed outside of the chuck and on the bottom insulator ring;
The isolation structure is located between the top surface and the bottom surface of the edge insulating ring at the axial position.
3. The semiconductor process chamber of claim 2, wherein the isolation structure comprises a dielectric isolation ring removably disposed between the baffle and the lower liner.
4. The semiconductor process chamber according to claim 3, wherein a connecting ring is arranged at the top of the lower liner, and a plurality of mounting holes are correspondingly arranged on the guide plate, the medium isolation ring and the connecting ring along the circumferential direction;
the isolation structure further comprises a plurality of fasteners and a plurality of isolation sleeves, the isolation sleeves respectively penetrate through the corresponding mounting holes in sequence, the fasteners penetrate through the isolation sleeves in a one-to-one correspondence mode, and the guide plate, the medium isolation ring and the connecting ring are fixed.
5. The semiconductor processing chamber of claim 3, wherein the dielectric spacer ring comprises: at least one of quartz, ceramic, polytetrafluoroethylene and epoxy resin.
6. The semiconductor process chamber of claim 2, wherein an axial gap is provided between the baffle plate and the lower liner, the axial gap forming the isolation structure.
7. The semiconductor process chamber of claim 6, further comprising a lift structure having a drive end coupled to the lower liner for varying the distance of the axial gap.
8. The semiconductor process chamber of claim 1, wherein the connecting cylinder comprises an upper cylinder and a lower cylinder, the top of the upper cylinder is connected with the cavity, the bottom of the upper cylinder and the top of the lower cylinder are radially spaced and arranged in superposition, and the bottom of the lower cylinder is connected with the guide plate.
9. The semiconductor processing chamber of claim 8, wherein a height of overlap between the upper and lower cylinders is 3mm or less, a separation distance between the upper and lower cylinders is 1.5mm or less, and a distance between the lower cylinder and the inner wall of the chamber is 12mm or more.
10. The semiconductor process chamber of claim 2, wherein the pedestal further comprises a land disposed between the bottom insulating ring and the chuck;
An insulating groove is formed in the central area of the top surface of the connecting disc, the edge area of the top surface of the connecting disc is in contact with the bottom of the chuck, and the edge area surrounds the periphery of the central area;
the lower electrode assembly is electrically connected with the bottom surface of the land to be electrically connected with the base through the land.
11. The semiconductor process chamber of claim 10, wherein the lower electrode assembly comprises a power supply, a matcher, and a coaxial cable, the power supply feeding radio frequency to the pedestal through the matcher, the coaxial cable in sequence;
the coaxial cable passes through the surrounding area of the bottom insulating ring and is electrically connected with the connecting disc;
A preset gap is arranged between the bottom insulating ring and the coaxial cable, and a gas medium exists in the preset gap.
12. A semiconductor processing apparatus comprising the semiconductor processing chamber of any one of claims 1 to 11.
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| CN202210003575.3A CN114361000B (en) | 2022-01-04 | 2022-01-04 | Semiconductor process chamber and semiconductor process equipment |
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| CN202210003575.3A CN114361000B (en) | 2022-01-04 | 2022-01-04 | Semiconductor process chamber and semiconductor process equipment |
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| CN114361000B true CN114361000B (en) | 2024-04-16 |
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Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101926232A (en) * | 2008-01-28 | 2010-12-22 | 应用材料公司 | Etching chamber having flow equalizer and lower liner |
| CN204455275U (en) * | 2015-02-10 | 2015-07-08 | 北京北方微电子基地设备工艺研究中心有限责任公司 | A kind of inner lining structure of sputtering technology reaction chamber |
| WO2015135350A1 (en) * | 2014-03-13 | 2015-09-17 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Reaction chamber and plasma machining device |
| CN107578977A (en) * | 2017-09-27 | 2018-01-12 | 北京北方华创微电子装备有限公司 | Reaction chamber and capacitance coupling plasma equipment |
| CN207320060U (en) * | 2017-09-27 | 2018-05-04 | 北京北方华创微电子装备有限公司 | Reaction chamber and capacitance coupling plasma equipment |
| CN209133451U (en) * | 2018-11-02 | 2019-07-19 | 北京北方华创微电子装备有限公司 | Liner Components, reaction chamber and semiconductor processing equipment |
| CN110289200A (en) * | 2019-07-01 | 2019-09-27 | 北京北方华创微电子装备有限公司 | Liner Components and processing chamber |
| WO2020088413A1 (en) * | 2018-11-02 | 2020-05-07 | 北京北方华创微电子装备有限公司 | Liner assembly, reaction chamber and semiconductor processing apparatus |
| CN112017933A (en) * | 2019-05-31 | 2020-12-01 | 北京北方华创微电子装备有限公司 | Lining, reaction chamber and semiconductor processing equipment |
| CN112259429A (en) * | 2020-09-30 | 2021-01-22 | 北京北方华创微电子装备有限公司 | Semiconductor process equipment |
-
2022
- 2022-01-04 CN CN202210003575.3A patent/CN114361000B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101926232A (en) * | 2008-01-28 | 2010-12-22 | 应用材料公司 | Etching chamber having flow equalizer and lower liner |
| WO2015135350A1 (en) * | 2014-03-13 | 2015-09-17 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Reaction chamber and plasma machining device |
| CN204455275U (en) * | 2015-02-10 | 2015-07-08 | 北京北方微电子基地设备工艺研究中心有限责任公司 | A kind of inner lining structure of sputtering technology reaction chamber |
| CN107578977A (en) * | 2017-09-27 | 2018-01-12 | 北京北方华创微电子装备有限公司 | Reaction chamber and capacitance coupling plasma equipment |
| CN207320060U (en) * | 2017-09-27 | 2018-05-04 | 北京北方华创微电子装备有限公司 | Reaction chamber and capacitance coupling plasma equipment |
| CN209133451U (en) * | 2018-11-02 | 2019-07-19 | 北京北方华创微电子装备有限公司 | Liner Components, reaction chamber and semiconductor processing equipment |
| WO2020088413A1 (en) * | 2018-11-02 | 2020-05-07 | 北京北方华创微电子装备有限公司 | Liner assembly, reaction chamber and semiconductor processing apparatus |
| CN112017933A (en) * | 2019-05-31 | 2020-12-01 | 北京北方华创微电子装备有限公司 | Lining, reaction chamber and semiconductor processing equipment |
| CN110289200A (en) * | 2019-07-01 | 2019-09-27 | 北京北方华创微电子装备有限公司 | Liner Components and processing chamber |
| CN112259429A (en) * | 2020-09-30 | 2021-01-22 | 北京北方华创微电子装备有限公司 | Semiconductor process equipment |
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