CN114355236A - Detection method and device for rectification inverter circuit and uninterruptible power supply - Google Patents
Detection method and device for rectification inverter circuit and uninterruptible power supply Download PDFInfo
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Abstract
The invention provides a detection method and a detection device for a rectification inverter circuit and an uninterruptible power supply, wherein the method comprises the following steps: acquiring voltage phase values of an input end and an output end of a rectification inverter circuit; carrying out attenuation processing on the voltage phase value of the output end to obtain a reference value; comparing the voltage phase value of the input end with a reference value, if the voltage phase value of the input end is smaller than the reference value, starting timing, and recording the duration of time that the voltage phase value of the input end is smaller than the reference value; and if the duration is longer than the preset duration, determining that the rectification inverter circuit is abnormal, wherein the abnormality comprises the power failure of the input end, or the voltage phase of the input end and the voltage phase of the output end are asynchronous. The invention can realize the abnormal detection of power failure and phase desynchronization in the rectification inverter circuit.
Description
Technical Field
The invention relates to the technical field of circuits, in particular to a detection method and a detection device for a rectification inverter circuit and an uninterruptible power supply.
Background
With the development of circuit technology, the rectification and inversion technology is widely applied. However, in practical application of the rectification inverter circuit, the power failure of the input end power supply of the rectification inverter circuit may occur, and the voltage at the input end and the voltage at the output end are not synchronous, which may cause a short circuit inside the rectification inverter circuit, and components inside the rectification inverter circuit need to bear a larger short-circuit voltage or short-circuit, and may cause damage to the components inside the rectification inverter circuit in severe cases, thereby affecting the safety and reliability of the rectification inverter circuit.
Disclosure of Invention
The invention provides a detection method and a detection device for a rectification inverter circuit and an uninterruptible power supply, which can realize abnormal detection of power failure and phase desynchronization in the rectification inverter circuit.
In a first aspect, the present invention provides a detection method for a rectification inverter circuit, including: acquiring voltage phase values of an input end and an output end of a rectification inverter circuit; carrying out attenuation processing on the voltage phase value of the output end to obtain a reference value; comparing the voltage phase value of the input end with a reference value, if the voltage phase value of the input end is smaller than the reference value, starting timing, and recording the duration of time that the voltage phase value of the input end is smaller than the reference value; and if the duration is longer than the preset duration, determining that the rectification inverter circuit is abnormal, wherein the abnormality comprises the power failure of the input end, or the voltage phase of the input end and the voltage phase of the output end are asynchronous.
The invention provides a detection method of a rectification inverter circuit, which obtains a reference value by carrying out attenuation processing on a phase value at an output end, compares a voltage phase value at an input end with the reference value, and determines that the input end of the rectification inverter circuit is in power failure or phase desynchronization when the voltage phase value at the input end is smaller than the reference value and is longer than a preset time duration, thereby realizing the abnormal detection of the power failure or the phase desynchronization of the input end of the rectification inverter circuit.
In one possible implementation, obtaining a voltage phase value of an input terminal of a rectifying inverter circuit includes: acquiring a voltage instantaneous value of an input end and a voltage effective value of the input end; the ratio of the instantaneous value of the voltage at the input end to the effective value of the voltage at the input end is determined as the phase value of the voltage at the input end.
In one possible implementation, obtaining a voltage phase value of an output terminal of the rectifying inverter circuit includes: and acquiring a voltage phase value of the output end through the phase-locked loop.
In a possible implementation manner, the attenuating the voltage phase value of the output terminal to obtain a reference value includes: and determining the product of the voltage phase value of the output end and a preset coefficient as a reference value, wherein the preset coefficient is in negative correlation with the harmonic content of the input end of the rectification inverter circuit.
In a possible implementation manner, comparing the voltage phase value at the input terminal with a reference value, and starting timing if the voltage phase value at the input terminal is smaller than the reference value, includes: judging whether the voltage phase value of the output end is in an undetected interval or not; if the voltage phase value of the output end belongs to the undetected interval, comparing the voltage phase value of the input end with the reference value; if the voltage phase value of the output end belongs to the detection interval, comparing the voltage phase value of the input end with a reference value, and starting timing when the voltage phase value of the input end is smaller than the reference value; the undetected interval is an interval in which the absolute value of the difference between the voltage phase value of the output end and the first phase value is smaller than a preset threshold value, the first phase value is a phase value when the instantaneous value of the voltage of the output end is zero, and the detection interval is an interval except the undetected interval.
In one possible implementation, the preset duration is greater than 1/20 and less than 1/4 of the period of the input.
In a possible implementation manner, the rectification inverter circuit is a three-bridge-arm topology circuit, the three-bridge-arm topology circuit includes a first bridge arm, a first capacitor, a second bridge arm and a third bridge arm, which are sequentially connected in parallel, the first bridge arm includes a first switch and a second switch tube, the second bridge arm includes a third switch and a fourth switch tube, the third bridge arm includes a fifth switch and a sixth switch tube, a midpoint of the first bridge arm and a midpoint of the second bridge arm are connected to the input end, and a midpoint of the third bridge arm and a midpoint of the second bridge arm are connected to the output end.
In a second aspect, an embodiment of the present invention provides a detection apparatus for a rectification inverter circuit, including a memory, a processor, and a computer program stored in the memory and executable on the processor, where the processor executes the computer program to implement the steps of the method according to the first aspect or any possible implementation manner.
In a third aspect, an embodiment of the present invention provides an uninterruptible power supply, including the detection apparatus for the rectification inverter circuit according to the second aspect, and a rectification inverter circuit; the rectification inverter circuit comprises a rectification module and an inverter module; the first end of the rectifying module is connected with the input end, the second end of the rectifying module is connected with the first end of the inverting module, and the rectifying module is used for converting a first alternating current signal input by the input end into a direct current signal; and the second end of the inverter module is connected with the output end and used for converting the direct current signal into a second alternating current signal to supply power to a load.
In a fourth aspect, the present invention provides a computer-readable storage medium, which stores a computer program, and when the computer program is executed by a processor, the computer program implements the steps of the method according to the first aspect and any possible implementation manner of the first aspect.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
Fig. 1 is a schematic structural diagram of a rectification inverter circuit according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a three-bridge topology circuit according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a control device according to an embodiment of the present invention;
fig. 4 is a schematic flowchart of a detection method of a rectification inverter circuit according to an embodiment of the present invention;
fig. 5 is a schematic flowchart of another detection method for a rectification inverter circuit according to an embodiment of the present invention;
fig. 6 is a schematic flowchart of another detection method for a rectification inverter circuit according to an embodiment of the present invention;
FIG. 7 is a waveform diagram illustrating the phase synchronization of the input voltage and the output voltage according to an embodiment of the present invention;
FIG. 8 is a waveform diagram illustrating the phase of the input and output voltages being out of phase according to an embodiment of the present invention;
fig. 9 is a schematic structural diagram of another control device according to an embodiment of the present invention.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.
In the description of the present invention, "/" means "or" unless otherwise specified, for example, a/B may mean a or B. "and/or" herein is merely an association describing an associated object, and means that there may be three relationships, e.g., a and/or B, which may mean: a exists alone, A and B exist simultaneously, and B exists alone. Further, "at least one" or "a plurality" means two or more. The terms "first", "second", and the like do not necessarily limit the number and execution order, and the terms "first", "second", and the like do not necessarily limit the difference.
In the embodiments of the present application, words such as "exemplary" or "for example" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "e.g.," is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the word "exemplary" or "such as" is intended to present relevant concepts in a concrete fashion for ease of understanding.
Furthermore, the terms "including" and "having," and any variations thereof, as referred to in the description of the present application, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or modules is not limited to the listed steps or modules, but may alternatively include other steps or modules not listed or inherent to such process, method, article, or apparatus.
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following description is made by way of specific embodiments with reference to the accompanying drawings.
Fig. 1 is a topology diagram of a rectifying inverter circuit. The rectification inverter circuit comprises a rectification module 101 and an inverter module 102; the first end of the rectifying module 101 is connected with the input end, and the second end of the rectifying module is connected with the first end of the inverting module 102, and is used for converting a first alternating current signal input by the input end into a direct current signal; the second end of the inverter module 102 is connected to the output end, and is configured to convert the dc signal into a second ac signal to supply power to the load.
The rectifying and inverting circuit shown in fig. 1 may have a phenomenon that an input terminal is powered off or phases of an input terminal voltage and an output terminal voltage are not synchronous, so that components inside the rectifying module 101 and the inverting module 102 need to bear a large reverse voltage, or a short circuit occurs inside the rectifying module 101 and the inverting module 102, so that a large short-circuit current is generated, and the device is easily damaged.
Illustratively, as shown in fig. 2, the rectifying and inverting circuit may be a three-leg topology circuit, the three-leg topology circuit includes a first leg, a first capacitor C1, a second leg, and a third leg, which are connected in parallel in this order, the first leg includes a first switch tube T1 and a second switch tube T2, the second leg includes a third switch tube T3 and a fourth switch tube T4, the third leg includes a fifth switch T5 and a sixth switch tube T6, a midpoint of the first leg and a midpoint of the second leg are connected to the input end, and a midpoint of the third leg and a midpoint of the second leg are connected to the output end. Wherein, the input end is connected with an alternating current power supply. For example, the input may be connected to a mains supply and the output to a load.
In some embodiments, the three-bridge arm topology circuit further comprises: a first diode D1 connected in inverse parallel with the first switching transistor T1, a second diode D2 connected in inverse parallel with the second switching transistor T2, a third diode D3 connected in inverse parallel with the third switching transistor T3, a fourth diode D4 connected in inverse parallel with the fourth switching transistor T4, a fifth diode D5 connected in inverse parallel with the fifth switching transistor T5, and a sixth diode D6 connected in inverse parallel with the sixth switching transistor T6. The six diodes can play the roles of freewheeling and voltage stabilization.
In some embodiments, the three-bridge topology circuit further comprises a first inductor L1 connected in series in the input end circuit and a second inductor L2 connected in series in the output end circuit.
For example, the load at the output terminal may be the second inductor C2 and the first resistor R1.
For the three-bridge-arm topology circuit shown in fig. 2, the input terminal is powered down or the input terminal voltage and the output terminal voltage are not synchronous, which may cause a large reverse voltage and short-circuit current to be generated inside the three-bridge-arm topology circuit, so that a switching tube and a diode inside the three-bridge-arm topology circuit are damaged.
In order to solve the above technical problem, an embodiment of the present invention provides a detection method for a rectification inverter circuit. In order to implement the method, an embodiment of the present application provides a control device for executing a detection method of the rectifying inverter circuit. Fig. 3 is a schematic structural diagram of a control device according to an embodiment of the present application. The control device 300 comprises a communication module 301 and a processing module 302. The control device 300 is connected to the input terminal and the output terminal of the rectifying and inverting circuit, respectively, and obtains electrical parameters of the input terminal and the output terminal, for example, electrical parameters such as voltage and current. The control device is also connected with the switch tube and used for controlling the switch tube.
Fig. 4 is a detection method of a rectifying and inverting circuit according to an embodiment of the present application, applied to the control device 300 shown in fig. 3, where the method includes steps S401 to S403.
S401, the control device obtains voltage phase values of an input end and an output end of the rectification inverter circuit.
As a possible implementation, the control device can obtain the instantaneous voltage value at the input terminal and the effective voltage value at the input terminal, and determine the ratio of the instantaneous voltage value at the input terminal to the effective voltage value at the input terminal as the voltage phase value at the input terminal.
For example, assuming that the control device obtains an instantaneous value of the voltage at the input terminal of 110V and an effective value of the voltage at the input terminal of 220V, the phase value of the voltage at the input terminal is 0.5.
In some embodiments, the control device may obtain a peak voltage value of the input terminal, and determine the effective voltage value of the input terminal according to the maximum voltage value.
As a possible implementation, the control device may obtain the voltage phase value at the output terminal according to a phase-locked loop.
It should be noted that the voltage phase value of the output terminal is related to the load condition of the output terminal. For example, when the output terminal is connected to a capacitive load or an inductive load, the waveform of the voltage may be distorted, so that the voltage phase value of the output terminal is changed. Therefore, the voltage phase value of the output end can be obtained according to the phase-locked loop, and the problem that the voltage phase value error is large due to actual measurement of the load is avoided.
As a possible implementation manner, the control device may periodically detect the voltage instantaneous values of the input end and the output end of the rectification inverter circuit. For example, assuming that the duty cycle of the rectifying inverter circuit is 20ms, the detection period of the control device may be 0.5ms, or 0.2 ms.
As a possible implementation manner, the control device may detect the voltage instantaneous values of the input terminal and the output terminal of the rectification inverter circuit when receiving indication information for instructing the control device to detect the voltage instantaneous values. For example, the control device may detect the voltage instantaneous value when receiving the indication information sent by the rectification inverter circuit.
As a possible implementation, the control device may perform normalization processing on the voltage phase values of the input terminal and the output terminal of the rectification inverter circuit. Illustratively, the control device may normalize the voltage phase values at the input and output to an interval of (-1, 1). Therefore, the control device can compare, judge and analyze the voltage phase values of the input end and the output end conveniently.
S402, the control device performs attenuation processing on the voltage phase value of the output end to obtain a reference value.
As a possible implementation, the control device may determine the product of the voltage phase value at the output terminal and a preset coefficient as the reference value. The preset coefficient is in negative correlation with the harmonic content of the input end of the rectification inverter circuit.
Illustratively, the higher the harmonic content of the input end in the rectification inverter circuit is, the smaller the preset coefficient is, and correspondingly, the smaller the value of the reference value is. The lower the harmonic content of the input end in the rectification inverter circuit is, the larger the preset coefficient is, and correspondingly, the value of the reference value is larger.
For example, the control device may attenuate the voltage phase value of the output terminal by a factor of 0.7, and accordingly, the value of the predetermined coefficient is 0.7. It is assumed that the variation interval of the voltage phase value at the output terminal is (-1,1), and the variation interval at the reference value is (-0.7, 0.7).
In some embodiments, the value of the preset coefficient may be preset, or the preset coefficient may be modified by the control device according to the actual operating condition. It should be noted that, when the reference value is small, the detection method of the rectification inverter circuit is too sensitive, which easily causes malfunction. When the value of the reference value is large, the detection method of the rectification inverter circuit is too slow, so that the detection cannot be successful. Therefore, the value of the second predetermined coefficient should be within a reasonable range.
Illustratively, the reference value may be greater than or equal to 0.5 and less than or equal to 0.9. For example, the preset coefficient may be 0.7. The invention is not limited in this regard.
And S403, comparing the voltage phase value of the input end with a reference value by the control device.
As a possible implementation, the control device may directly compare the magnitude relationship between the voltage phase value at the input terminal and the reference value.
As another possible implementation manner, the control device may determine the magnitude relationship between the voltage phase value of the input terminal and the reference value by determining whether the difference between the voltage phase value of the input terminal and the reference value is smaller than zero.
S404, if the voltage phase value of the input end is smaller than the reference value, timing is started, and the duration of time that the voltage phase value of the input end is smaller than the reference value is recorded.
In the embodiment of the present application, the voltage phase value of the input terminal is smaller than the reference value, which is used to indicate that the voltage phase value of the input terminal may have an abnormality, that is, the voltage of the input terminal may have a power failure or a desynchronization phenomenon, so that the voltage phase value of the input terminal is smaller than the reference value.
It is understood that, in the case where it is judged that there may be an abnormality in the voltage phase value at the input terminal, the control device needs to determine the duration of the abnormality. Therefore, the control device may control the timer to start timing when the voltage phase value of the input terminal is less than the reference value to record a duration for which the voltage phase value of the input terminal is less than the reference value.
S405, if the duration is longer than the preset duration, determining that the rectification inverter circuit is abnormal.
The abnormality includes a power failure at the input terminal, or a voltage phase at the input terminal and a voltage phase at the output terminal are asynchronous.
It should be noted that, in order to improve the accuracy of the detection method provided by the present invention, the preset time duration should be set within a reasonable range. If the preset time is set to be too long, devices in the rectification inverter circuit are easily damaged; if the preset time is too short, the detection method is sensitive, and the detection error is caused, so that the accuracy is reduced.
Illustratively, the predetermined duration is greater than 1/20 and less than 1/4 of the period of the input. For example, when the frequency of the input terminal is 50hz and the period is 20ms, the preset time duration should be greater than 1ms and less than 5 ms.
For another example, the preset time period may also be determined according to the frequency of the input end. For example, assuming that the fluctuation range of the frequency of the input end is 39hz to 55hz, the preset time period may be greater than 0.9ma and less than 1.25 ms.
The invention provides a detection method of a rectification inverter circuit, which obtains a reference value by carrying out attenuation processing on a phase value at an output end, compares a voltage phase value at an input end with the reference value, and determines that the input end of the rectification inverter circuit is in power failure or phase desynchronization when the voltage phase value at the input end is smaller than the reference value and is longer than a preset time duration, thereby realizing the abnormal detection of the power failure or the phase desynchronization of the input end of the rectification inverter circuit.
Alternatively, as shown in fig. 5, step S403 may be embodied as steps S501-S503.
S501, the control device judges whether the voltage phase value of the output end is in an undetected interval.
S502, if the voltage phase value of the output end belongs to the undetected interval, the control device does not compare the voltage phase value of the input end with the reference value.
S503, if the voltage phase value of the output end belongs to the detection interval, the control device compares the voltage phase value of the input end with a reference value, and starts timing when the voltage phase value of the input end is smaller than the reference value.
The voltage instantaneous value of the output end is zero, and the detection interval is an interval except the undetected interval.
For example, the first phase value may be phase 0, pi, 2 pi, … …, etc. assuming that the instantaneous value of the voltage at the output of phase 0, pi, 2 pi, … …, etc. is zero. The undetected interval may be an interval around the first phase value, that is, an interval in which the absolute value of the difference between the voltage phase value of the output terminal and the first phase value is smaller than a preset threshold. For example, the undetected range may be (-0.1. pi., 0.1. pi.), (0.9. pi., 1.1. pi.), etc
It should be noted that, in order to improve the accuracy of the detection method of the present invention, a non-detection interval is set for the zero-crossing point region of the voltage phase value at the output end, that is, the voltage phase value at the input end is not compared with the reference value in the interval. And in the interval with larger absolute value of the voltage phase value, namely the detection interval, the voltage phase value of the input end is compared with the reference value, so that the abnormity of the rectification inverter circuit is accurately detected.
As shown in fig. 6, the present invention provides a detection method for a rectification inverter circuit, which is applied to a control device and includes steps S601 to S609.
S601, starting.
S602, the control device acquires a voltage phase value U of the input endIntoAnd a voltage phase value U of the output terminalGo out。
S603, the control device performs attenuation processing on the voltage phase value of the output end to obtain a reference value UR1。
The reference value is the product of the voltage phase value of the output end and a preset coefficient.
S604, the control device determines whether or not the detection section is present. If yes, go to S605, otherwise go to S602.
As a possible implementation manner, the control device may determine whether the voltage phase value at the output terminal is in the detection interval.
As another possible implementation, the control device may determine whether or not the detection interval is in accordance with the reference value.
S605 and control deviceJudging the voltage phase value U of the input endIntoWhether or not it is less than the reference value UR1. If yes, go to S606, otherwise go to S602.
And S606, controlling the timer to count time by the control device.
S607, the control device judges whether the duration is longer than the preset duration. If so, go to S608, otherwise, go to S606.
The duration is the time length that the voltage phase value of the input end is smaller than the reference value.
And S608, the control device determines that the rectification inverter circuit is abnormal.
And S609, ending.
Based on the embodiment shown in fig. 6, the method and the device can detect the power failure and asynchronous phase abnormality of the input end of the rectification inverter circuit, and improve the safety and reliability of the rectification inverter circuit.
Fig. 7 is a waveform diagram illustrating an exemplary case where the input terminal and the output terminal are phase-synchronized. Voltage phase value U of input terminal in fig. 7IntoAnd a reference value UR1I.e. the voltage at the input and the voltage at the output run synchronously.
Fig. 8 is a waveform diagram when the phases of the voltages at the input terminal and the output terminal are not synchronized. Voltage phase value U of input terminal in fig. 8IntoAnd a reference value UR1Are out of phase. Voltage phase value U of control device to input terminalIntoAnd a reference value UR1Comparing and recording the voltage phase value U of the input endIntoLess than reference value UR1The duration of (c). And when the duration is longer than the preset duration, the control device determines that the rectification inverter circuit is abnormal. For example, when the duration is longer than T, the control device determines that an abnormality occurs in the rectifying inverter circuit.
It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present invention.
The following are embodiments of the apparatus of the invention, reference being made to the corresponding method embodiments described above for details which are not described in detail therein.
Based on the control device shown in fig. 3, the control device 300 is used to implement the detection method of the rectifying inverter circuit described in the above embodiment. The control device 300 includes: a communication module 301 and a processing module 302.
The communication module 301 is configured to obtain voltage phase values of an input end and an output end of the rectification inverter circuit;
the processing module 302 is configured to perform attenuation processing on the voltage phase value of the output end to obtain a reference value; comparing the voltage phase value of the input end with a reference value, if the voltage phase value of the input end is smaller than the reference value, starting timing, and recording the duration of time that the voltage phase value of the input end is smaller than the reference value; and if the duration is longer than the preset duration, determining that the rectification inverter circuit is abnormal, wherein the abnormality comprises the power failure of the input end, or the voltage phase of the input end and the voltage phase of the output end are asynchronous.
In a possible implementation manner, the communication module 301 is specifically configured to obtain a voltage instantaneous value at the input end and a voltage effective value at the input end; the processing module 302 is specifically configured to determine a ratio of the instantaneous voltage value at the input end to the effective voltage value at the input end as the voltage phase value at the input end.
In a possible implementation manner, the obtaining module 301 is specifically configured to obtain the voltage phase value at the output end through a phase-locked loop.
In a possible implementation manner, the processing module 302 is specifically configured to determine, as a reference value, a product of a voltage phase value at the output end and a preset coefficient, where the preset coefficient is inversely related to a harmonic content at the input end of the rectification inverter circuit.
In a possible implementation manner, the processing module 302 is specifically configured to determine whether a voltage phase value at the output end is in an undetected interval; if the voltage phase value of the output end belongs to the undetected interval, comparing the voltage phase value of the input end with the reference value; if the voltage phase value of the output end belongs to the detection interval, comparing the voltage phase value of the input end with a reference value, and starting timing when the voltage phase value of the input end is smaller than the reference value; the undetected interval is an interval in which the absolute value of the difference between the voltage phase value of the output end and the first phase value is smaller than a preset threshold value, the first phase value is a phase value when the instantaneous value of the voltage of the output end is zero, and the detection interval is an interval except the undetected interval.
In a possible implementation manner, the processing module 302 is specifically configured to determine the preset time duration according to the frequency and the period of the output end.
In a possible implementation manner, the rectification inverter circuit is a three-bridge-arm topology circuit, the three-bridge-arm topology circuit includes a first bridge arm, a first capacitor, a second bridge arm and a third bridge arm, which are sequentially connected in parallel, the first bridge arm includes a first switch and a second switch tube, the second bridge arm includes a third switch and a fourth switch tube, the third bridge arm includes a fifth switch and a sixth switch tube, a midpoint of the first bridge arm and a midpoint of the second bridge arm are connected to the input end, and a midpoint of the third bridge arm and a midpoint of the second bridge arm are connected to the output end.
Fig. 9 is a schematic structural diagram of another control device according to an embodiment of the present invention. As shown in fig. 9, the control device 300 of this embodiment includes: a processor 901, a memory 902 and a computer program 903 stored in said memory 902 and operable on said processor 901. The processor 901, when executing the computer program 903, implements the steps in the various power control system method embodiments described above, such as the steps shown in fig. 4, 5, and 6. Alternatively, the processor 901 implements the functions of each module/unit in each device embodiment described above when executing the computer program 903, for example, the functions of the communication module 301 and the processing module 302 shown in fig. 3.
Illustratively, the computer program 903 may be partitioned into one or more modules/units that are stored in the memory 902 and executed by the processor 901 to implement the present invention. The one or more modules/units may be a series of computer program instruction segments capable of performing specific functions, which are used to describe the execution of the computer program 903 in the control device 300. For example, the computer program 903 may be divided into the communication module 301 and the processing module 302 shown in fig. 3.
The Processor 901 may be a Central Processing Unit (CPU), other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic device, discrete hardware component, or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The memory 902 may be an internal storage unit of the control device 300, such as a hard disk or a memory of the control device 300. The memory 902 may also be an external storage device of the control apparatus 300, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), and the like, provided on the control apparatus 300. Further, the memory 902 may also include both an internal storage unit and an external storage device of the control apparatus 300. The memory 902 is used for storing the computer programs and other programs and data required by the control device. The memory 902 may also be used to temporarily store data that has been output or is to be output.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-mentioned division of the functional units and modules is illustrated, and in practical applications, the above-mentioned function distribution may be performed by different functional units and modules according to needs, that is, the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-mentioned functions. Each functional unit and module in the embodiments may be integrated in one processing unit, or each unit may exist alone physically, or two or more units are integrated in one unit, and the integrated unit may be implemented in a form of hardware, or in a form of software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working processes of the units and modules in the system may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and reference may be made to the related descriptions of other embodiments for parts that are not described or illustrated in a certain embodiment.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
In the embodiments provided in the present invention, it should be understood that the disclosed apparatus/terminal and method may be implemented in other ways. For example, the above-described apparatus/terminal embodiments are merely illustrative, and for example, the division of the modules or units is only one logical division, and there may be other divisions when actually implemented, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated modules/units, if implemented in the form of software functional units and sold or used as separate products, may be stored in a computer readable storage medium. Based on such understanding, all or part of the flow in the method of the above embodiments may be implemented by a computer program, which may be stored in a computer readable storage medium, and when the computer program is executed by a processor, the steps of the method embodiments of the power control system may be implemented. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, an executable file or some intermediate form, etc. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, usb disk, removable hard disk, magnetic disk, optical disk, computer Memory, Read-Only Memory (ROM), Random Access Memory (RAM), electrical carrier wave signals, telecommunications signals, software distribution medium, and the like. It should be noted that the computer readable medium may contain other components which may be suitably increased or decreased as required by legislation and patent practice in jurisdictions, for example, in some jurisdictions, computer readable media which may not include electrical carrier signals and telecommunications signals in accordance with legislation and patent practice.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present invention, and are intended to be included within the scope of the present invention.
Claims (10)
1. A detection method for a rectification inverter circuit is characterized by comprising the following steps:
acquiring voltage phase values of an input end and an output end of a rectification inverter circuit;
carrying out attenuation processing on the voltage phase value of the output end to obtain a reference value;
comparing the voltage phase value of the input end with the reference value, if the voltage phase value of the input end is smaller than the reference value, starting timing, and recording the duration of time that the voltage phase value of the input end is smaller than the reference value;
and if the duration is longer than the preset duration, determining that the rectification inverter circuit is abnormal, wherein the abnormality comprises the power failure of an input end, or the voltage phase of the input end is asynchronous with the voltage phase of the output end.
2. The method of claim 1, wherein obtaining the voltage phase value of the input terminal of the rectifying inverter circuit comprises:
acquiring a voltage instantaneous value of the input end and a voltage effective value of the input end;
and determining the ratio of the instantaneous value of the voltage at the input end to the effective value of the voltage at the input end as the voltage phase value at the input end.
3. The method of claim 1, wherein obtaining the voltage phase value of the output terminal of the rectifying inverter circuit comprises:
and acquiring a voltage phase value of the output end through a phase-locked loop.
4. The method of claim 1, wherein said attenuating the voltage phase value of the output to obtain a reference value comprises:
and determining the product of the voltage phase value of the output end and a preset coefficient as a reference value, wherein the preset coefficient is in negative correlation with the harmonic content of the input end of the rectification inverter circuit.
5. The method of claim 1, wherein comparing the voltage phase value of the input terminal with the reference value and starting timing if the voltage phase value of the input terminal is less than the reference value comprises:
judging whether the voltage phase value of the output end is in an undetected interval or not;
if the voltage phase value of the output end belongs to the undetected interval, comparing the voltage phase value of the input end with the reference value;
if the voltage phase value of the output end belongs to a detection interval, comparing the voltage phase value of the input end with the reference value, and starting timing when the voltage phase value of the input end is smaller than the reference value;
the undetected interval is an interval in which an absolute value of a difference between a voltage phase value of the output terminal and a first phase value is smaller than a preset threshold, the first phase value is a phase value when an instantaneous voltage value of the output terminal is zero, and the detected interval is an interval other than the undetected interval.
6. The method of claim 1, wherein the preset duration is greater than 1/20 and less than 1/4 cycles of the input.
7. The method according to claim 1, wherein the rectification inverter circuit is a three-bridge-arm topology circuit, the three-bridge-arm topology circuit comprises a first bridge arm, a first capacitor, a second bridge arm and a third bridge arm which are sequentially connected in parallel, the first bridge arm comprises a first switch and a second switch tube, the second bridge arm comprises a third switch and a fourth switch tube, the third bridge arm comprises a fifth switch and a sixth switch tube, a midpoint of the first bridge arm and a midpoint of the second bridge arm are connected with the input end, and a midpoint of the third bridge arm and a midpoint of the second bridge arm are connected with the output end.
8. A detection device for a rectification inverter circuit, comprising a memory, a processor and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the method according to any one of claims 1 to 6 when executing the computer program.
9. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 6.
10. An uninterruptible power supply, comprising
The detecting device of the rectifying inverter circuit according to claim 8; and the number of the first and second groups,
the rectification inverter circuit comprises a rectification module and an inverter module;
the first end of the rectifying module is connected with the input end, the second end of the rectifying module is connected with the first end of the inverting module, and the rectifying module is used for converting a first alternating current signal input by the input end into a direct current signal;
and the second end of the inverter module is connected with the output end and used for converting the direct current signal into a second alternating current signal to supply power to a load.
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