CN114338953A

CN114338953A - Video processing circuit, video processing method and electronic device

Info

Publication number: CN114338953A
Application number: CN202111626915.XA
Authority: CN
Inventors: 庄文龙
Original assignee: Vivo Mobile Communication Co Ltd
Current assignee: Vivo Mobile Communication Co Ltd
Priority date: 2021-12-28
Filing date: 2021-12-28
Publication date: 2022-04-12

Abstract

The application discloses a video processing circuit, a video processing method and electronic equipment, wherein the video circuit comprises a main control chip and a video processing chip, and the main control chip is connected with the video processing chip; the main control chip is used for acquiring first video information based on the information to be processed; the video processing chip is used for performing frame insertion processing on the first video information and outputting second video information under the condition that the first video information meets the preset condition.

Description

Video processing circuit, video processing method and electronic device

Technical Field

The application belongs to the technical field of video processing, and particularly relates to a processing circuit, a video processing method and electronic equipment.

Background

At present, in order to make a video picture viewed more smoothly and improve the visual effect of the video picture, an interpolation technique may be used to perform interpolation on the video picture. The frame interpolation technology is to interpolate one or more intermediate frames between video frames of adjacent video pictures to convert a video from a low frame rate to a high frame rate. However, the current video frame interpolation has poor effect.

Disclosure of Invention

An object of the embodiments of the present application is to provide a processing circuit, a video processing method, and an electronic device, which can improve a video frame insertion effect.

In a first aspect, an embodiment of the present application provides a video processing circuit, which is characterized by including a main control chip and a video processing chip, wherein the main control chip is connected to the video processing chip; the main control chip is used for acquiring first video information based on the information to be processed; the video processing chip is used for performing frame insertion processing on the first video information and outputting second video information under the condition that the first video information meets the preset condition.

In a second aspect, an embodiment of the present application provides a video processing method, which is applied to the video processing circuit in the first aspect, and the method includes: the main control chip acquires first video information based on the information to be processed; and under the condition that the first video information meets the preset condition, the video processing chip performs frame insertion processing on the first video information and outputs second video information.

In a third aspect, an embodiment of the present application provides a video processing circuit, which is characterized by including a main control chip and a video processing chip, where the main control chip includes an obtaining unit and a first interface; the video processing chip comprises a second interface and a frame inserting unit; an acquisition unit configured to acquire first video information based on information to be processed; the acquisition unit is connected with a first interface, and the first interface is used for outputting first video information; the second interface is respectively connected with the first interface and the frame insertion unit; and the frame interpolation unit is used for performing frame interpolation processing on the first video information and outputting second video information under the condition that the first video information meets the preset condition.

In a fourth aspect, an embodiment of the present application provides an electronic device, which is characterized by comprising a display screen and the video processing circuit of the first aspect, wherein the display screen is connected to the video processing circuit; the display screen is used for displaying the video information processed by the video processing circuit.

In a fifth aspect, an embodiment of the present application provides an electronic device, which is characterized by comprising a display screen and the video processing circuit of the second aspect, wherein the display screen is connected to the video processing circuit; the display screen is used for displaying the video information processed by the video processing circuit.

In a sixth aspect, the present application provides a computer program product, which is stored in a storage medium and executed by at least one processor to implement the method according to the second aspect.

The scheme provided by the embodiment of the application comprises a main control chip and a video processing chip, wherein the main control chip is connected with the video processing chip; the main control chip is used for acquiring first video information based on the information to be processed; the video processing chip is used for performing frame insertion processing on the first video information and outputting second video information under the condition that the first video information meets a preset condition. Therefore, the method and the device for frame interpolation can flexibly perform frame interpolation processing on the first video information according to the content of the first video information, can effectively avoid that the first video information contains other dynamic layers to influence the motion calculation of the picture of the video, and improve the video frame interpolation effect. In addition, the embodiment of the application carries out frame insertion processing through the video processing chip, so that the power consumption of the main control chip can be reduced, the frame insertion efficiency is improved, and the real-time performance of frame insertion videos is ensured.

Drawings

Fig. 1 is a schematic structural diagram of a video processing circuit according to an embodiment of the present disclosure;

fig. 2 is a schematic flowchart of a video processing method according to an embodiment of the present application;

fig. 3 is a second schematic structural diagram of a video processing circuit according to an embodiment of the present application;

fig. 4 is a third schematic structural diagram of a video processing circuit according to an embodiment of the present application;

FIG. 5 is a fourth schematic diagram of a video processing circuit according to an embodiment of the present disclosure;

FIG. 6 is a schematic structural diagram of an electronic device provided in an embodiment of the present application;

fig. 7 is a second schematic structural diagram of an electronic device according to an embodiment of the present application;

fig. 8 is a third schematic structural diagram of an electronic device according to an embodiment of the present application;

fig. 9 is a hardware schematic diagram of an electronic device provided in an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described clearly below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments that can be derived by one of ordinary skill in the art from the embodiments given herein are intended to be within the scope of the present disclosure.

The terms first, second and the like in the description and in the claims of the present application are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It will be appreciated that the data so used may be interchanged under appropriate circumstances such that embodiments of the application may be practiced in sequences other than those illustrated or described herein, and that the terms "first," "second," and the like are generally used herein in a generic sense and do not limit the number of terms, e.g., the first term can be one or more than one. In addition, "and/or" in the specification and claims means at least one of connected objects, a character "/" generally means that a preceding and succeeding related objects are in an "or" relationship.

In the related frame interpolation technology, frame interpolation processing is directly performed on received video information, however, since the video information generally includes video image information and interface image information, and the interface image information includes image information separable from the video image information, changes in this separable interface image information may affect motion calculation of a video frame, and affect the frame interpolation effect. The video processing circuit in the embodiment of the application can generate the first video information meeting different preset conditions according to whether the video image information and the interface image information in the information to be processed are separable or not, so that the frame insertion processing can be flexibly performed on the first video information according to the content of the first video information, the situation that the motion calculation of the picture of the video is influenced by the fact that other dynamic layers are contained in the first video information can be effectively avoided, and the video frame insertion effect is improved. In addition, the embodiment of the application carries out frame insertion processing through the video processing chip, so that the power consumption of the main control chip can be reduced, the frame insertion efficiency is improved, and the real-time performance of frame insertion videos is ensured.

The video processing circuit provided by the embodiment of the present application is described in detail by specific embodiments with reference to the accompanying drawings.

Fig. 1 is a schematic diagram of a possible structure of a video processing circuit according to an embodiment of the present disclosure.

The video processing circuit 300 comprises a main control chip 310 and a video processing chip 320, wherein the main control chip 310 is connected with the video processing chip 320; the main control chip 310 is configured to obtain first video information based on the information to be processed; the video processing chip 320 is configured to perform frame interpolation on the first video information and output second video information when the first video information meets a preset condition.

In the embodiment of the application, the information to be processed may include video image information and interface image information.

Illustratively, the video image information may be: video image information corresponding to the original video data decoded by the decoder.

Illustratively, the video image information may be: the video information that has already been played, the video information that is playing or the video information that has not been played in the electronic equipment.

Illustratively, the interface image information may include at least one of: bullet screen image information, advertisement image information, message popup window image information, control image information, progress bar image information, status bar image information and station caption image information.

It is to be understood that, in general, the interface image information may or may not be separable from the video image information.

Illustratively, the interface image information may include: first interface image information and second interface image information.

Wherein the first interface image information may include at least one of: the message popup image information, the control image information, the progress bar image information, the status bar image information and the station caption image information.

The second interface image information may be: the third party application adds image information (e.g., the above-described bullet screen image information, advertisement image information) to the video image information.

It is to be understood that, in general, the first interface image information may be separable from the video image information, and the second interface image information may be separable from the video image information, or may not be separable.

Therefore, the main control chip can acquire different first video information according to whether the video image information and the interface image information are separable or not, namely, the main control chip can be based on different information to be processed, the acquired first video information can meet different preset conditions, so that the video processing chip can flexibly perform frame insertion processing on the first video information according to the preset conditions met by the first video information, the situation that the first video information contains other dynamic layers to influence the motion calculation of the picture of the video is effectively avoided, and the video frame insertion effect is improved.

Optionally, the preset condition includes a first preset condition or a second preset condition.

The first preset condition is as follows: the first video information comprises only video image information.

The second preset condition is as follows: the first video information comprises video image information and interface image information, and the display area proportion of the interface image information is smaller than a preset threshold value.

Illustratively, the display area ratio (hereinafter referred to as a first ratio) of the interface image information is: and the display area proportion of the interface image information in the video picture in which the interface image information is positioned.

For example, the preset threshold may be 30%, 50%, or other possible thresholds, which are not limited in the embodiments of the present application.

The video processing circuit provided by the embodiment of the application comprises a main control chip and a video processing chip, wherein the main control chip is connected with the video processing chip; the main control chip is used for acquiring first video information based on the information to be processed; the video processing chip is used for performing frame insertion processing on the first video information and outputting second video information under the condition that the first video information meets a preset condition. Therefore, the method and the device for frame interpolation can flexibly perform frame interpolation processing on the first video information according to the content of the first video information, can effectively avoid that the first video information contains other dynamic layers to influence the motion calculation of the picture of the video, and improve the video frame interpolation effect. In addition, the embodiment of the application carries out frame insertion processing through the video processing chip, so that the power consumption of the main control chip can be reduced, the frame insertion efficiency is improved, and the real-time performance of frame insertion videos is ensured.

Optionally, in this embodiment of the application, the main control chip 310 is specifically configured to obtain the first video information, the first interface image information, and the second interface image information based on the information to be processed.

The main control chip 310 is further configured to fuse the first interface image information and the second interface image information, and output fused interface image information;

the video processing chip 320 is further configured to synthesize the second video information and the fusion interface image information, and output third video information.

Or, in this embodiment of the application, the main control chip is specifically configured to obtain the first video information, the first interface image information, and the second interface image information based on the information to be processed.

The main control chip 310 is further configured to fuse the first interface image information, the second interface image information, and the second video information, and output third video information.

It is understood that the first interface image information and the second interface image information are both the interface image information.

It is understood that the first video information is the video image information. That is to say, the first video information in the embodiment of the present application satisfies the first preset condition.

It is understood that, in the embodiment of the present application, the interface image information (i.e., including the first interface image and the second interface image information) and the video image information (i.e., the first video information) are in a separable state. The first interface image information is other interface image information outside the video, and the second interface image information is interface image information in the video. The video is the video corresponding to the information to be processed.

In other words, the dynamic layer corresponding to the interface image information is separated from the video layer corresponding to the video image information, and in this case, the motion calculation of the picture of the video corresponding to the video layer cannot be affected due to the change of the dynamic layer only when the video layer is subjected to the frame interpolation. Therefore, the video layer needs to be separated from the dynamic layer, so that the frame interpolation effect can be greatly improved.

Illustratively, the dynamic layer generally includes: and the Alpha calculation layer is used for recovering the video layer and the dynamic layer. Therefore, when the main control chip obtains that the first video information and the interface image information (including the first interface image information and the second interface image information) in the information to be processed can be separated, all the interface image information can be fused through the main control chip, and the fused interface image information is output. The video processing chip can synthesize the second video information and the fusion interface image information based on the Alpha calculation layer, and output third video information.

Illustratively, the dynamic layer generally includes: and the Alpha calculation layer is used for recovering the video layer and the dynamic layer. Therefore, when the main control chip obtains that the first video information and the interface image information (including the first interface image information and the second interface image information) in the information to be processed can be separated, the main control chip can send the first video information to the video processing chip, and the video processing chip performs frame insertion processing on the first video information.

And for other interface image information (including the first interface image information, the second interface image information, and Alpha calculation image information (for restoring the video image information and the interface image information)) except the first video information (i.e., the video image information) in the information to be processed, the following processing modes are included, but not limited to:

in a first possible example, the main control chip may fuse all interface image information and output the fused interface image information to the video processing chip, and the video processing chip may calculate image information based on Alpha, synthesize the second video information and the fused interface image information, and output third video information, so that the third video information may be displayed by the display screen.

In a second possible example, the video processing chip sends second video information obtained by performing frame insertion processing on the first video information to the main control chip, and then the main control chip may calculate image information based on Alpha, synthesize the second video information with all other interface image information (including the first interface image information and the second interface image information), and output third video information, so that the third video information may be displayed by the display screen.

In this way, the video image information (i.e. the first video information) is separated from the interface image information, and only the video image information is subjected to frame interpolation processing, so that the influence of the change of the interface image information on the motion calculation of the video picture corresponding to the video image information is avoided, and the frame interpolation effect of the video image information (i.e. the video layer) can be improved.

In addition, compared with the first possible example, in the second possible example, the main control chip performs Alpha overlay calculation on the second video information obtained after frame insertion and the interface image information, which is easier and more accurate than performing the Alpha overlay calculation at the video processing chip side, and the frame insertion effect is further improved.

Optionally, in this embodiment of the application, the main control chip is specifically configured to obtain, based on the information to be processed, a video to be processed and first interface image information, where the video to be processed includes the video image information and second interface image information;

the main control chip is also used for synthesizing the video to be processed and the first interface image information to generate first video information under the condition that the video image information and the second interface image information are inseparable.

It can be understood that the first video information includes video image information, first interface image information and second interface image information, and the video image information and the second interface image information are inseparable.

It can be understood that the layer corresponding to the video to be processed and the layer corresponding to the first interface image information are in a separable state, and therefore, before the video to be processed and the first interface image information are sent to the video processing chip, the main control chip needs to synthesize the video to be processed and the first interface image information.

Illustratively, the first interface image information includes progress bar image information and status bar image information, and the second interface image information includes pop-up screen image information, so that the main control chip is required to synthesize the progress bar image information, the status bar image information, and the video to be processed (including the pop-up screen image information and the video image information) to generate the first video information.

Optionally, in this embodiment of the application, the main control chip is specifically configured to obtain a video to be processed based on information to be processed; the video to be processed comprises video image information and second interface image information;

the main control chip is specifically used for taking the video to be processed as the first video information under the condition that the video image information and the second interface image information are inseparable.

It is understood that the interface image information in the embodiment of the present application includes only the second interface image information, that is, the image information added to the video image information by the third-party application (for example, the bullet screen image information, the advertisement image information).

According to the scheme of the embodiment of the application, because the video image information and the second interface image information can not be separated, the video image information and the second interface image information do not need to be synthesized by the main control chip, and only the main control chip needs to take the video to be processed as the first video information, so that subsequent processing such as frame insertion is continuously carried out.

In addition, when the first video information includes video image information and interface image information, the video processing chip may perform frame interpolation on the first video information according to the frame interpolation policy corresponding to the first ratio. Therefore, the frame insertion strategy can be flexibly adjusted according to the first proportion.

Optionally, the frame interpolation function of the video processing chip is turned off when the first ratio is greater than or equal to the preset threshold.

It can be understood that if the first ratio is too large, the frame cannot be normally interpolated, and therefore, when the first ratio is greater than or equal to the preset threshold, the frame interpolation function of the video processing chip needs to be turned off, that is, the frame interpolation processing is not performed on the first video information.

Illustratively, the preset threshold may be set on the principle that the frame insertion requirement can be met and the video frame insertion effect is improved.

Illustratively, in the case that the first ratio is greater than or equal to the preset threshold, the first video information is directly transmitted to the display screen through the video processing chip.

In example 1, if the preset threshold is 50%, in the case that the first ratio is 60%, the frame insertion function of the video processing chip may be turned off by the main control chip, and the first video information may be directly transmitted to the display screen through the BYPASS mode.

Optionally, when the first ratio is updated from being greater than or equal to the preset threshold to being smaller than the preset threshold, the frame insertion function of the video processing chip is started through the main control chip, and frame insertion processing is performed on the first video information.

In general, when playing a video frame, the first ratio is constantly changed, and therefore, when the first ratio is updated from being greater than or equal to the preset threshold to being smaller than the preset threshold, the frame insertion function of the video processing chip needs to be started.

It can be understood that, when the first ratio is smaller than the preset threshold, it indicates that normal frame interpolation is not affected, so that, by using the frame interpolation function of the video processing chip, frame interpolation operation is performed on the first video information, that is, frame interpolation processing is performed on the first video information, thereby improving the video frame interpolation effect.

Example 2, in combination with example 1, with the video playing, when the first ratio is 30%, the frame insertion function of the video processing chip may be started through the main control chip, and the frame insertion processing is performed on the first video information through the video processing chip, so that a smoother video picture may be displayed on the display screen.

Therefore, according to the embodiment of the application, the frame insertion function in the video processing chip can be flexibly started or closed according to the display area proportion of the interface image information, under the condition that the frame insertion requirement is met, the power consumption is reduced, and the normal playing of the video picture is ensured.

It should be noted that, as the video processing chip sends the video data after frame insertion, or the video data without frame insertion (i.e., the video data transmitted through the BYPASS function (BYPASS) unit), to the display screen for display, the main control chip may dynamically switch the refresh rate of the display screen to adapt to the video frame rate after frame insertion in real time.

As shown in fig. 2, an embodiment of the present application further provides a video processing method, which is applied to the video processing circuit in any of the foregoing embodiments, and the method includes step 101 and step 102.

Step 101, a main control chip acquires first video information based on information to be processed;

and 102, under the condition that the first video information meets the preset condition, the video processing chip performs frame insertion processing on the first video information and outputs second video information.

Optionally, the preset condition includes a first preset condition or a second preset condition:

the first preset condition is as follows: the first video information only comprises video image information;

The video processing method provided by the embodiment of the application can acquire the first video information based on the information to be processed, perform frame insertion processing on the first video information under the condition that the first video information meets the preset condition, and output the second video information. Because the information to be processed comprises the video image information and the interface image information, the frame insertion processing can be flexibly performed on the first video information according to the content of the first video information, the situation that the motion calculation of the picture of the video is affected by the fact that other dynamic layers are contained in the first video information can be effectively avoided, and the video frame insertion effect is improved. In addition, the embodiment of the application carries out frame insertion processing through the video processing chip, so that the power consumption of the main control chip can be reduced, the frame insertion efficiency is improved, and the real-time performance of frame insertion videos is ensured.

Optionally, in this embodiment of the present application, the step 101 includes: step 101a and step 101 b.

Step 101a, a main control chip acquires first video information, first interface image information and second interface image information based on information to be processed;

and step 101b, the main control chip fuses the first interface image information and the second interface image information and outputs fused interface image information.

After the above step 102, step 103 is included.

And 103, synthesizing the second video information and the fusion interface image information by the video processing chip, and outputting third video information.

It can be understood that, in the embodiment of the present application, the first video information satisfies the first preset condition.

It can be understood that the interface image information and the video image information in the information to be processed can be separated.

Therefore, under the condition that the interface image information and the video image information are separable, the interface image information and the video image information are separated, and only the video image information is subjected to frame interpolation processing, so that the influence of the change of the interface image information on the motion calculation of the picture of the video image information is avoided, and the frame interpolation effect of the video can be improved.

Optionally, in this embodiment of the present application, the step 101 includes: and step 101 c.

And step 101c, the main control chip acquires first video information, first interface image information and second interface image information based on the information to be processed.

After step 102, step 104 is included.

And 104, the main control chip synthesizes the first interface image information, the second interface image information and the second video information and outputs third video information.

Therefore, under the condition that the interface image information and the video image information can be separated, the interface image information does not need to be sent to the video processing chip, the video processing chip is only needed to perform frame insertion processing on the video image information and feed back the video image information to the main control chip, and the main control chip directly synthesizes the obtained second video information and the interface image information and then transmits the second video information and the interface image information to the display screen, so that the power consumption is saved. Meanwhile, the main control chip performs Alpha superposition calculation on the second video information and the interface image information obtained by frame insertion, and the Alpha superposition calculation is easier and more accurate than that performed at the video processing chip end, so that the frame insertion effect is further improved.

Optionally, in this embodiment of the present application, the step 101 includes: step 101d and step 101 f.

Step 101d, the main control chip acquires a video to be processed and first interface image information based on the information to be processed, wherein the video to be processed comprises the video image information and second interface image information;

and step 101f, under the condition that the video image information and the second interface image information are inseparable, the main control chip synthesizes the video to be processed and the first interface image information to generate first video information.

It can be understood that, in the embodiment of the present application, the first video information satisfies the second preset condition.

It can be understood that there is an inseparable condition between the interface image information and the video image information in the information to be processed.

In this way, since the video image information and the interface image information are inseparable, the frame interpolation processing is directly performed on the first video information including the interface image information, and the frame interpolation effect can also be improved to a certain extent, so that the video picture after the frame interpolation processing is observed more smoothly.

Optionally, in this embodiment of the present application, the step 101 includes a step 101 g.

Step 101g, the main control chip acquires a video to be processed based on the information to be processed, and the video to be processed is used as first video information;

the video to be processed comprises video image information and second interface image information, and the video image information and the second interface image information cannot be separated.

It can be understood that the interface image information and the video image information in the information to be processed are not separable.

Therefore, the video image information and the interface image information can not be separated, and the display area proportion of the interface image information is smaller than the preset threshold value, so that the influence on the frame interpolation of the video image is small, and therefore, the frame interpolation processing is directly carried out on the first video information comprising the interface image information, and the frame interpolation effect can be improved to a certain extent.

Optionally, in this embodiment of the present application, after step 101f, or after step 101g, step 102 includes:

step 102a, the main control chip detects a first proportion, and closes a frame insertion function of the video processing chip under the condition that the first proportion is greater than or equal to a preset threshold value;

and 102b, under the condition that the first proportion is updated to be smaller than the preset threshold value from being larger than or equal to the preset threshold value, starting a frame inserting function of the video processing chip by the main control chip, and performing frame inserting processing on the first video information.

Therefore, according to the embodiment of the application, the frame insertion function in the video processing chip can be flexibly started or closed according to the first proportion, under the condition that the frame insertion requirement is met, the power consumption is reduced, and the normal playing of video pictures is ensured.

The video processing scheme provided by the embodiment of the application can be applied to another video processing circuit.

Fig. 3 is a schematic diagram of a possible video processing circuit structure. Specifically, the video processing circuit includes: the system comprises a main control chip (AP), an Application Processor (AP), a video processing chip and a display screen.

Illustratively, the main control chip may include: a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a Display Processing Unit (DPU), a storage Unit (e.g., Dynamic Random Access Memory (DRAM)), and an Interface (e.g., Mobile Industry Processor Interface (MIPI)) transmitting signal line TX); wherein, the number of DPUs and MIPI TX is at least one.

Illustratively, the acquisition unit and/or the fusion unit may be integrated in the display processing unit.

Illustratively, the video processing chip may be an inter-frame stand-alone chip.

Illustratively, the video processing chip may include: the Mobile communication system comprises a CPU, a Digital Signal Processor (DSP), a Mobile Industry Processor Interface (MIPI) receiving Signal line RX, a BYPASS function (BYPASS) unit, a fusion unit (such as a MIXER (MIXER)), a MEMC and an MIPI TX Interface. The number of the MIPI RX interfaces is at least one, and the frame interpolation unit may be a Motion Estimation and Motion Compensation (MEMC) module.

Illustratively, the display screen may include: MIPI RX interface.

For example, the main control chip may be configured to, when the information to be processed includes the interface image information, transmit the video image information and/or the interface image information to the video processing chip according to whether the video image information and the interface image information in the information to be processed are separable.

Illustratively, the video processing chip may be configured to perform frame interpolation processing on video image information, and may also be configured to fuse the video image information and interface image information.

And the display screen can be used for displaying the video pictures subjected to the frame interpolation processing and the video pictures not subjected to the frame interpolation processing.

For example, as shown in fig. 3, the main control chip includes 2 MIPI interfaces, which are a first interface (MIPI TX1) and a third interface (MIPI TX2), respectively; the video processing chip comprises 3 MIPI interfaces, namely a second interface (MIPI RX1), a fourth interface (MIPI RX2) and a fifth interface (MIPI TX 3).

Referring to fig. 3, a video processing circuit provided in an embodiment of the present application includes a main control chip 310 and a video processing chip 320, where the main control chip includes an obtaining unit 311 and a first interface 312; the video processing chip comprises a second interface 321 and a frame insertion unit 322;

an obtaining unit 311 configured to obtain first video information based on information to be processed;

the obtaining unit 311 is connected to the first interface 312, and the first interface 312 is configured to output first video information;

the second interface 321 is respectively connected with the first interface 312 and the frame insertion unit 322;

the frame interpolation unit 322 is configured to perform frame interpolation processing on the first video information and output second video information when the first video information meets a preset condition.

For example, the first interface 312 and the second interface 321 may both adopt MIPI interfaces.

Illustratively, the frame interpolation unit 322 may employ a motion estimation and motion compensation unit (i.e., a MEMC unit).

Illustratively, the information to be processed may be stored in a storage unit (e.g., a DRAM), and the obtaining unit 311 may be connected to the storage unit, so that the obtaining unit 311 may obtain the first video information through the storage unit and sequentially pass through the first interface 312 and the second interface 321 to send the first video information to the frame insertion unit 322, and then the frame insertion unit 322 may flexibly process the first video information according to whether the first video information satisfies a preset condition.

Therefore, the frame interpolation unit in the video processing chip can flexibly perform frame interpolation processing on the first video information according to the preset condition met by the first video information, the frame interpolation is not influenced by the change of the interface image information, and the video frame interpolation effect is improved.

Optionally, in this embodiment of the application, the preset condition includes a first preset condition or a second preset condition:

Under the condition that the first video information meets a first preset condition and video image information in the video to be processed is separable from interface image information (the interface image information comprises the first interface image information and/or the second interface image information), the scheme of the application can be completed through the following two possible implementation manners.

Optionally, in a first possible implementation manner, referring to fig. 3 in this embodiment of the application, the obtaining unit 311 is further configured to obtain first interface image information and second interface image information based on a video to be processed;

the main control chip 310 further includes: the first fusion unit 313 and the third interface 314, wherein the first fusion unit 313 is connected with the acquisition unit 311 and the third interface 314 respectively;

the first fusion unit 313 is configured to fuse the first interface image information and the second interface image information, and output fused interface image information;

the video processing chip 320 further includes a fourth interface 323 and a second fusing unit 324;

the third interface 314 is connected with the fourth interface 323, and the second fusion unit 324 is respectively connected with the fourth interface 323 and the frame insertion unit 322;

the second fusion unit 324 is configured to synthesize the second video information and the fusion interface image information, and output third video information.

It can be understood that, in the embodiment of the present application, the first video information satisfies the first preset condition, and the video image information in the video to be processed is separable from the interface image information. The interface image information includes first interface image information and second interface image information.

Illustratively, the first and

second fusion units

313 and 324 may each employ a mixer.

Illustratively, the third interface 314 and the fourth interface 323 may both employ MIPI interfaces.

Illustratively, the video processing chip 320 further includes a fifth interface and BYPASS function (BYPASS) unit (hereinafter referred to as a BYPASS unit).

Illustratively, the video processing circuitry is coupled to a display screen 330, the display screen 330 including a sixth interface.

Illustratively, the bypass unit is connected with the second interface 321 and the fifth interface, respectively, and the fifth interface is connected with the sixth interface. In this way, the first video information can be sent to the fifth interface through the bypass unit without frame insertion, and thus displayed by the display screen.

In one possible example, the obtaining unit 311 may include two sub-obtaining units, which are a first sub-obtaining unit and a second sub-obtaining unit, respectively, where the first sub-obtaining unit is connected to the storage unit and the first interface, respectively, the first sub-obtaining unit obtains the first video information based on the video to be processed in the storage unit, and the first interface is connected to the frame insertion unit through the second interface; and the frame interpolation unit performs frame interpolation processing on the first video information and outputs second video information.

The second sub-acquisition unit is respectively connected with the storage unit and the first fusion unit 313, the second sub-acquisition unit acquires first interface image information and second interface image information based on a video to be processed in the storage unit, the first fusion unit 313 fuses the first interface image information and the second interface image information to output fusion interface image information, the third interface 314 is respectively connected with the first fusion unit 313 and the fourth interface 323, the second fusion unit 324 is respectively connected with the fourth interface 323 and the frame insertion unit 322, the second fusion unit 324 is used for synthesizing the second video information and the fusion interface image information to acquire third video information, and then the third video information is sent to the display screen sequentially through the fifth interface and the sixth interface.

In another possible example, referring to fig. 3, the obtaining unit 311 is connected to the storage unit, the first interface 312, and the first fusing unit 313, respectively, and obtains the first video information, the first interface image information, and the second interface image information based on the video to be processed in the storage unit; the first fusion unit 313 fuses the first interface image information and the second interface image information and outputs fused interface image information; the second interface 321 is connected to the first interface 312 and the frame interpolation unit 322, respectively, and the frame interpolation unit performs frame interpolation processing on the first video information and outputs second video information; the third interface 314 is connected to the first fusion unit 313 and the fourth interface 323, the second fusion unit 324 is connected to the fourth interface 323 and the frame interpolation unit 322, and the second fusion unit synthesizes the second video information with the fusion interface image information and outputs the third video information. The second fusing unit 324 is connected to the display screen 330 through a fifth interface, so that the second fusing unit 324 outputs the third video information to the display screen, thereby displaying the video image information processed by frame insertion.

Optionally, in a second possible implementation manner, as shown in fig. 4, in this embodiment of the application, the obtaining unit 311 is further configured to obtain first interface image information and second interface image information based on a video to be processed;

the main control chip 310 further includes a first fusion unit 313 and a third interface 314;

the video processing chip 320 further includes a fourth interface 323; the fourth interface 323 is connected with the frame insertion unit 322 and the third interface 314 respectively;

the obtaining unit 311 is connected to the first fusing unit 313 and the third interface 314, respectively;

the first fusion unit 313 is configured to synthesize the first interface image information, the second interface image information, and the second video information, and output third video information.

Illustratively, the second interface 321 may be connected to the fourth interface 323 through a bypass unit, so that the first video information may be sent to the fourth interface through the bypass functional unit without frame insertion, and then is transmitted back to the main control chip by the fourth interface.

Illustratively, the main control chip 310 includes a first storage unit, and the obtaining unit 311 is connected to the first storage unit.

Illustratively, the video processing chip 320 includes a second storage unit, and the fourth interface 323 is connected to the frame interpolation unit 322 through the second storage unit.

In one possible example, the obtaining unit may include two sub-obtaining units, which are a first sub-obtaining unit and a second sub-obtaining unit, respectively, where the first sub-obtaining unit is connected to the first storage unit and the first interface 312, the first sub-obtaining unit obtains the first video information based on the video to be processed in the first storage unit, and the first interface 312 is connected to the frame insertion unit 322 through the second interface 321; the frame interpolation unit 322 performs frame interpolation processing on the first video information and outputs second video information, the fourth interface 323 is connected with the third interface 314 and the frame interpolation unit 322 respectively, and the third interface 314 is connected with the first storage unit. It is understood that the frame insertion unit 322 outputs the second video information to the first storage unit of the host chip 310 through the fourth interface 323.

The second sub-acquiring unit is respectively connected with the first storage unit and the first fusion unit, acquires the first interface image information, the second interface image information and the second video information based on the information in the first storage unit, and the first fusion unit 313 synthesizes the first interface image information, the second interface image information and the second video information and outputs third video information.

In another possible example, referring to fig. 4, the obtaining unit 311 is connected to the first storage unit, the first interface 312, and the first fusing unit 313, respectively, and the obtaining unit 311 obtains the first video information, the first interface image information, and the second interface image information based on the video to be processed in the first storage unit; the second interface 321 is connected to the first interface 312 and the frame interpolation unit 322, respectively, and the frame interpolation unit 322 performs frame interpolation on the first video information and outputs second video information; the fourth interface 323 is connected to the third interface 314 and the frame insertion unit 322, respectively, and the third interface 314 is connected to the first storage unit. It is understood that the frame insertion unit 322 outputs the second video information to the first storage unit of the host chip 310 through the fourth interface 323. The acquisition unit 311 also acquires second video information based on the information in the first storage unit, and the first fusion unit 313 synthesizes the first interface image information, the second interface image information, and the second video information, and outputs third video information.

It should be noted that, in the scheme in this embodiment of the application, after the frame insertion processing is completed to obtain the second video information, the second video information needs to be transmitted back to the main control chip side, and finally, the third video information is sent to the display screen through the main control chip for display, so that power consumption increment caused by two times of interface (for example, MIPI interface) transmission can be reduced, and meanwhile, the main control chip performs Alpha overlay calculation on the second video information and the interface image information obtained by frame insertion, which is easier and more accurate than the Alpha overlay calculation performed at the video processing chip side, and further improves the frame insertion effect.

Optionally, in this embodiment of the application, as shown in fig. 5, the obtaining unit 311 is further configured to obtain, based on the to-be-processed information, a to-be-processed video and first interface image information, where the to-be-processed video includes video image information and second interface image information;

the main control chip 310 further includes a first fusion unit 313, and the first fusion unit 313 is connected to the obtaining unit 311 and the first interface 312 respectively;

the first fusion unit 313 is configured to synthesize the video to be processed and the first interface image information to generate the first video information when the video image information is inseparable from the second interface image information.

It can be understood that the first video information in the embodiment of the present application satisfies the second preset condition.

The acquisition unit may be connected to the storage unit, for example.

Illustratively, the video processing chip 320 further includes a third interface, and the second interface 321 may be connected to the third interface through a bypass unit.

Exemplarily, referring to fig. 5, the video processing circuit is further connected to a display screen 330, the display screen 330 includes a fourth interface, the fourth interface is connected to the third interface, and the display screen is configured to display the second video information.

Therefore, in the embodiment of the application, under the condition that frame insertion is not needed, the first video information can be sent to the display screen through the bypass function unit, the video without frame insertion is displayed by the display screen, and the second video information inserted by the frame insertion unit 322 can also be displayed by the display screen.

In addition, since the video image information and the interface image information are inseparable, the first video information including the interface image information can be directly subjected to the frame interpolation processing, and the frame interpolation effect can be improved to a certain extent.

Optionally, in this embodiment of the application, the obtaining unit is specifically configured to obtain a video to be processed based on the information to be processed; the video to be processed comprises video image information and second interface image information;

the acquisition unit is specifically used for taking the video to be processed as the first video information under the condition that the video image information and the second interface image information are inseparable.

It can be understood that the interface image information in the information to be processed only contains the interface image information added by the third-party application, that is, the second interface image information. And the video image information and the second interface image information in the information to be processed can not be separated.

It should be noted that both the acquiring unit and the fusing unit may be integrated in the display processing unit.

It should be noted that the main control chip may further include a switch unit, where the switch unit is connected to the frame insertion unit, and the switch unit is configured to close a frame insertion function of the frame insertion unit when the first ratio is greater than or equal to a preset threshold; and starting the frame inserting function of the frame inserting unit under the condition that the first proportion is updated to be smaller than the preset threshold value from being larger than or equal to the preset threshold value. Therefore, under the condition that the first video information meets the second preset condition, the video processing circuit of the embodiment of the application can flexibly start or close the frame insertion function in the video processing chip according to the first proportion, and under the condition that the frame insertion requirement is met, the power consumption is reduced, and the normal playing of the video picture is ensured.

The video processing circuit provided by the embodiment of the application comprises a main control chip and a video processing chip, wherein the main control chip comprises an acquisition unit and a first interface; the video processing chip comprises a second interface and a frame inserting unit; an acquisition unit configured to acquire first video information based on information to be processed; the acquisition unit is connected with a first interface, and the first interface is used for outputting first video information; the second interface is respectively connected with the first interface and the frame insertion unit; and the frame interpolation unit is used for performing frame interpolation processing on the first video information and outputting second video information under the condition that the first video information meets the preset condition. Therefore, the method and the device for frame interpolation can flexibly perform frame interpolation processing on the first video information according to the content of the first video information, can effectively avoid that the first video information contains other dynamic layers to influence the motion calculation of the picture of the video, and improve the video frame interpolation effect. In addition, the embodiment of the application carries out frame insertion processing through the video processing chip, so that the power consumption of the main control chip can be reduced, the frame insertion efficiency is improved, and the real-time performance of frame insertion videos is ensured.

As shown in fig. 6, an embodiment of the present application further provides an electronic device, which includes a display screen and the video processing circuit in any of the foregoing embodiments, where the display screen is connected to the video processing circuit; the display screen is used for displaying the video information processed by the video processing circuit.

Optionally, in this embodiment of the application, with reference to fig. 6, as shown in fig. 7, the electronic device further includes a camera; the camera is connected with the main control chip of the video processing circuit and is used for collecting the video image information.

Optionally, in this embodiment of the application, referring to fig. 7, the electronic device further includes a camera; the camera is connected with the acquisition unit of the video processing circuit and is used for acquiring the video image information.

The video frame interpolation apparatus in the embodiment of the present application may be an electronic device, or may be a component in an electronic device, such as an integrated circuit or a chip. The electronic device may be a terminal, or may be a device other than a terminal. The electronic Device may be, for example, a Mobile phone, a tablet computer, a notebook computer, a palm top computer, a vehicle-mounted electronic Device, a Mobile Internet Device (MID), an Augmented Reality (AR)/Virtual Reality (VR) Device, a robot, a wearable Device, an ultra-Mobile personal computer (UMPC), a netbook or a Personal Digital Assistant (PDA), and the like, and may also be a server, a Network Attached Storage (NAS), a Personal Computer (PC), a Television (TV), a teller machine, a self-service machine, and the like, and the embodiments of the present application are not particularly limited.

The video frame interpolation apparatus in the embodiment of the present application may be an apparatus having an operating system. The operating system may be an Android (Android) operating system, an ios operating system, or other possible operating systems, and embodiments of the present application are not limited specifically.

Optionally, as shown in fig. 8, an electronic device 70 is further provided in this embodiment of the present application, and includes a processor 72 and a memory 71, where the memory 71 stores a program or an instruction that can be executed on the processor 72, and when the program or the instruction is executed by the processor 72, the steps of the above-mentioned embodiment of the video processing method are implemented, and the same technical effects can be achieved, and are not described again here to avoid repetition.

It should be noted that the electronic device in the embodiment of the present application includes the mobile electronic device and the non-mobile electronic device described above.

Fig. 9 is a schematic diagram of a hardware structure of an electronic device implementing an embodiment of the present application.

The electronic device 100 includes, but is not limited to: a radio frequency unit 101, a network module 102, an audio output unit 103, an input unit 104, a sensor 105, a display unit 106, a user input unit 107, an interface unit 108, a memory 109, a processor 110, a video processing chip, and the like. The processor 110 is connected to a video processing chip.

Those skilled in the art will appreciate that the electronic device 100 may further comprise a power source (e.g., a battery) for supplying power to various components, and the power source may be logically connected to the processor 110 through a power management system, so as to implement functions of managing charging, discharging, and power consumption through the power management system. The electronic device structure shown in fig. 9 does not constitute a limitation of the electronic device, and the electronic device may include more or less components than those shown, or combine some components, or arrange different components, and thus, the description is not repeated here.

The processor 110 obtains the first video information based on the information to be processed.

And the video processing chip is used for performing frame insertion processing on the first video information and outputting second video information under the condition that the first video information meets the preset condition.

According to the electronic device provided by the embodiment of the application, the electronic device can acquire the first video information based on the information to be processed, and perform frame insertion processing on the first video information and output the second video information under the condition that the first video information meets the preset condition. Because the information to be processed comprises the video image information and the interface image information, the frame insertion processing can be flexibly performed on the first video information according to the content of the first video information, the situation that the motion calculation of the picture of the video is affected by other dynamic layers contained in the first video information can be effectively avoided, and the video frame insertion effect is improved. In addition, the embodiment of the application carries out frame insertion processing through the video processing chip, so that the power consumption of the main control chip can be reduced, the frame insertion efficiency is improved, and the real-time performance of frame insertion videos is ensured.

Optionally, in this embodiment of the application, the processor 110 is specifically configured to obtain, based on information to be processed, first video information, first interface image information, and second interface image information;

the processor 110 is specifically configured to fuse the first interface image information and the second interface image information, and output fused interface image information;

and the video processing chip is specifically used for synthesizing the second video information and the fusion interface image information and outputting third video information.

Therefore, under the condition that the interface image information and the video image information are separable, the interface image information and the video image information are separated, and only the video image information is subjected to frame interpolation processing, so that the influence of the change of the interface image information on the motion calculation of the picture of the video image information is avoided, the frame interpolation effect of the video can be improved, and the video picture after frame interpolation processing is more smoothly viewed.

the processor 110 is specifically configured to synthesize the first interface image information, the second interface image information, and the second video information, and output third video information.

Therefore, under the condition that the interface image information and the video image information can be separated, the interface image information does not need to be sent to the video processing chip, the video processing chip is only needed to perform frame insertion processing on the video image information and feed the video image information back to the processor, the processor directly synthesizes the obtained second video information and the interface image information and then transmits the second video information and the interface image information to the display screen, and power consumption is saved. Meanwhile, the processor performs Alpha superposition calculation on the second video information and the interface image information obtained by frame insertion, and the Alpha superposition calculation is easier and more accurate than that performed at a video processing chip end, so that the frame insertion effect is further improved.

Optionally, in this embodiment of the application, the processor 110 is specifically configured to obtain a video to be processed and first interface image information based on the information to be processed, where the video to be processed includes the video image information and second interface image information.

The processor 110 is specifically configured to, in a case that the video image information is inseparable from the second interface image information, synthesize the video to be processed and the first interface image information to generate the first video information.

Optionally, in this embodiment of the application, the processor 110 is further configured to obtain a video to be processed based on the information to be processed, and use the video to be processed as the first video information;

It should be understood that, in the embodiment of the present application, the input Unit 104 may include a Graphics Processing Unit (GPU) 1041 and a microphone 1042, and the Graphics Processing Unit 1041 processes image data of a still picture or a video obtained by an image capturing device (such as a camera) in a video capturing mode or an image capturing mode. The display unit 106 may include a display panel 1061, and the display panel 1061 may be configured in the form of a liquid crystal display, an organic light emitting diode, or the like. The user input unit 107 includes at least one of a touch panel 1071 and other input devices 1072. The touch panel 1071 is also referred to as a touch screen. The touch panel 1071 may include two parts of a touch detection device and a touch controller. Other input devices 1072 may include, but are not limited to, a physical keyboard, function keys (e.g., volume control keys, switch keys, etc.), a trackball, a mouse, and a joystick, which are not described in detail herein.

The memory 109 may be used to store software programs as well as various data. The memory 109 may mainly include a first storage area storing a program or an instruction and a second storage area storing data, wherein the first storage area may store an operating system, an application program or an instruction (such as a sound playing function, an image playing function, etc.) required for at least one function, and the like. Further, memory 109 may include volatile memory or non-volatile memory, or memory 109 may include both volatile and non-volatile memory. The non-volatile Memory may be a Read-Only Memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an Electrically Erasable PROM (EEPROM), or a flash Memory. The volatile Memory may be a Random Access Memory (RAM), a Static Random Access Memory (Static RAM, SRAM), a Dynamic Random Access Memory (Dynamic RAM, DRAM), a Synchronous Dynamic Random Access Memory (Synchronous DRAM, SDRAM), a Double Data Rate Synchronous Dynamic Random Access Memory (Double Data Rate SDRAM, ddr SDRAM), an Enhanced Synchronous SDRAM (ESDRAM), a Synchronous Link DRAM (SLDRAM), and a Direct Memory bus RAM (DRRAM). Memory 109 in the embodiments of the subject application includes, but is not limited to, these and any other suitable types of memory.

Processor 110 may include one or more processing units; optionally, the processor 110 integrates an application processor, which mainly handles operations related to the operating system, user interface, application programs, etc., and a modem processor, which mainly handles wireless communication signals, such as a baseband processor. It will be appreciated that the modem processor described above may not be integrated into the processor 110.

The embodiment of the present application further provides a readable storage medium, where a program or an instruction is stored on the readable storage medium, and when the program or the instruction is executed by a processor, the program or the instruction implements each process of the video frame interpolation method embodiment, and can achieve the same technical effect, and in order to avoid repetition, details are not repeated here.

The processor is the processor in the electronic device described in the above embodiment. The readable storage medium includes a computer readable storage medium, such as a computer read only memory ROM, a random access memory RAM, a magnetic or optical disk, and the like.

Embodiments of the present application provide a computer program product, where the program product is stored in a storage medium, and the program product is executed by at least one processor to implement the processes of the above-mentioned video frame interpolation method embodiments, and can achieve the same technical effects, and in order to avoid repetition, details are not repeated here.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. Further, it should be noted that the scope of the methods and apparatus of the embodiments of the present application is not limited to performing the functions in the order illustrated or discussed, but may include performing the functions in a substantially simultaneous manner or in a reverse order based on the functions involved, e.g., the methods described may be performed in an order different than that described, and various steps may be added, omitted, or combined. In addition, features described with reference to certain examples may be combined in other examples.

Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner. Based on such understanding, the technical solutions of the present application may be embodied in the form of a computer software product, which is stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal (such as a mobile phone, a computer, a server, or a network device) to execute the method according to the embodiments of the present application.

While the present embodiments have been described with reference to the accompanying drawings, it is to be understood that the invention is not limited to the precise embodiments described above, which are meant to be illustrative and not restrictive, and that various changes may be made therein by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A video processing circuit is characterized by comprising a main control chip and a video processing chip, wherein the main control chip is connected with the video processing chip;

the main control chip is used for acquiring first video information based on information to be processed;

the video processing chip is used for performing frame insertion processing on the first video information and outputting second video information under the condition that the first video information meets a preset condition.

2. The circuit of claim 1, wherein the preset condition comprises a first preset condition or a second preset condition:

3. The circuit of claim 1,

the main control chip is specifically used for acquiring the first video information, the first interface image information and the second interface image information based on the information to be processed;

the main control chip is also used for fusing the first interface image information and the second interface image information and outputting fused interface image information;

the video processing chip is further used for synthesizing the second video information and the fusion interface image information and outputting third video information.

4. The circuit of claim 1,

the main control chip is further configured to fuse the first interface image information, the second interface image information, and the second video information, and output third video information.

5. The circuit of claim 1,

the main control chip is specifically used for acquiring a video to be processed and first interface image information based on the information to be processed, wherein the video to be processed comprises the video image information and second interface image information;

the main control chip is further configured to synthesize the video to be processed and the first interface image information to generate the first video information under the condition that the video image information and the second interface image information are inseparable.

6. The circuit of claim 1,

the main control chip is specifically used for acquiring a video to be processed based on the information to be processed; the video to be processed comprises video image information and second interface image information;

the main control chip is specifically configured to use the video to be processed as the first video information under the condition that the video image information and the second interface image information are inseparable.

7. A video processing method applied to the video processing circuit according to any one of claims 1 to 6, the method comprising:

the main control chip acquires first video information based on the information to be processed;

and under the condition that the first video information meets the preset condition, a video processing chip performs frame insertion processing on the first video information and outputs second video information.

8. The method of claim 7,

the preset conditions comprise a first preset condition or a second preset condition:

9. The method of claim 7, wherein the obtaining, by the main control chip, the first video information based on the information to be processed comprises:

the main control chip acquires the first video information, the first interface image information and the second interface image information based on the information to be processed;

the main control chip fuses the first interface image information and the second interface image information and outputs fused interface image information;

after the video processing chip performs frame interpolation processing on the first video information and outputs second video information, the method further comprises:

and the video processing chip synthesizes the second video information and the fusion interface image information and outputs third video information.

10. The method of claim 7,

the main control chip obtains first video information based on the information to be processed, and the method comprises the following steps:

and the main control chip synthesizes the first interface image information, the second interface image information and the second video information and outputs third video information.

11. The method of claim 7,

the main control chip acquires a video to be processed and first interface image information based on the information to be processed, wherein the video to be processed comprises video image information and second interface image information;

and under the condition that the video image information and the second interface image information are inseparable, the main control chip synthesizes the video to be processed and the first interface image information to generate the first video information.

12. The method of claim 7,

the main control chip acquires a video to be processed based on the information to be processed, and takes the video to be processed as the first video information;

the video to be processed comprises video image information and second interface image information, and the video image information and the second interface image information are inseparable.

13. A video processing circuit is characterized by comprising a main control chip and a video processing chip, wherein the main control chip comprises an acquisition unit and a first interface; the video processing chip comprises a second interface and a frame insertion unit;

the acquisition unit is used for acquiring first video information based on the information to be processed;

the acquisition unit is connected with the first interface, and the first interface is used for outputting the first video information;

the second interface is respectively connected with the first interface and the frame insertion unit;

and the frame interpolation unit is used for performing frame interpolation processing on the first video information and outputting second video information under the condition that the first video information meets a preset condition.

14. The circuit of claim 13, wherein the preset condition comprises a first preset condition or a second preset condition:

15. The circuit of claim 13,

the acquisition unit is further used for acquiring first interface image information and second interface image information based on the video to be processed;

the main control chip further comprises: the first fusion unit is respectively connected with the acquisition unit and the third interface;

the first fusion unit is used for fusing the first interface image information and the second interface image information and outputting fusion interface image information;

the video processing chip also comprises a fourth interface and a second fusion unit;

the third interface is connected with the fourth interface, and the second fusion unit is respectively connected with the fourth interface and the frame insertion unit;

the second fusion unit is used for synthesizing the second video information and the fusion interface image information and outputting third video information.

16. The circuit of claim 13,

the main control chip also comprises a first fusion unit and a third interface;

the video processing chip also comprises a fourth interface; the fourth interface is respectively connected with the frame insertion unit and the third interface;

the acquisition unit is respectively connected with the first fusion unit and the third interface;

the first fusion unit is used for synthesizing the first interface image information, the second interface image information and the second video information and outputting third video information.

17. The circuit of claim 13,

the acquisition unit is further used for acquiring a video to be processed and first interface image information based on the information to be processed, wherein the video to be processed comprises the video image information and second interface image information;

the main control chip also comprises a first fusion unit which is respectively connected with the acquisition unit and the first interface;

the first fusion unit is used for synthesizing the video to be processed and the first interface image information to generate the first video information under the condition that the video image information and the second interface image information are inseparable.

18. The circuit of claim 13,

the acquiring unit is specifically configured to acquire a video to be processed based on the information to be processed; the video to be processed comprises video image information and second interface image information;

the acquiring unit is specifically configured to take the video to be processed as the first video information under the condition that the video image information is inseparable from the second interface image information.

19. An electronic device, characterized in that it comprises a display screen and a video processing circuit according to any one of claims 1 to 6,

the display screen is connected with the video processing circuit;

the display screen is used for displaying the video information processed by the video processing circuit.

20. An electronic device, characterized in that it comprises a display screen and a video processing circuit according to any one of claims 13 to 18,

the display screen is connected with the video processing circuit;