CN114337637A

CN114337637A - Geminate transistor circuit

Info

Publication number: CN114337637A
Application number: CN202210018712.0A
Authority: CN
Inventors: 高怀; 田婷
Original assignee: Xiamen Innotion Technology Co ltd
Current assignee: Xiamen Innotion Technology Co ltd
Priority date: 2022-01-08
Filing date: 2022-01-08
Publication date: 2022-04-12

Abstract

The invention discloses a pair tube circuit, which comprises: the transistor array is composed of two groups of transistors on the same substrate, and each group of transistors is formed by connecting a plurality of transistors with the same number and the same process in parallel. There is no electrical connection between the two sets of transistors, and the isolation unit between the two sets of transistors is formed by a loss structure. Each port of the two sets of transistors has a separate bi-directional ESD protection cell to ground, which is typically formed by a diode string. The GND unit provides a heat dissipation path to the heat sink; and when the layout is drawn, uniformly distributing a plurality of GND units. When the layout is designed, the metal connecting line of the base electrode and the emitting electrode is widened, and a gradual change transmission line is used when the metal connecting line is close to a transistor pin. When the whole circuit is used for drawing a layout, the whole circuit is completely symmetrical and can rotate by 180 degrees. The invention effectively improves the high-frequency differential performance of the circuit.

Description

Geminate transistor circuit

Technical Field

The present invention relates to integrated circuits, and more particularly, to a pair-transistor circuit on the same substrate.

Background

In a pair transistor circuit, two transistors which are identical are manufactured on the same substrate, the temperatures of the two transistors can affect each other, and the ambient temperature can also affect the transistors. Theoretically, the noise coefficients, characteristic curves, amplification factors and the like of the two transistors are required to be consistent, so that in the application of the differential circuit, the influence of the common-mode signal on the differential-mode signal can be counteracted to a great extent, and the zero drift caused by the temperature influence can be counteracted. In addition to the differential circuit, a common Voltage Controlled Oscillator (VCO) circuit structure is also composed of an oscillating tube and an amplifying tube, so that the VCO can also be constructed by using a pair tube circuit.

When a traditional pair transistor circuit is designed, two transistors are not electrically isolated, and parasitic parameters between ports are many, which affects the high-frequency performance of the circuit, such as the parasitic capacitance between electrodes in fig. 1: c _ B1B2, C _ E1B2, C _ E1C2, C _ C1B 2.

Disclosure of Invention

In view of the deficiencies of the prior art, the present invention provides a high performance pair transistor circuit, the two transistors are electrically isolated from each other by a port-to-Ground (GND) isolation unit, cross talk between each other is reduced, and the GND unit provides a heat dissipation path to ground. In order to reduce the Miller capacitance of the transistor, the metal width of the base electrode and the emitter electrode of the transistor is widened when the layout design is carried out. And each port of the transistor has a bidirectional (forward, reverse) esd (electro Static discharge) protection unit to ground in order to improve the standing wave resistance of the circuit.

The technical scheme of the invention is as follows:

based on the same substrate, the device is composed of two groups of transistors T1 and T2, wherein each group of transistors is formed by connecting a plurality of transistors with the same number and the same process in parallel;

there is no electrical connection between the two sets of transistors T1, T2, there is an isolation unit to ground GND1, GND2 between the two sets of transistors T1, T2 for decoupling isolation, the isolation unit is composed of loss structure, for example, the isolation unit is a resistor.

Each port B1, E1, C1, B2, E2, C2 of the two sets of transistors T1, T2 has a separate bidirectional ESD protection cell to ground, which is a diode string.

The GND unit provides a heat dissipation path to the heat sink; and when the layout is drawn, uniformly distributing a plurality of GND units.

When the layout is designed, metal connecting wires of base electrodes (B1, B2) and emitter electrodes (E1, E2) are widened, and a gradual transmission line is used when the wire is close to a transistor pin.

When the whole circuit is used for drawing a layout, the whole circuit is completely symmetrical and can rotate by 180 degrees, the position of the isolation unit is unchanged, and the positions of the transistors are overlapped.

The two sets of transistors T1, T2 are formed by a semiconductor process using HBT, or a semiconductor process using BJT, or a semiconductor process using FET.

The invention has the beneficial effects that:

the high-performance and high-isolation geminate transistors circuit is provided, no electrical connection exists between geminate transistors, isolation units are used for isolation, the symmetry is improved, crosstalk and parasitic parameters are reduced, and the high-frequency performance is improved; and the heat dissipation environment is improved, and the method is suitable for high-power application.

Drawings

Fig. 1 is a conventional pair tube circuit.

Fig. 2 is one of the structural diagrams of the present invention.

FIG. 3 is a second block diagram of the present invention.

FIG. 4 is a circuit diagram of the second structure of the present invention.

Detailed Description

The circuit of the present invention is further described below with reference to the accompanying drawings:

two sets of transistors T1 and T2 are disposed on the same substrate, and each set of transistors can select a corresponding semiconductor process according to the requirements of cost, output power, working frequency, etc. For example, a Si-based BJT semiconductor process is selected to save cost, a GaN HEMT semiconductor process is selected to increase output power, and a GaAs HBT semiconductor process is selected to increase working frequency.

Each group is formed by connecting a plurality of transistors in parallel, generally 1-4 transistors can be used, the number of the parallel transistors of the two groups of transistors is consistent, and the process is consistent. The transistor T1 and the transistor T2 are not electrically connected, decoupling isolation is performed by an isolation unit from one port to the ground, the isolation unit is distributed at a position between the transistors T1 and T2, for example, the isolation unit is obliquely spanned between GND1 and GND2 at 45 degrees in FIG. 2, crosstalk between the transistor T1 and the transistor T2 is effectively reduced, and the whole operating frequency of the circuit is improved. The isolation unit is typically formed by a lossy structure, such as a resistor.

The emitters E1 and E2, the collectors C1 and C2 and the bases B1 and B2 of the transistor T1 and the transistor T2 are respectively provided with a bidirectional ESD protection unit to the ground, so that the anti-burning capacity of the circuit can be improved. The ESD protection unit is generally formed of a diode string. The number of diodes can be set according to the size of the protection electrostatic voltage required.

The GND unit provides a heat dissipation path to a heat sink (ThermalShont), which is beneficial to the application of the circuit to high-power scenes. When the layout is drawn, each GND unit can be uniformly distributed according to specific heat dissipation requirements, and the number of GND can be adjusted.

When the transistor T1 and the transistor T2 are designed in a layout mode, the base electrodes B1 and B2 and the emitter electrodes E1 and E2 are widened, a gradual change transmission line is used at a position close to a transistor pin, the characteristic impedance of the pin transmission line is changed, the Miller capacitance is effectively reduced, and the frequency characteristic of a circuit is improved.

When the whole circuit is used for drawing a layout, the rotation is carried out by 180 degrees at the central point of the substrate, and the positions of the transistors T1 and T2 are symmetrical, so that the realization of complete symmetry of the electrical properties of the two groups of transistors T1 and T2 is facilitated, and the circuit is more suitable for a differential circuit structure.

As shown in fig. 3, when used as a differential circuit structure, the emitters E1 and E2 of two sets of transistors T1, T2 may be electrically connected by a GND unit, further improving the symmetry of the circuit. In the figure, the emitters E1 and E2 of the transistor T1 and the transistor T2 are electrically connected through GND3 and GND4, or can be electrically connected through GND2 and GND1, so that the circuit layout is ensured to be symmetrical as far as possible, and the symmetry of the transistors is ensured.

All GND units represent only one pin function after chip packaging, and may not be connected to system ground when subsequent PCB-based system scheme design is performed.

Claims

1. A pair of transistor circuits, characterized by that it is made up of two groups of transistors (T1, T2) on the identity substrate, each group of transistors is connected in parallel and formed by many transistors identical in number and technology;

the two groups of transistors (T1 and T2) are not electrically connected, an isolation unit to the ground (GND1 and GND2) is arranged between the two groups of transistors (T1 and T2) for decoupling isolation, and the isolation unit is composed of a loss structure;

each port (B1, E1, C1, B2, E2, C2) of the two sets of transistors (T1, T2) has a separate bidirectional ESD protection unit to ground.

2. A pair of transistor circuits according to claim 1, wherein: the emitters (E1 and E2) of the two sets of transistors (T1, T2) are electrically connected through the GND cell.

3. A pair transistor circuit as claimed in any one of claims 1 to 2, wherein: the number of each group of transistors (T1 or T2) is 1-4.

4. A pair of transistor circuits according to claim 3, wherein: the GND unit provides a heat dissipation path to the heat sink; and when the layout is drawn, uniformly distributing a plurality of GND units.

5. A pair of transistor circuits according to claim 4, wherein: the isolation unit is a resistor.

6. A pair of transistor circuits according to claim 5, wherein: the ESD protection unit is a diode string.

7. A pair of transistor circuits according to claim 6, wherein: when the layout is designed, metal connecting wires of base electrodes (B1, B2) and emitter electrodes (E1, E2) are widened, and a gradual transmission line is used when the wire is close to a transistor pin.

8. A pair of transistor circuits according to claim 7, wherein: when the whole circuit is used for drawing a layout, the central point is rotated by 180 degrees, and the physical positions of the two groups of transistors (T1 and T2) are symmetrical.

9. A pair of transistor circuits according to claim 6, wherein: the two sets of transistors (T1, T2) are formed by a semiconductor process using HBTs, a semiconductor process using BJTs, or a semiconductor process using FETs.