CN114337203B - Low-power-consumption driving circuit for switching power supply and switching power supply system - Google Patents

Abstract

A low-power consumption driving circuit for a switching power supply and a switching power supply system comprise a controlled current source, a pull-up switch and a pull-down switch, wherein the controlled current source provides a base current of a bipolar power transistor in the switching power supply, so that the magnitude of the base current changes along with a current flowing through the bipolar transistor, the pull-up switch is used for controlling the controlled current source to be turned on and off, and the pull-down switch is used for pulling down the base potential of the bipolar transistor. The low-power consumption driving circuit can effectively reduce the power consumption of the chip and the required capacitance value of the power supply capacitor.

Description

Low-power-consumption driving circuit for switching power supply and switching power supply system

Technical Field

The present invention relates to electronic circuits, and more particularly, to a low power consumption driving circuit for a switching power supply and a switching power supply system.

Background

Switching power supplies are currently widely used in a variety of circuit applications. In order to drive the power transistors in the switching power supply, most of the switching power supply control chips include a driving circuit for providing a voltage or a current required for driving the power transistors to be turned on and off. In the selection of switching power transistors, bipolar transistors (BJTs) are favored for low cost applications because of their low cost.

However, since the bipolar transistor is a current-type control device, a mode of modulating the base current is required to control the current output, which often accompanies a problem of higher power consumption, and is not suitable for applications with higher efficiency requirements. Specifically, the larger the bipolar transistor output current, the larger the base current IB required to drive the bipolar transistor, i.e. the larger the current consumed by the control chip, which not only reduces the system efficiency, but also requires a higher capacitance system power (VCC) capacitor to power the chip, which substantially counteracts the cost advantage of the bipolar transistor.

More disadvantageously, in the prior art, in order to always provide a sufficient driving current for the bipolar transistor, the driving current needs to ensure that a proper base current can be provided to adapt to a peak current flowing through the bipolar transistor, and this needs to always keep a higher level of the driving current, so that a higher base current causes a larger waste, especially when the switching power supply works under a working condition with a larger duty ratio, the system efficiency is rapidly reduced, and the control chip heats seriously, thereby bringing about a heat dissipation problem.

Accordingly, improvements in the art are needed to reduce the power consumption of the drive circuit.

Disclosure of Invention

In response to one or more problems in the prior art, a low power consumption driving circuit for a switching power supply is proposed.

One aspect of the present invention proposes a driving circuit for driving a bipolar transistor as a power switch in a switching power supply system, the bipolar transistor being coupled to a power inductor or a transformer in the switching power supply system, wherein the driving circuit comprises: a controlled current source for outputting a controlled current to provide a base current of the bipolar transistor, wherein the magnitude of the controlled current follows the current flowing through the bipolar transistor after the bipolar transistor is turned on during each duty cycle; a pull-up switch coupled to the controlled current source for controlling the controlled current source to turn on and off; a pull-down switch is coupled to the base of the bipolar transistor for pulling down the base potential of the bipolar transistor.

In one embodiment, after the bipolar transistor begins to turn on, the controlled current increases following the current increase of the bipolar transistor until it increases to a maximum value.

In one embodiment, the controlled current linearly follows the current of the bipolar transistor during each duty cycle of the switching power supply and rises to the maximum value at a time earlier than when the pull-up control the controlled current source to turn off.

In one embodiment, the controlled current has an initial value that is not zero at the moment the bipolar transistor is turned on during each duty cycle of the switching power supply, the initial value being derived from the minimum value of the current flowing through the bipolar transistor.

In one embodiment, the pull-up switch turns off the controlled current source at a time earlier than the pull-down switch pulls down the bipolar transistor base potential during each duty cycle of the switching power supply.

In one embodiment, the pull-up switch is controlled by a first pulse width modulation signal, the pull-down switch is controlled by a second pulse width modulation signal, the first pulse width modulation signal controls the pull-up switch to turn off the controlled current source when the current of the bipolar transistor rises to a first reference value during the turn-on period of the bipolar transistor, and the second pulse width modulation signal controls the pull-down switch to pull down the base potential of the bipolar transistor when the current of the bipolar transistor continues to rise to a second reference value.

In one embodiment, the controlled current source receives a transistor current sense signal as a basis for controlling the controlled current, the transistor current sense signal being indicative of the current flowing through the bipolar transistor.

In one embodiment, the driving circuit is located in an integrated circuit chip, and the controlled current source includes a mirror current source, and the mirror current source includes: a first mirror branch including a first upper arm transistor having a first end coupled to receive system power from the integrated circuit chip, a second end coupled to the base of the bipolar transistor and to a first end of the pull-down switch, and a second end coupled to a chip ground of the integrated circuit chip; a second mirror branch comprising a second upper arm transistor and a second lower arm transistor, the control terminal of the first upper arm transistor being connected to the control terminal of the second upper arm transistor and further connected to the second terminal of the second upper arm transistor, the first terminal of the second upper arm transistor being coupled to receive system power from the integrated circuit chip, the second terminal of the second upper arm transistor being further connected to the first terminal of the pull-up switch, the second lower arm transistor being coupled between the second terminal of the pull-up switch and the chip ground and being controlled by a dynamic reference bias signal generated based at least on the transistor current sense signal; the controlled current source further includes a dynamic reference operator for generating the dynamic reference bias signal based at least on the transistor current sense signal.

In one embodiment, the dynamic reference operator includes a third mirror branch and a current extraction circuit, the current extraction circuit extracting a dynamic current from the third mirror branch, the dynamic current being generated based at least on the transistor current sense signal, the dynamic current gradually decreasing until zero after the bipolar transistor is turned on; the third mirror leg includes: a first reference current source, a first end coupled to receive the system power of the integrated circuit chip, and a second end outputting a first reference current, wherein the current extraction circuit extracts the dynamic current from the second end of the first reference current source; a third upper arm transistor, a first end of which is coupled with a second end of the first reference current source, and a control end of which is connected with the second end of the third upper arm transistor; the control end and the first end of the third lower arm transistor are coupled with the second end of the third upper arm switch tube, and the second end is connected with the chip ground; wherein the second end of the third upper arm transistor outputs the dynamic reference bias signal.

Another aspect of the present invention provides a switching power supply system, wherein the power switch of the switching power supply system at least comprises a bipolar transistor, the bipolar transistor is coupled to a power inductor or a transformer in the switching power supply system, and the bipolar transistor is driven by the driving circuit according to any one of the above embodiments.

In one embodiment, the switching power supply system further comprises a transistor current sampling resistor, a first end of the transistor current sampling resistor is connected to an emitter of the bipolar transistor, a second end of the transistor current sampling resistor is connected to a system ground, and the driving circuit is located in an integrated circuit chip, wherein the integrated circuit chip is provided with a chip ground, and the chip ground is the first end of the transistor current sampling resistor.

The embodiment of the invention provides a low-power-consumption driving circuit for a switching power supply. Compared with the traditional drive circuit applied to the bipolar transistor, the drive circuit can effectively reduce the average working current of the chip, thereby reducing the power consumption of the chip and the required VCC capacitance.

Drawings

Throughout the following drawings, the same reference numerals indicate the same, similar or corresponding features or functions.

Fig. 1 shows a schematic circuit configuration of a driving circuit 100 according to an embodiment of the present invention;

fig. 2 shows a waveform diagram of a driving circuit 100 according to an embodiment of the present invention;

FIG. 3 shows a block diagram of a controlled current source 101 according to one embodiment of the invention;

fig. 4 shows a circuit configuration diagram of a dynamic reference operator 201 according to an embodiment of the present invention;

Detailed Description

Specific embodiments of the invention will be described in detail below, it being noted that the embodiments described herein are for illustration only and are not intended to limit the invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one of ordinary skill in the art that: no such specific details are necessary to practice the invention. In other instances, well-known circuits, materials, or methods have not been described in detail in order not to obscure the invention.

Throughout the specification, references to "one embodiment," "an embodiment," "one example," or "an example" mean: a particular feature, structure, or characteristic described in connection with the embodiment or example is included within at least one embodiment of the invention. Thus, the appearances of the phrases "in one embodiment," "in an embodiment," "one example," or "an example" in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable combination and/or sub-combination in one or more embodiments or examples. Moreover, those of ordinary skill in the art will appreciate that the illustrations provided herein are for illustrative purposes and that the illustrations are not necessarily drawn to scale. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected to" or "directly coupled to" another element, there are no intervening elements present. Like reference numerals designate like elements. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Accordingly, a first element discussed below could be termed a second element without departing from the teachings of the present inventive concept. As used herein, the term "and/or" includes all combinations of any of the associated listed items and one or more.

Fig. 1 shows a schematic circuit configuration of a driving circuit 100 according to an embodiment of the present invention. As shown in fig. 1, the driving circuit 100 is located in one switching power supply system 10. In the illustrated embodiment, the switching power supply system 10 is a flyback isolated converter, and the driving circuit 100 is configured to drive the bipolar power transistor Q1, which is a primary power switch, on the primary side of the flyback isolated converter. The bipolar transistor Q1 is connected to the primary winding L1. Those of ordinary skill in the art will appreciate that in other embodiments, the switching power supply system 10 may take other suitable topologies, as long as the switching power supply system includes bipolar power transistors as power switches coupled to a power inductor or transformer, as the invention is not limited in this regard.

As further shown in fig. 1, the driving circuit 100 includes a controlled current source 101, a pull-up switch M2 and a pull-down switch M1. The controlled current source 101 is arranged to output a controlled current IB providing the base current of the bipolar transistor. Wherein the magnitude of the controlled current IB changes following the change of the current IC flowing through the bipolar transistor Q1 after the bipolar transistor Q1 is turned on during the duty cycle of each switching power supply. In the illustrated embodiment, controlled current source 101 receives a transistor current sense signal VCS that characterizes the current IC flowing through Q1, from which the value of the output controlled current IB is determined. The transistor current sense signal VCS may track the current IC flowing through the transistor Q1 in reverse (i.e., vcs= -j×ic, j being a coefficient), i.e., the larger the IC, the lower the potential of the transistor current sense signal VCS.

Wherein in the illustrated embodiment, the pull-up switch M2 is coupled to the controlled current source 101 for controlling the controlled current source to be turned on and off. Specifically, when the controlled current source 101 is located in the integrated circuit chip, the pull-up switch M2 may control whether the controlled current source is enabled by controlling the establishment and disconnection of an electrical connection between the controlled current source 101 and a power supply voltage of the integrated circuit chip. For example, in the illustrated embodiment, when the pull-up switch M2 is closed, the controlled current source 101 is able to output the controlled current IB, and when the pull-up switch is open, the controlled current source 101 stops outputting the controlled current IB, at which point the current on the base of the bipolar transistor Q1 is no longer present, resulting in the turning off of the bipolar transistor Q1.

The pull-down switch M1 is coupled to the base of the bipolar transistor Q1, and is configured to pull down the base potential of the bipolar transistor Q1 during the turn-off process of the bipolar transistor, so as to ensure that the bipolar transistor Q1 is completely turned off. Specifically, when the driving circuit is located in the integrated circuit chip, the pull-down switch M1 is connected between the base of the bipolar transistor Q1 and the chip ground CGND of the chip in the integrated circuit, and during the period that the bipolar transistor Q1 is turned on, the pull-down switch M1 is turned off, so that the bipolar transistor can operate normally. When the bipolar transistor Q1 needs to be turned off, the pull-down switch M1 is turned on so that the bipolar transistor Q1 is quickly pulled down to a position close to the integrated circuit chip ground, so that the bipolar transistor Q1 is quickly turned off.

The operation principle of the driving circuit 100 will be described below with reference to the waveform diagram shown in fig. 2, taking the primary side of the flyback isolated converter in the illustrated embodiment as an example. Since Q1 is connected to the primary winding L1, when the bipolar transistor Q1 is turned on initially, the current flowing through the bipolar transistor Q1 is affected by the choking action of the primary winding L1, and then gradually rises. Therefore, the required base current can also be a lower value at the beginning of the turn-on of the bipolar transistor Q1. In this way, during the process of turning on Q1, the pull-up switch M2 of the driving circuit 100 is turned on, the controlled current source 101 starts to operate, and outputs a lower controlled current as an initial value, which is IB0, so that a lower initial base current is provided for the bipolar transistor Q1, so that the bipolar transistor Q1 can be turned on smoothly. The initial value IB0 may be set according to an operating point of the current IC flowing through the bipolar transistor Q1, such that IB0 corresponds to a minimum value of the transistor current IC during the on period of Q1 as much as possible, thereby minimizing unnecessary chip power consumption. It should be noted, however, that while in theory, for the flyback converter topology primary winding illustrated, or power inductances in some other topologies, when the switching power supply system 10 is operating in either the inductor current critical continuous mode or the inductor current discontinuous mode, the Q1 current IC may have a minimum value of 0 during Q1 conduction, where the initial value of the corresponding desired controlled current IB may also be 0, when it is at the minimum value, since zero current is difficult to detect, if the initial value IB0 is set to 0, various types of disturbances may be experienced, resulting in a failure of the circuit from IC to IB to produce the correct drive current, ultimately resulting in Q1 turn-on failure, and therefore, for the case of the illustrated embodiment, it is preferable that the initial value IB0 is not 0 and is as small as possible if the disturbance can be avoided.

In the illustrated embodiment, after Q1 is turned on smoothly, the IC current gradually increases along with the inductor current IL, and at this time, the potential corresponding to VCS gradually decreases. VCS is input to controlled current source 101 and the resulting controlled current IB gradually increases from IB0 until it increases to a maximum IBF. In the illustrated embodiment, the controlled current IB linearly follows the current IC of the bipolar transistor Q1 during one duty cycle of the switching power supply and rises to the maximum value at a time earlier than when the pull-up switch M2 controls the turn-off of the controlled current source. Since the primary inductor current IL and the Q1 transistor current IC substantially exhibit a linear rising trend over time during conduction, the controlled current IB also exhibits a linear rising trend over time by following the IC linearly. In this way, the controlled current IB and the transistor current IC have a substantially uniform rising trend. At the same time, in order to avoid errors and disturbances occurring in real applications, it is preferable that the rise of the controlled current IB needs to be slightly advanced with respect to the rise of the transistor current IC, so that the controlled current IB rises to a maximum value before the controlled current source turn-off instant, enabling the base current provided by the controlled current IB to always meet the need to support the transistor current IC.

Continuing with fig. 2, during each duty cycle, pull-up switch M2 turns off the controlled current source at a time earlier than pull-down switch M1 pulls down the base potential of bipolar transistor Q1. For the bipolar transistor, a certain delay exists when the bipolar transistor is turned off, in the process of turning off the Q1, when VCS falls to V1, M2 is turned off, the controlled current source is turned off, so that the controlled current IB jumps to 0, but at the moment, the Q1 still needs a certain response time, the IC continues to follow the IL to rise until the peak value, and then when VCS falls to V2, the pull-down switch M1 is turned on again, the base potential of the Q1 is pulled down to be close to the chip CGND, and therefore the Q1 is reliably turned off. In a specific implementation process, the pull-up switch M2 is controlled by a first pulse width modulation signal PWM2, the pull-down switch M1 is controlled by a second pulse width modulation signal PWM1, during the on period of the bipolar transistor Q1, when the current IC of the bipolar transistor rises to a first reference value (corresponding to VCS being equal to V1), the first pulse width modulation signal PWM2 controls the pull-up switch M2 to turn off the controlled current source 101, and when the current IC of the bipolar transistor Q1 continues to rise to a second reference value (corresponding to VCS being equal to V2), the second pulse width modulation signal PWM1 controls the pull-down switch M1 to pull down the base potential of the bipolar transistor Q1.

In this way, by utilizing the characteristic of the turn-off delay of the bipolar transistor Q1, the maximum value is not required to be designed for the controlled current IB in an absolute correspondence with the peak value of the transistor current IC, but can be designed correspondingly with a value smaller than the peak value of the transistor current IC, thus further reducing the average driving current and the chip power consumption.

After the bipolar transistor Q1 is completely turned off, due to the inherent characteristics of the flyback topology, the inter-electrode capacitance of the bipolar transistor Q1 needs to be charged until the collector voltage of the transistor Q1 rises to be equal to the sum of the input voltage VIN and the output voltage Vout a times (a is the gate ratio of the flyback converter transformer), so that the flywheel diode on the secondary side is turned on. Thus, during this period, inductor current IL will continue to rise, while both current IC and VCS signals flowing through the transistor are zeroed.

Fig. 3 shows a block diagram of a controlled current source 101 according to one embodiment of the invention. In the embodiment shown in fig. 3, the driving circuit 100 is still located in the integrated circuit chip and is connected to the primary side of a flyback isolated converter, and in contrast to the embodiment shown in fig. 2, the primary side of the flyback isolated converter has a transistor current sampling resistor R1, the first terminal R1 of which is connected to the emitter of the bipolar transistor Q1, and at the same time, R1 is also connected to the terminal of the pulldown switch M1 remote from the base of the bipolar transistor. A second terminal of the transistor current sampling resistor R1 is connected to the system ground PGND. Further, in the illustrated embodiment, the integrated circuit chip on which the driving circuit 100 is located has a chip ground CGND, which is a first terminal of the transistor current sampling resistor R1. When a glitch or oscillation occurs in the transistor current and acts on the transistor current sampling resistor R1 after the chip ground CGND and the system ground PGND are separated in this way, since the chip ground CGND is located at the first end of R1, the glitch is not introduced from the first end of R1 to act on the pull-down switch M1, but acts on the VCS. Thus, the burr peak can be effectively prevented from generating breakdown on the pulldown switch M1. Meanwhile, in some applications, the Q1 emitter may be connected to a power supply circuit of the chip in addition to R1, so that part of the emitter current is used for power supply, and at this time, by adopting a design of separating the chip ground and the system ground, the first end of R1 is connected to the chip ground CGND, so that the system power supply current drawn from the Q1 emitter current flows to R1 after flowing through the chip ground CGND, so that R1 can more accurately detect the transistor current IC. Those having ordinary skill in the art will appreciate that in other embodiments of the present invention, the transistor current sampling resistor R1 need not be connected to the chip ground CGND, and the basic object of embodiments of the present invention can be achieved without employing a separate system-on-chip and chip-on-chip design for situations where the linear adjustment rate is not required and where the corresponding protection circuit is provided on M1.

As further shown in fig. 3, the controlled current source 101 comprises a mirrored current source having two mirrored branches: a first mirror leg and a second mirror leg. The first mirror circuit includes a first upper arm transistor QP1 having a first terminal coupled to receive the system power VCC of the integrated circuit chip, a second terminal of the first upper arm transistor QP1 coupled to the base of the bipolar transistor Q1 and a first terminal of the pull-down switch M1, and a second terminal of the pull-down switch M1 coupled to the chip ground CGND of the integrated circuit chip. Herein and herein, it will be understood by those skilled in the art that "system power for an integrated circuit chip" may include one or more sets of voltages, rather than just a single voltage value. For example, in some integrated circuit chips, there may be multiple dies (die), some of which may be located in one of the dies, with, for example, 3.3V being the system power, and some of which may be located in another of the dies, with, for example, 5V being the system power. In this context, for convenience of identification, power supplies that can play a role of power supply in the integrated circuit chip are unified as system power supplies, and VCC is used as a flag. In real world engineering, the system power supply may be implemented by using a plurality of different voltages, have different generation manners, and have different symbols, such as VCC, VDD or other symbols, for identification and distinction, and still should be considered as falling within the concept of "system power supply" herein.

The second mirror branch includes a second upper arm transistor QP2 and a second lower arm transistor QN2, the control terminal of the first upper arm transistor QP1 is connected to the control terminal of the second upper arm transistor QP2 and further connected to the second terminal of the second upper arm transistor QP2, the first terminal of the second upper arm transistor QP2 is coupled to receive the system power of the integrated circuit chip, the second terminal of the second upper arm transistor QP2 is further connected to the first terminal of the pull-up switch M2, the second lower arm transistor QN2 is coupled between the second terminal of the pull-up switch M2 and the chip ground CGND, and is controlled by a dynamic reference bias signal Vbias, which is generated based at least on the transistor current sense signal VCS. Here and hereinafter, "chip ground" refers to the lowest potential point of the chip or die (die) on which the circuit is located.

The controlled current source 101 further comprises a dynamic reference operator 201 for generating a dynamic reference bias signal VBias based at least on the transistor current sense signal VCS. In the illustrated embodiment, the dynamic reference operator 201 receives a reference voltage VREF1, a first reference current IREF1 output by a constant current source, and a second reference current IREF2 output by another constant current source in addition to the transistor current sensing signal VCS, to calculate a dynamic reference bias signal Vbias, which may be obtained based on an analog current operation, or may be obtained based on other suitable operation modes, such as an analog voltage operation, a digital operation, etc., which is not limited in this aspect of the present invention. In the following embodiments, for illustrative purposes, description will be made mainly based on related embodiments of current operation.

Those skilled in the art will appreciate that in the illustrated embodiment, the "upper arm transistor" refers to a P-type MOS transistor and the "lower arm transistor" refers to an N-type MOS transistor. In other embodiments, the "upper arm transistor" and "lower arm transistor" may also be configured as other types of transistors capable of performing a mirror current function, so long as an active mirror current source is formed.

With the dynamic reference bias signal Vbias, when the pull-up switch M1 is turned on, the current I2 flowing on the second mirror leg is set by the dynamic reference Vbias by controlling the second lower arm transistor QN 2. In general, the current flowing through the first mirrored branch, i.e. the controlled current IB, may be multiplied by the current flowing through the second mirrored branch by setting a mirror relationship, e.g. preferably ib=k×i2, k being an integer greater than 1.

Fig. 4 shows a schematic circuit diagram of a dynamic reference arithmetic unit 201 according to an embodiment of the present invention, as shown in fig. 4, the dynamic reference arithmetic unit 201 includes a third mirror circuit and a current extraction circuit 211, the current extraction circuit 211 extracts a dynamic current ICOM from the third mirror circuit, the dynamic current ICOM is generated at least based on a transistor pole current sensing signal VCS, and the dynamic current ICOM gradually becomes smaller until zero after the bipolar transistor Q1 is turned on.

In the illustrated embodiment, the third mirror circuit includes a first reference current source IS1, a third upper arm transistor QP3 and a third lower arm transistor QN3, where a first terminal of the first reference current source IS1 IS coupled to receive the system power VCC of the integrated circuit chip, and a second terminal of the first reference current source IS1 outputs a first reference current IREF1, and the current extraction circuit 211 extracts the dynamic current ICOM from the second terminal of the first reference current source IS 1. The first terminal of the third upper arm transistor QP3 IS coupled to the second terminal of the first reference current source IS1, and the control terminal and the second terminal of the third upper arm transistor QP3 are interconnected. The control terminal and the first terminal of the third lower arm transistor QN3 are coupled to the second terminal of the third upper arm switch transistor QP3, and the second terminal of the third lower arm transistor QN3 is connected to the chip CGND. Wherein a second terminal of the third upper arm transistor QP3 outputs a dynamic reference bias signal VBias.

Because the third mirror branch and the second mirror branch are also in mirror image relationship, by outputting the dynamic reference bias signal VBias, when the pull-up switch M2 is turned on, the current I2 flowing through the second mirror branch and the current I3 flowing through the third upper arm transistor QP3 on the third mirror branch can be in mirror image proportion relationship, and indirectly, IB and I3 are also in proportion mirror image relationship. Let i2=m×i3, ib=k×m×i3. And i3=iref1-ICOM, so when icom=0, i3=iref1, when I3 reaches a maximum value, the corresponding IB also reaches its maximum value, equal to iref1×k×m. By setting the magnitude of the first reference current IREF1, the maximum value of the controlled current IB can be obtained.

Fig. 4 further shows a detailed view of the current extraction circuit 211, and as shown in the drawing, the current extraction circuit 211 includes 5 current operation branches and a diode-connected PMOS transistor QCOM and an amplifier AMP4 in the manner of a current mirror branch. The 5 image branches are a fourth image branch, a fifth image branch, a sixth image branch, a seventh image branch and an eighth image branch, respectively. The fourth mirror branch includes a fourth upper arm transistor QP4 and a fourth lower arm transistor QN4 connected in series between the system power VCC and the chip ground CGND, and a fourth resistor R4, a first end of a PMOS transistor QCOM is connected to a first end of the third upper arm transistor QP3, a second end of the PMOS transistor QCOM is connected to the gate, and further connected to a common end of QP4 and QN4 (i.e., a second end of QP4 and a first end of QN 4), and a first end of QP4 is coupled to receive the system power. The control end of the QN4 is controlled by the amplifier AMP4, the positive input end of the AMP4 receives the first reference voltage VREF1, the negative input end is connected to the second end of the QN4, the second end of the QN4 is connected to the first end of the fourth resistor R4, and the second end of the fourth resistor R4 is connected to the chip ground CGND.

In the fourth mirror branch, the second terminal potential of QN4 will be clamped to VREF1 during operation due to the negative feedback effect of amplifier AMP4, so that the current I4 flowing through QN4 is constant, equal to VREF1/R4. The current flowing through QCOM is the extraction current ICOM, icom=i4-iup4=vref/R4-IUP 4, where IUP4 is the current flowing through QP 4.

Continuing to the fifth mirror leg, the fifth mirror leg includes a fifth upper arm transistor QP5 and a fifth lower arm transistor QN5, wherein a first terminal of QP5 is coupled to receive the system power VCC, and a control terminal is connected to the second terminal, and further connected to a control terminal of a fourth upper arm transistor QP4 and a first terminal of the fifth lower arm transistor QN 5. The sixth mirror circuit includes a sixth upper arm transistor QP6, a sixth lower arm transistor QN6, and a sixth resistor R6, where a first terminal of QP6 is coupled to receive the system power VCC, a second terminal of QP6 is coupled to the first terminal and the control terminal of the sixth lower arm transistor QN6, and a second terminal of QN6 is connected to the chip ground CGND through the sixth resistor R6. The seventh mirror circuit includes a seventh upper arm transistor QP7, a seventh lower arm transistor QN7, and a seventh resistor R7, where a first end of the seventh upper arm transistor QP7 is coupled to the receiving system power VCC, a second end is connected to the control end of the fifth lower arm transistor QN5 and the first end of the seventh lower arm transistor QN7, the control end of the seventh lower arm transistor QN7 is connected to the control end of the sixth lower arm transistor QN6, a second end of the seventh lower arm transistor QN7 is connected to the first end of the seventh resistor and the second end of the fifth lower arm transistor QN5, and the second end of the seventh resistor receives the transistor current sensing signal VCS. The eighth mirror branch includes an eighth upper arm transistor QP8 and a second reference current source IS2 for outputting a second reference current IREF2 from a second terminal thereof, wherein a first terminal of the eighth upper arm transistor QP8 IS coupled to the receiving system power VCC, and a control terminal IS connected to the control terminals of the sixth upper arm transistor QP6 and the seventh upper arm transistor QP7 and the second terminal of the QP 8. The second terminal of the eighth upper arm transistor QP8 IS further connected to a first terminal of the second reference current source IS2, and the second terminal of the second reference current source IS2 IS connected to the chip ground CGND.

In the fourth mirror branch, the current IUP4 of the fourth upper arm transistor QP4 has a mirror relationship with the current I5 flowing through the fifth mirror branch because the control terminal of QP4 is connected to the control terminal and the second terminal of the fifth upper arm transistor, and in this embodiment, the fourth mirror branch and the fifth mirror branch are set to have a relationship of 1:n, i.e., iup4=n×i5. At the same time, the current I5 finally flows into the seventh mirror branch and into the seventh resistor R7. Therefore, the current I7 at R7 across the seventh resistor is the sum of the currents I5 flowing through the seventh lower arm transistor (IUP 7), i.e. I7 = iup7+i5 = iup7+ IUP4/n, in other words iup4= (I7-IUP 7) n. Since the control terminals of the seventh lower arm upper arm transistor and the eighth upper arm transistor are connected to the second terminal of the eighth upper arm transistor in an interconnection and cut manner, there is a mirror relationship between the two branches, and when the mirror ratio is 1:1, the current I8 (i.e., IREF 2) =iup7, i.e., iup7=iref2 of the eighth mirror branch. Meanwhile, the current I6 of the sixth mirror branch is also mirrored in the eighth mirror branch, when the mirror ratio is 1: at q, i6=q×iref2. Thus, since the first terminal voltage of the sixth resistor R6 is q×iref2/R6 and the control terminals of the seventh lower arm transistor QN7 and the sixth lower arm transistor QN6 are connected to each other, at this time, the first terminal voltage of the seventh resistor R7 is q×iref2×r6, and the current i7= (q×iref2×r6—vcs)/R7 through the seventh resistor.

From the above derivation, it is possible to obtain: iup4= [ (q x IREF2 x R6-VCS)/R7-IREF 2 x n, bring icom=vref/R4-IUP 4, resulting in a pull current:

ICOM＝VREF/R4-[(q*IREF2*R6-VCS)/R7-IREF2]*n。

i.e. ICOM has a forward linear relationship with VCS. Since VCS is a negative value with respect to chip ground CGND, when transistor current IC flowing through Q1 rises, vcs= -j IC correspondingly drops, and ICOM correspondingly drops until ICOM becomes zero, specifically:

ICOM＝VREF/R4-[(q*IREF2*R6+j*IC)/R7-IREF2]*n

IB＝k*m*I3＝k*m*(IREF1-ICOM)

＝k*m*(IREF1-VREF/R4)+k*m*n[(q*IREF2*R6+j*IC)/R7-IREF2]

i.e., IB forward linear with respect to IC. At the initial time of Q1 conduction, a desired IB initial value IB0 can be obtained by reasonably setting the correspondence of VREF, IREF2, and IREF1, and the coefficient j, k, m, n, Q.

Those skilled in the art will appreciate that the detailed structural description of the current extraction circuit 211 above is merely an example illustrated according to one embodiment of the present invention, and that the structure of the current extraction circuit 211, and the design of the mathematical relationship of the currents, are not limited to the above-described embodiments. In other embodiments, the current extraction circuit 211 may be implemented using any other structure capable of performing mathematical operations, and the mathematical relationships between IC, VCS and IB may be different from the formulas described above.

The above description of the control method and steps according to the embodiments of the present invention is merely exemplary, and is not intended to limit the present invention. In other instances, well known control steps, used control parameters, and the like have not been shown or described in detail in order to avoid obscuring the invention, in a clear, concise, and convenient manner. It will be appreciated by those skilled in the art that the step numbers used in the description of the control method and steps according to the embodiments of the present invention above are not intended to indicate the absolute sequence of steps, and that the steps are not performed in the order of step numbers, but may be performed in a different order, or may be performed concurrently and in parallel, and are not limited to just the described embodiments.

While the invention has been described with reference to several exemplary embodiments, it is to be understood that the terminology used is intended to be in the nature of words of description and of limitation. As the present invention may be embodied in several forms without departing from the spirit or essential characteristics thereof, it should also be understood that the above-described embodiments are not limited by any of the details of the foregoing description, but rather should be construed broadly within its spirit and scope as defined in the appended claims, and therefore all changes and modifications that fall within the meets and bounds of the claims, or equivalences of such meets and bounds are therefore intended to be embraced by the appended claims.

Claims (9)

1. A drive circuit for driving a bipolar transistor as a power switch in a switching power supply system, the bipolar transistor being coupled to a power inductor or transformer in the switching power supply system, wherein the drive circuit comprises:

a controlled current source for outputting a controlled current to provide a base current of the bipolar transistor, wherein the magnitude of the controlled current follows the current flowing through the bipolar transistor after the bipolar transistor is turned on during each duty cycle;

a pull-up switch coupled to the controlled current source for controlling the controlled current source to turn on and off;

a pull-down switch coupled to the base of the bipolar transistor for pulling down the base potential of the bipolar transistor;

wherein, in each duty cycle, at the moment when the bipolar transistor is turned on, the controlled current has an initial value which is not zero, the initial value being derived from the minimum value of the current flowing through the bipolar transistor, after the bipolar transistor starts to be turned on, the controlled current increases following the increase of the current of the bipolar transistor until it increases to a maximum value, and the controlled current rises to the maximum value and remains at the maximum value until the turn-off moment earlier than the turn-off moment when the pull-up switch controls the controlled current source.

2. The drive circuit of claim 1, wherein the controlled current linearly follows the current of the bipolar transistor during each duty cycle.

3. The drive circuit of claim 1, wherein, during each duty cycle, the pull-up switch turns off the controlled current source at a time earlier than the pull-down switch pulls down the bipolar transistor base potential.

4. The drive circuit of claim 3, wherein the pull-up switch is controlled by a first pulse width modulation signal and the pull-down switch is controlled by a second pulse width modulation signal, the first pulse width modulation signal controlling the pull-up switch to turn off the controlled current source when the current of the bipolar transistor rises to a first reference value during the turn-on of the bipolar transistor, the second pulse width modulation signal controlling the pull-down switch to pull down the base potential of the bipolar transistor when the current of the bipolar transistor continues to rise to a second reference value.

5. The drive circuit of claim 1, wherein the controlled current source receives a transistor current sense signal as a basis for controlling the controlled current, the transistor current sense signal being indicative of current flowing through the bipolar transistor.

6. The drive circuit of claim 5, wherein the drive circuit is located in an integrated circuit chip, the controlled current source comprises a mirrored current source comprising:

a first mirror branch including a first upper arm transistor having a first end coupled to receive system power from the integrated circuit chip, a second end coupled to the base of the bipolar transistor and to a first end of the pull-down switch, and a second end coupled to a chip ground of the integrated circuit chip;

a second mirror branch comprising a second upper arm transistor and a second lower arm transistor, the control terminal of the first upper arm transistor being connected to the control terminal of the second upper arm transistor and further connected to the second terminal of the second upper arm transistor, the first terminal of the second upper arm transistor being coupled to receive system power from the integrated circuit chip, the second terminal of the second upper arm transistor being further connected to the first terminal of the pull-up switch, the second lower arm transistor being coupled between the second terminal of the pull-up switch and the chip ground and being controlled by a dynamic reference bias signal generated based at least on the transistor current sense signal;

the controlled current source further includes a dynamic reference operator for generating the dynamic reference bias signal based at least on the transistor current sense signal.

7. The drive circuit of claim 6, wherein the dynamic reference operator includes a third mirrored branch and a current extraction circuit that extracts a dynamic current from the third mirrored branch, the dynamic current being generated based at least on the transistor current sense signal, the dynamic current gradually decreasing until zero after the bipolar transistor is turned on;

the third mirror leg includes:

a first reference current source, a first end coupled to receive the system power of the integrated circuit chip, and a second end outputting a first reference current, wherein the current extraction circuit extracts the dynamic current from the second end of the first reference current source;

a third upper arm transistor, a first end of which is coupled with a second end of the first reference current source, and a control end of which is connected with the second end of the third upper arm transistor;

a third lower arm transistor having a control terminal and a first terminal coupled to a second terminal of the third upper arm transistor, the second terminal being connected to the chip ground;

wherein the second end of the third upper arm transistor outputs the dynamic reference bias signal.

8. A switching power supply system, wherein the power switch of the switching power supply system comprises at least a bipolar transistor, the bipolar transistor being coupled to a power inductor or a transformer in the switching power supply system, the bipolar transistor being driven by the driving circuit according to any of claims 1-7.

9. The switching power supply system of claim 8 wherein said switching power supply system further comprises a transistor current sampling resistor, a first terminal of said transistor current sampling resistor being connected to an emitter of said bipolar transistor and a second terminal of said transistor current sampling resistor being connected to system ground at a terminal of said pull-down switch remote from a base of said bipolar transistor, said driver circuit being located in an integrated circuit chip having a chip ground that is the first terminal of said transistor current sampling resistor.