CN114335279A - Flip high-voltage light-emitting diode chip and preparation method thereof - Google Patents
Flip high-voltage light-emitting diode chip and preparation method thereof Download PDFInfo
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- CN114335279A CN114335279A CN202210244023.1A CN202210244023A CN114335279A CN 114335279 A CN114335279 A CN 114335279A CN 202210244023 A CN202210244023 A CN 202210244023A CN 114335279 A CN114335279 A CN 114335279A
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Abstract
The invention discloses a flip high-voltage light emitting diode chip and a preparation method thereof, wherein the chip comprises: the light-emitting diode comprises a substrate, an epitaxial layer, an isolation groove for isolating the epitaxial layer into at least two independent light-emitting units, a current blocking layer, a current expansion layer, an electrode layer, a Bragg reflection layer and a bonding pad layer; the angle of the isolation groove is 25-60 degrees, the independent light-emitting unit at least comprises X first light-emitting units and Y second light-emitting units, and the first light-emitting units and the second light-emitting units are arranged adjacently; the electrode layer comprises a P-type electrode and an N-type electrode which are arranged on the first light-emitting unit, a P-type electrode and an N-type electrode which are arranged on the second light-emitting unit, and a bridging electrode which is used for connecting the N-type electrode of the first light-emitting unit and the P-type electrode of the second light-emitting unit. The invention can solve the problems that the inverted high-voltage chip has low EOS capability in the prior art, so that the inverted high-voltage chip is stopped in illumination application and cannot be widely applied to the field of backlight display in a large scale.
Description
Technical Field
The invention relates to the technical field of chips, in particular to a flip high-voltage light emitting diode chip and a preparation method thereof.
Background
The LED chip is widely applied to two fields of illumination and display with the advantages of environmental protection, energy conservation, high efficiency, high reliability and the like.
In recent years, with the support of national policies and the active competition of various manufacturers, the light emitting diode chip gradually evolves from the original front-mounted chip to a high voltage chip, a flip chip and a flip high voltage chip. The high-voltage chip is gradually accepted by the market by the advantages of high luminous efficiency, reduced driving wire resistance and the like, but the existing flip high-voltage chip has low EOS capability, and the backlight display has extremely high requirement on the EOS capability, so that the flip high-voltage chip is stopped in lighting application and cannot be widely applied to backlight display in a large quantity, and how to improve the EOS capability of the flip high-voltage light-emitting diode chip becomes an urgent problem to be solved.
Disclosure of Invention
Aiming at the defects of the prior art, the invention aims to provide a flip high-voltage light emitting diode chip and a preparation method thereof, and aims to solve the problems that the EOS capability of the flip high-voltage chip is low, so that the flip high-voltage chip is stopped in lighting application and cannot be widely applied to backlight display in a large quantity in the prior art.
A first aspect of the present invention provides a flip-chip high voltage light emitting diode chip, the chip comprising: the light-emitting diode comprises a substrate, an epitaxial layer, an isolation groove for isolating the epitaxial layer into at least two independent light-emitting units, a current blocking layer, a current expansion layer, an electrode layer, a Bragg reflection layer and a bonding pad layer;
the angle of the isolation groove is 25-60 degrees, the independent light-emitting units at least comprise X first light-emitting units and Y second light-emitting units, the first light-emitting units and the second light-emitting units are arranged adjacently, and X, Y are integers which are not less than 1;
the electrode layer comprises a P-type electrode and an N-type electrode which are arranged on the first light-emitting unit, a P-type electrode and an N-type electrode which are arranged on the second light-emitting unit, and a bridging electrode which is used for connecting the N-type electrode of the first light-emitting unit and the P-type electrode of the second light-emitting unit.
According to an aspect of the above technical solution, the width of the bridge electrode is 20 um-50 um.
According to an aspect of the above technical solution, the angle of the isolation groove is 45 °, and the width of the bridging electrode is 30 um.
According to an aspect of the above technical solution, the angle of the isolation groove is 30 °, and the width of the bridging electrode is 35 um.
According to an aspect of the above technical solution, the angle of the isolation groove is 35 °, and the width of the bridging electrode is 40 um.
According to an aspect of the foregoing technical solution, the pad layer is disposed on the bragg reflection layer, and the pad layer includes a P-type pad layer disposed on the bragg reflection layer of the first light emitting unit, and an N-type pad layer disposed on the bragg reflection layer of the second light emitting unit.
According to one aspect of the foregoing technical solution, a P-type reflection through hole is formed in the bragg reflection layer of the first light emitting unit, and the P-type pad layer is in contact with the P-type electrode of the first light emitting unit through the P-type reflection through hole to form an electrical connection;
and the Bragg reflection layer of the second light-emitting unit is provided with an N-type reflection through hole, and the N-type welding disc layer is in contact with the N-type electrode of the second light-emitting unit through the N-type reflection through hole to form electric connection.
A second aspect of the present invention is to provide a method for manufacturing a flip-chip high-voltage light emitting diode chip, where the method is used to manufacture the flip-chip high-voltage light emitting diode chip in the above technical solution, and the method includes:
providing a substrate;
manufacturing an epitaxial layer on the substrate, wherein the epitaxial layer sequentially comprises a buffer layer, an N-type semiconductor layer, an active layer and a P-type semiconductor layer from bottom to top;
etching the epitaxial layer to manufacture an MESA step;
etching the epitaxial layer to the substrate to obtain an isolation groove, wherein the isolation groove isolates the epitaxial layer into at least two independent light-emitting units; the independent light-emitting units at least comprise X first light-emitting units and Y second light-emitting units, the first light-emitting units and the second light-emitting units are arranged adjacently, and X, Y are integers which are not less than 1;
manufacturing a current barrier layer on the surface of the epitaxial layer;
manufacturing a current expansion layer on the surfaces of the current barrier layer and the epitaxial layer;
manufacturing electrode layers on the surfaces of the MESA steps and the current expansion layer; the electrode layer comprises a P-type electrode of the first light-emitting unit and an N-type electrode of the first light-emitting unit, a P-type electrode of the second light-emitting unit and an N-type electrode of the second light-emitting unit, and a bridging electrode for connecting the N-type electrode of the first light-emitting unit and the P-type electrode of the second light-emitting unit;
manufacturing Bragg reflection layers on the surfaces of the electrode layer, the isolation groove, the MESA step and the current expansion layer;
and manufacturing a pad layer on the surface of the Bragg reflection layer.
According to one aspect of the above technical solution, in the step of etching the epitaxial layer to the substrate to obtain the isolation trench, an angle of the isolation trench is 25 ° to 60 °.
Compared with the prior art, the flip high-voltage light emitting diode chip and the preparation method thereof have the advantages that:
according to the invention, the epitaxial layer is isolated from at least two independent light-emitting units through the isolation groove, the adjacent independent light-emitting units are connected through the bridging electrode of the electrode layer, and the angle of the isolation groove is greatly reduced compared with the prior art, so that the width and the thickness of the bridging electrode covered on the isolation groove are correspondingly increased, the cross section area of the bridging electrode is increased, the wire resistance is reduced, the conductivity of the bridging electrode is improved, the EOS (operating on) capability of the flip high-voltage light-emitting diode chip is improved, and the flip high-voltage light-emitting diode chip can be widely applied to the backlight display field such as illumination.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
FIG. 1 is a schematic top view of a high voltage LED flip chip according to a first embodiment of the present invention;
FIG. 2 is a sectional view taken along line A-A of FIG. 1;
FIG. 3 is a schematic top view of a high voltage LED flip chip according to a second embodiment of the present invention;
FIG. 4 is a schematic top view of a high voltage LED flip chip according to a third embodiment of the present invention;
FIG. 5 is a schematic flow chart illustrating a method for manufacturing a flip-chip high-voltage LED chip according to a fourth embodiment of the present invention;
description of reference numerals:
51-substrate, 521-buffer layer, 522-N type semiconductor layer, 523-active layer, 524-P type semiconductor layer, 53-current blocking layer, 54-current spreading layer, 551-P type electrode of first light emitting unit, 552-N type electrode of first light emitting unit, 553-bridge electrode, 554-P type electrode of second light emitting unit, 555-N type electrode of second light emitting unit, 56-Bragg reflection layer, 561-P type reflection via, 562-N type reflection via, 571-P type pad layer, 572-N type pad layer, 58-MESA step, 59-isolation groove.
Detailed Description
In order to make the objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. Several embodiments of the invention are presented in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. As used herein, the terms "vertical," "horizontal," "left," "right," "up," "down," and the like are used for descriptive purposes only and not for purposes of indicating or implying that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be construed as limiting the invention.
In the present invention, unless otherwise expressly specified or limited, the terms "mounted," "connected," "fixed," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
Example one
Referring to fig. 1-2, a flip-chip high voltage led chip according to a first embodiment of the present invention includes: the light-emitting diode comprises a substrate 51, an epitaxial layer, an isolation groove 59 for isolating the epitaxial layer into at least two independent light-emitting units, a current blocking layer 53, a current extension layer 54, an electrode layer, a Bragg reflection layer 56 and a pad layer; as will be readily understood by those skilled in the art, the epitaxial layer sequentially includes a buffer layer 521, an N-type semiconductor layer 522, an active layer 523 and a P-type semiconductor layer 524 from bottom to top, and the MESA step 58 is disposed on the epitaxial layer to expose the N-type semiconductor layer 522, so as to fabricate an N-type electrode on the N-type semiconductor layer 522.
The independent light-emitting units at least comprise X first light-emitting units and Y second light-emitting units, the first light-emitting units and the second light-emitting units are arranged adjacently, and X, Y are integers which are not less than 1;
by way of example and not limitation, X is equal to Y, i.e., the number of the first light emitting units is equal to the number of the second light emitting units, i.e., the isolation trench 59 needs to isolate the epitaxial layer into an even number of independent light emitting units, e.g., two or four; of course, X and Y may also be unequal, that is, the number of the first light-emitting units is unequal to the number of the second light-emitting units, specifically, the number of the first light-emitting units is always one more than the number of the second light-emitting units, for example, when the number of the independent light-emitting units is three, the number of the first light-emitting units is two, and only one second light-emitting unit is located between two first light-emitting units.
It should be noted that, a first independent light-emitting unit on the whole chip is always a first light-emitting unit, and a second independent light-emitting unit adjacent to the first independent light-emitting unit is a second light-emitting unit; when the number of the independent light-emitting units is more than or equal to 3, a third independent light-emitting unit adjacent to a second independent light-emitting unit is a second first light-emitting unit, a fourth independent light-emitting unit adjacent to the third independent light-emitting unit is a second light-emitting unit, and so on.
When the epitaxial layer is separated into at least two independent light emitting units by the isolation trench 59, in order to electrically connect the two adjacent independent light emitting units, in the present embodiment, the electrode layer includes a P-type electrode 551 of the first light emitting unit and an N-type electrode 552 of the first light emitting unit, a P-type electrode 554 of the second light emitting unit and an N-type electrode 555 of the second light emitting unit, and a bridging electrode 553 for connecting the N-type electrode 552 of the first light emitting unit and the P-type electrode 554 of the second light emitting unit. That is, the N-type electrode 552 of the first light emitting unit and the P-type electrode 554 of the second light emitting unit, which are adjacently disposed, are bridged by the bridging electrode 553, for example, the first independent light emitting unit (the first light emitting unit) and the second independent light emitting unit (the second light emitting unit) are bridged by the bridging electrode 553 between the N-type electrode and the P-type electrode between the two adjacent independent light emitting units, and the second independent light emitting unit (the second light emitting unit) and the third independent light emitting unit (the first light emitting unit) are bridged by the bridging electrode 553 between the N-type electrode and the P-type electrode between the two adjacent independent light emitting units.
In summary, two adjacent independent light emitting cells are bridged by the bridging electrode 553, and therefore, the conductivity of the bridging electrode 553 should meet the usage requirement. However, the angle of the isolation trench of the conventional flip-chip high-voltage light emitting diode chip is generally 70-80 °, which results in a smaller thickness of the bridging electrode coated on the isolation trench and a smaller width of the bridging electrode being 5-15 um, so the cross-sectional area of the bridging electrode is smaller, which results in a larger line resistance, when an EOS test is performed, the bridging electrode is instantly fused when encountering a large current impact, and the EOS capability of the chip is low.
In order to solve the problem of low EOS capability of the chip, in the embodiment, the angle of the isolation groove 59 for separating the epitaxial layer into a plurality of independent light emitting units is 25 ° to 60 °, and compared with the prior art, the angle of the isolation groove is greatly reduced, so that the width of the bridging electrode coated on the isolation groove is greatly increased, and correspondingly, the thickness of the bridging electrode is also greatly increased, specifically, the width of the bridging electrode is 20um to 50 um. In conclusion, the improved bridging electrode has larger cross-sectional area, smaller wire resistance and effectively improved conductivity, and when EOS test is carried out, the bridging electrode is not easy to fuse when encountering heavy current impact, namely, the EOS capability of the chip is higher, so that the flip high-voltage chip can be applied to the backlight display field such as illumination.
TABLE 1
| Bridging electrode widths | Angle of isolation groove | EOS capability |
| 15 | 75° | 34V |
| 15 | 60° | 40V |
| 15 | 45° | 46V |
| 15 | 30° | 50V |
| 15 | 20° | 52V |
| 20 | 45° | 50V |
| 25 | 45° | 54V |
| 30 | 45° | 58V |
| 40 | 35° | 62V |
| 35 | 30° | 64V |
| 45 | 45° | 68V |
| 50 | 45° | 68V |
| 55 | 45° | 68V |
Table 1 is a comparison table of EOS capability for different isolation trench angles and different bridge electrode widths.
As an example, in the present embodiment, the angle of the isolation groove 59 for separating the epitaxial layer into the plurality of independent light emitting cells is 45 °, and when the angle of the isolation groove 59 is 45 °, the width of the bridge electrode 553 is 30 um. With reference to table 1, the EOS capability of the flip-chip high voltage led chip is 58V, which is improved by about 70% compared to the width of the bridging electrode 553 of 15um, the angle of the isolation trench 59 of 75 °, and the EOS capability of 34V in the prior art example.
In this embodiment, the pad layer is disposed on the bragg reflector 56, and the pad layer includes a P-type pad layer 571 disposed on the bragg reflector 56 of the first light-emitting unit, and an N-type pad layer 572 disposed on the bragg reflector 56 of the second light-emitting unit.
Specifically, a P-type reflection via 561 is disposed on the bragg reflection layer 56 of the first light emitting unit, and the P-type pad layer 571 is in contact with the P-type electrode 551 of the first light emitting unit through the P-type reflection via 561 to form an electrical connection; an N-type reflection through hole 562 is formed in the bragg reflection layer 56 of the second light emitting unit, and the N-type pad layer 572 is in contact with the N-type electrode 555 of the second light emitting unit through the N-type reflection through hole 562 to form electrical connection.
Compared with the prior art, adopt the flip-chip high voltage light emitting diode chip that shows among the embodiment, beneficial effect lies in:
this embodiment separates at least two independent luminescence units with the epitaxial layer through isolating slot 59, connect through the bridge electrode 553 of electrode layer between the adjacent independent luminescence unit, because isolating slot 59's angle compares and reduces in prior art by a wide margin, so the width and the thickness of the bridge electrode 553 of cladding on isolating slot 59 correspond the increase, bridge electrode 553's cross-sectional area increases, the line resistance reduces, so just promoted bridge electrode 553's electric conductive property, the EOS ability of this flip-chip high voltage light emitting diode chip has been promoted, thereby make this flip-chip high voltage light emitting diode chip can extensively apply to backlight display fields such as illumination.
Example two
Referring to fig. 3, a flip-chip high voltage led chip according to a second embodiment of the present invention has a structure substantially the same as that of the flip-chip high voltage led chip according to the first embodiment, and the difference is that:
in the present embodiment, the angle of the isolation trench 59 is 30 °, and the width of the bridging electrode 553 is 35 um.
Referring to table 1 again, in the present embodiment, the angle of the isolation trench 59 for separating the epitaxial layer into a plurality of independent light emitting units is 30 °, and when the angle of the isolation trench 59 is 30 °, the width of the bridge electrode 553 is 35um, and the EOS capability of the flip-chip high voltage light emitting diode chip is 64V, which is about 88% higher than that of the flip-chip high voltage light emitting diode chip in the prior art.
EXAMPLE III
Referring to fig. 4, a flip-chip high voltage led chip according to a third embodiment of the present invention has a structure substantially the same as that of the flip-chip high voltage led chip according to the first embodiment, and the difference is that:
in the present embodiment, the angle of the isolation trench 59 is 30 °, and the width of the bridging electrode 553 is 35 um.
Referring to table 1 again, in the present embodiment, the angle of the isolation trench 59 for separating the epitaxial layer into a plurality of independent light emitting units is 35 °, and when the angle of the isolation trench 59 is 35 °, the width of the bridge electrode 553 is 40um, and the EOS capability of the flip-chip high voltage light emitting diode chip is 62V, which is about 82% higher than that of the flip-chip high voltage light emitting diode chip in the prior art.
Example four
Referring to fig. 5, a fourth embodiment of the present invention provides a method for manufacturing a flip-chip high voltage light emitting diode chip, where the method is used to manufacture the flip-chip high voltage light emitting diode chip in the above embodiments, and the method includes steps S10-S90:
step S10, providing a substrate;
step S20, manufacturing an epitaxial layer on the substrate, wherein the epitaxial layer sequentially comprises a buffer layer, an N-type semiconductor layer, an active layer and a P-type semiconductor layer from bottom to top;
step S30, etching the epitaxial layer to obtain an MESA step;
step S40, etching the epitaxial layer to the substrate to obtain an isolation groove, wherein the isolation groove isolates the epitaxial layer into at least two independent light-emitting units; the angle of the isolation groove is 25-60 degrees, the independent light-emitting units at least comprise X first light-emitting units and Y second light-emitting units, the first light-emitting units and the second light-emitting units are arranged adjacently, and X, Y are integers which are not less than 1;
step S50, manufacturing a current barrier layer on the surface of the epitaxial layer;
step S60, manufacturing a current expansion layer on the surfaces of the current barrier layer and the epitaxial layer;
step S70, manufacturing electrode layers on the surfaces of the MESA steps and the current spreading layer; the electrode layer comprises a P-type electrode of the first light-emitting unit and an N-type electrode of the first light-emitting unit, a P-type electrode of the second light-emitting unit and an N-type electrode of the second light-emitting unit, and a bridging electrode connecting the N-type electrode 552 of the first light-emitting unit and the P-type electrode of the second light-emitting unit;
step S80, manufacturing Bragg reflection layers on the surfaces of the electrode layer, the isolation groove, the MESA step and the current expansion layer;
step S90, a pad layer is formed on the surface of the bragg reflector.
Specifically, the method for manufacturing a flip-chip high-voltage light emitting diode chip shown in this embodiment includes:
firstly, providing a substrate;
preparing an epitaxial layer (metal organic chemical vapor deposition) on the substrate by utilizing an MOCVD (metal organic chemical vapor deposition) process, wherein the epitaxial layer sequentially comprises a buffer layer, an N-type semiconductor layer, an active layer and a P-type semiconductor layer from bottom to top;
preparing an MESA step, coating photoresist on the surface of the epitaxial layer, exposing and developing to form a pattern, removing part of the P-type semiconductor layer, the active layer and the N-type semiconductor layer by utilizing an ICP (inductively coupled plasma) etching process to expose the MESA step, and removing the photoresist;
preparing an isolation groove, forming a pattern by utilizing a photoetching process, exposing partial MESA steps, removing partial exposed MESA steps by utilizing an ICP (inductively coupled plasma) etching process, etching to a substrate to form the isolation groove, and isolating the epitaxial layer into at least two independent light-emitting units;
preparing a current barrier layer, and depositing SiO on the surfaces of the isolation groove, the MESA step and the epitaxial layer by using a PECVD process2Or SiN, then using a photolithography process on the SiO2Forming a pattern on the surface, and removing partial SiO by using BOE corrosive liquid2Then removing the photoresist to formA current blocking layer;
preparing a current expansion layer, namely depositing ITO (indium tin oxide) on the surfaces of the current barrier layer, the isolation groove, the MESA step and the epitaxial layer by using a magnetron sputtering process, forming a pattern by using a photoetching process, removing part of the ITO by using an ITO corrosive liquid, and removing photoresist to form the current expansion layer;
preparing an electrode layer, namely coating negative photoresist on the surfaces of an isolation groove, an MESA step and a current expansion layer, exposing and developing to form a pattern, then evaporating a metal layer by using an electron beam evaporation process, then stripping Off part of metal by using a Lift-Off process, and removing the photoresist to form the electrode layer, wherein the electrode layer comprises a P-type electrode and an N-type electrode of a first light-emitting unit, a P-type electrode and an N-type electrode of a second light-emitting unit, and a bridging electrode for connecting the N-type electrode of the first light-emitting unit and the P-type electrode of the second light-emitting unit, and the electrode layer comprises one or more of Cr, Al, Ag, Ni, Ti, Pt and Au;
preparing a Bragg reflection layer, namely sequentially evaporating a plurality of pairs of material pairs consisting of high-refractive-index materials and low-refractive-index materials on the surfaces of the electrode layer, the isolation groove, the MESA step and the current expansion layer by using an electron beam evaporation process, forming a pattern on the surface of the material pairs by using a photoetching process, removing part of the Bragg reflection layer by using an ICP (inductively coupled plasma) etching process, and removing photoresist, wherein the Bragg reflection layer comprises a P-type reflection through hole arranged in the first light-emitting unit and an N-type reflection through hole arranged in the second light-emitting unit; the high refractive index material can be TiO or TiO2、Ti3O5(ii) a The low refractive index material may be SiO2、SiN；
And then preparing a pad layer, namely coating a negative photoresist on the surface of the Bragg reflection layer, exposing and developing to form a pattern, then evaporating a metal layer by using an electron beam evaporation process, stripping Off part of metal by using a Lift-Off process after the metal layer is removed, removing the photoresist, and forming the pad layer, wherein the pad layer comprises one or more of metal Cr, Al, Ag, Ni, Ti, Pt and Au, and the pad layer comprises a P-type pad layer and an N-type pad layer.
Compared with the prior art, the preparation method of the flip high-voltage light emitting diode chip has the advantages that:
this embodiment is through the isolation groove with epitaxial layer isolation two at least independent luminescence units, connect through the bridge electrode of electrode layer between the adjacent independent luminescence unit, because the angle of isolation groove compares and reduces in prior art by a wide margin, so the width and the thickness of the bridge electrode of cladding on the isolation groove correspond the increase, the cross-sectional area of bridge electrode increases, the line resistance reduces, so just, the electric conductive property of bridge electrode has been promoted, the EOS ability of this flip high voltage light emitting diode chip has been promoted, thereby make this flip high voltage light emitting diode chip can extensively apply to backlight display fields such as illumination.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The above examples only show some embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the present invention. It should be noted that, for those skilled in the art, various changes and modifications can be made without departing from the spirit of the invention, and these changes and modifications are all within the scope of the invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (9)
1. A flip-chip high voltage light emitting diode chip, said chip comprising: the light-emitting diode comprises a substrate, an epitaxial layer, an isolation groove for isolating the epitaxial layer into at least two independent light-emitting units, a current blocking layer, a current expansion layer, an electrode layer, a Bragg reflection layer and a bonding pad layer;
the angle of the isolation groove is 25-60 degrees, the independent light-emitting units at least comprise X first light-emitting units and Y second light-emitting units, the first light-emitting units and the second light-emitting units are arranged adjacently, and X, Y are integers which are not less than 1;
the electrode layer comprises a P-type electrode and an N-type electrode which are arranged on the first light-emitting unit, a P-type electrode and an N-type electrode which are arranged on the second light-emitting unit, and a bridging electrode which is used for connecting the N-type electrode of the first light-emitting unit and the P-type electrode of the second light-emitting unit.
2. The flip-chip high voltage light emitting diode chip as claimed in claim 1, wherein the width of the bridging electrode is 20 um-50 um.
3. The flip chip high voltage led chip of claim 2, wherein the angle of the isolation trench is 45 °, and the width of the bridging electrode is 30 μm.
4. The flip chip high voltage led chip of claim 2, wherein the angle of the isolation trench is 30 °, and the width of the bridging electrode is 35 μm.
5. The flip chip high voltage led chip of claim 2, wherein the angle of the isolation trench is 35 °, and the width of the bridging electrode is 40 μm.
6. The flip chip high voltage led chip of any one of claims 1 to 5, wherein the bonding pad layer is disposed on the bragg reflector, and the bonding pad layer comprises a P-type bonding pad layer disposed on the bragg reflector of the first light emitting unit, and an N-type bonding pad layer disposed on the bragg reflector of the second light emitting unit.
7. The flip-chip high-voltage light emitting diode chip as claimed in claim 6, wherein the bragg reflection layer of the first light emitting unit is provided with a P-type reflection through hole, and the P-type pad layer is in contact with the P-type electrode of the first light emitting unit through the P-type reflection through hole to form an electrical connection;
and the Bragg reflection layer of the second light-emitting unit is provided with an N-type reflection through hole, and the N-type welding disc layer is in contact with the N-type electrode of the second light-emitting unit through the N-type reflection through hole to form electric connection.
8. A method for manufacturing a flip-chip high-voltage light-emitting diode chip, wherein the method is used for manufacturing the flip-chip high-voltage light-emitting diode chip as claimed in any one of claims 1 to 7, and the method comprises:
providing a substrate;
manufacturing an epitaxial layer on the substrate, wherein the epitaxial layer sequentially comprises a buffer layer, an N-type semiconductor layer, an active layer and a P-type semiconductor layer from bottom to top;
etching the epitaxial layer to manufacture an MESA step;
etching the epitaxial layer to the substrate to obtain an isolation groove, wherein the isolation groove isolates the epitaxial layer into at least two independent light-emitting units; the independent light-emitting units at least comprise X first light-emitting units and Y second light-emitting units, the first light-emitting units and the second light-emitting units are arranged adjacently, and X, Y are integers which are not less than 1;
manufacturing a current barrier layer on the surface of the epitaxial layer;
manufacturing a current expansion layer on the surfaces of the current barrier layer and the epitaxial layer;
manufacturing electrode layers on the surfaces of the MESA steps and the current expansion layer; the electrode layer comprises a P-type electrode of the first light-emitting unit and an N-type electrode of the first light-emitting unit, a P-type electrode of the second light-emitting unit and an N-type electrode of the second light-emitting unit, and a bridging electrode for connecting the N-type electrode of the first light-emitting unit and the P-type electrode of the second light-emitting unit;
manufacturing Bragg reflection layers on the surfaces of the electrode layer, the isolation groove, the MESA step and the current expansion layer;
and manufacturing a pad layer on the surface of the Bragg reflection layer.
9. The method for manufacturing the flip chip high voltage light emitting diode chip as claimed in claim 8, wherein in the step of etching the epitaxial layer to etch the substrate to obtain the isolation trench, the angle of the isolation trench is 25 ° to 60 °.
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| CN202210244023.1A CN114335279A (en) | 2022-03-14 | 2022-03-14 | Flip high-voltage light-emitting diode chip and preparation method thereof |
| CN202222499024.9U CN218039252U (en) | 2022-03-14 | 2022-09-21 | Flip high-voltage light-emitting diode chip |
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| CN202210244023.1A CN114335279A (en) | 2022-03-14 | 2022-03-14 | Flip high-voltage light-emitting diode chip and preparation method thereof |
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| CN218039252U (en) | 2022-12-13 |
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