CN114334802A - Method for manufacturing semiconductor structure - Google Patents

Abstract

The application relates to the technical field of semiconductors, in particular to a preparation method of a semiconductor structure, which comprises the following steps: forming a metal interconnection line on the semiconductor substrate; forming a first IMD layer above the metal interconnection line, and patterning the first IMD layer to form a first half through hole penetrating through the first IMD layer; forming a second IMD layer above the first IMD layer, and patterning the second IMD layer to form a second half via hole penetrating through the second IMD layer; the position of the first half through hole corresponds to the position of the second half through hole, and the first half through hole is communicated with the second half through hole to form a through hole. By depositing the IMD layer twice, the via hole can be formed by 2 times of etching, so that the upper size of the via hole can be controlled, the problem that the reliability of a metal interconnection line and the IMD is poor is solved, and the performance of a device is improved.

Description

Method for manufacturing semiconductor structure

Technical Field

The application relates to the technical field of semiconductors, in particular to a preparation method of a semiconductor structure.

Background

As the line width of electronic integrated circuits is gradually reduced, the reliability is also gradually decreased. In order to reduce the resistance of Metal wiring, low-resistance copper is currently used as a material for forming wiring, and when a multi-layer wiring is formed by a damascene method, the smaller the line width, the poorer the reliability (TDDB) between Metal interconnection lines and Inter-Metal dielectrics (IMD), which also becomes a limitation condition for semiconductor device design, and causes difficulties in design and process.

Disclosure of Invention

The present application addresses, at least to some extent, the above-mentioned technical problems in the related art. Therefore, the present application provides a method for manufacturing a semiconductor structure to solve the problem of poor reliability of metal interconnection lines and IMD.

In order to achieve the above object, a first aspect of the present application provides a method for manufacturing a semiconductor structure, comprising the steps of:

providing a semiconductor substrate;

forming a first metal interconnection line on the semiconductor substrate;

forming a first IMD layer above the first metal interconnection line, and patterning the first IMD layer to form a first half through hole penetrating through the first IMD layer;

forming a second IMD layer above the first IMD layer, patterning the second IMD layer, and exposing the top surface of the first metal interconnection line to form a second half via penetrating through the second IMD layer;

the position of the first half through hole corresponds to the position of the second half through hole, and the first half through hole is communicated with the second half through hole to form a through hole;

forming a via contact within the via.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the application. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:

FIG. 1 is a schematic diagram illustrating a top view of a via and a metal interconnect line in the prior art;

FIG. 2 shows a schematic structural diagram of a via and a metal interconnect line in an embodiment of the present application;

FIG. 3 shows a schematic diagram of a first half via formed in one embodiment of the present application;

FIG. 4 shows a schematic structural view of the deposition of a second IMD layer thickness on FIG. 3;

fig. 5 shows a schematic structural diagram of the use of the first mask plate in fig. 4;

FIG. 6 is a schematic structural diagram of a via hole formed after etching by using the first mask plate in FIG. 5;

fig. 7 shows a schematic structural diagram after forming a via contact, a second metal interconnect line on fig. 6.

Detailed Description

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.

Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.

In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.

In the prior art, as shown in fig. 1, in order to reduce the resistance of a via (Contact hole) in a semiconductor multilayer Metal interconnect structure, the via is generally made larger, so that the line width between Metal interconnects 11' is continuously reduced, in a conventional manufacturing process, the edge of the Metal interconnect 11' is generally consistent with the edge of a via 12' during design, but during the manufacturing process, due to continuous etching, the upper portion of the via 12' is always preferentially etched, so that the upper portion of the via 12' is oversized, and further deviates from the upper portion of the Metal interconnect 11', so that the reliability (TDDB) of the Metal interconnect 11' and the Inter-Metal Dielectric (IMD) is deteriorated, and the performance of the device is affected.

To solve the above problem, referring to fig. 2, a first aspect of the present application provides a semiconductor structure 100, where the semiconductor structure 100 includes: a semiconductor substrate (not shown), a third IMD layer 10, a first metal interconnection line 11, a first inter-metal dielectric (IMD) layer 12, a second inter-metal dielectric (IMD) layer 13, a via contact 14, and a second metal interconnection line 15.

The first metal interconnection line 11 is formed in the third IMD layer 10, the top surface of the first metal interconnection line 11 is flush with the surface of the third IMD layer 10, and the first IMD layer 12 and the second IMD layer 13 are stacked from bottom to top on the third IMD layer 10.

The semiconductor substrate may comprise a semiconductor material such as silicon, germanium, silicon-germanium, or the like, or a III-V semiconductor compound such as GaP, GaAs, GaSb, or the like. In some embodiments, the semiconductor substrate may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

Further, although not shown, the semiconductor substrate may include a conductive pattern. The conductive pattern may be a metal line, a contact, a conductive pad, etc., and may be a gate electrode of a transistor, a source/drain of a transistor, or a diode, but the embodiment is not limited thereto.

It is noted that the first IMD layer 12,The second IMD layer 13 may include a dielectric constant lower than that of silicon oxide (SiO)₂) A low-k material of dielectric constant (c). For example, the silicon oxide may have a dielectric constant of about 3.9 to about 4.5. The first IMD layer 12 and the second IMD layer 13 may have a dielectric constant of 3.5 or less. For example, the IMD layer 11 may have a dielectric constant of about 2.0 to about 3.5. In example embodiments, the first and second IMD layers 12 and 13 may include silicon oxide containing carbon and hydrogen (SiCOH). For example, first IMD layer 12, second IMD layer 13 may include about 10% to about 50% carbon. In some example embodiments, the first IMD layer 12 and the second IMD layer 13 may include silicon oxide doped with fluorine (F-SiO)₂) Porous silica, and the like.

Further, the first IMD layer 12 is formed using a step coverage difference dielectric material, and in particular, the step coverage difference dielectric material is used when the first IMD layer 12 is deposited, so that the first half via does not need to be protected by a substance additionally when the second IMD layer 13 is deposited and the metal interconnection line is dry-etched, that is, the first half via does not need to be filled with a substance.

The via contact 14 penetrates through the first IMD layer 12 and the second IMD layer 13 and is in contact with the first metal interconnection line 11, and the second metal interconnection line 15 penetrates through the second IMD layer 13 and penetrates through a part of the first IMD layer 12, wherein the via contact 14, the first metal interconnection line 11 and the second metal interconnection line 15 each comprise a metal filling layer and a metal barrier layer wrapping the side surface and the bottom surface of the metal filling layer, and the metal filling layer may comprise at least one of aluminum, copper, tungsten and cobalt. In example embodiments, the metal fill layer may include copper, and the metal barrier layer may include, for example, titanium nitride, tantalum nitride, and the like.

In addition, with reference to fig. 2, in this embodiment, a first etching stop layer 16 is disposed between the third IMD layer 10 and the first IMD layer 12, and a second etching stop layer 17 is disposed on a surface of the second IMD layer 13, specifically, the first etching stop layer 16 and the second etching stop layer 17 may be selected from materials with high etching selectivity.

A method of manufacturing the semiconductor structure 100 in the embodiment of the present application is described below.

The present application provides a method for fabricating a semiconductor structure 100, comprising the steps of:

a semiconductor substrate is provided and placed in the reaction chamber, which in this embodiment may comprise a semiconductor material such as silicon, germanium, silicon-germanium, or the like, or a III-V semiconductor compound such as GaP, GaAs, GaSb, or the like. In some embodiments, the semiconductor substrate may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

When the semiconductor substrate is a silicon-based semiconductor substrate, the semiconductor substrate may comprise, for example, dangling bonded silicon atoms that are not bonded to oxygen ions. The operating characteristics of the transistor may be stabilized by a hydrogen annealing process by which hydrogen atoms are bonded to dangling bonded silicon atoms of the semiconductor substrate. In this case, the hydrogen atom may be easily separated from the silicon atom, but boron may increase the binding energy between the silicon atom and the hydrogen atom. Therefore, the variable holding time or charge holding time of the capacitor can be improved.

Next, as shown in fig. 3, the third IMD layer 10 may be formed by a deposition process, and the first metal interconnection line 11 may be formed in the third IMD layer 10 by a conventional damascene process, followed by depositing the first etch stop layer 16 covering the third IMD layer 10 and the top surface of the first metal interconnection line 11, and then the first IMD layer 12 may be formed on the surface of the first etch stop layer 16 by depositing a low-k material having a dielectric constant lower than that of silicon oxide (SiO 2). In example embodiments, the first IMD layer 12 may be a silicon oxide (SiCOH) including carbon and hydrogen. For example, first IMD layer 12 may include about 10% to about 50% carbon. In some example embodiments, first IMD layer 12 may include fluorine-doped silicon oxide (F-SiO2) or porous silicon oxide. Finally, the first IMD layer 12 is subjected to patterning etching treatment by using a first mask plate 18, namely, a first half via hole 19 penetrating through the first IMD layer 12 and a part of the first etching stop layer 16 is formed; wherein, the etching treatment can use a dry etching process; the bottom dimension of the first half via 19 formed at this time is substantially the same as the via dimension formed by the conventional process;

next, as shown in fig. 4, a second IMD layer 13 is deposited on the first IMD layer 12, wherein the first IMD layer 12 is formed using a step coverage poor dielectric material;

it is worth mentioning that the thickness H of the first IMD layer 12 is at least less than half the thickness of the conventional IMD layer, compared to the thickness H of the conventional IMD layer.

Then, as shown in fig. 5-6, the second IMD layer 13 is patterned and etched by using the second reticle 20, and the top surfaces of the metal interconnection lines 11 are exposed, so as to form second half via holes penetrating through the second IMD layer 13, wherein the second half via holes correspond to the first half via holes 19 in position and are communicated with each other to form via holes 21; at the same time, the second mask plate 20 is used to form wiring grooves 22 penetrating the second IMD layer 13 and a part of the first IMD layer 12 in other regions of the second IMD layer 13;

at this time, the upper dimension of the second half via is smaller than the upper dimension of the first Metal interconnection line 11, so that the problem of poor reliability (TDDB) between the Metal interconnection line 11 and an Inter-Metal Dielectric (IMD) is solved, and the performance of the device is improved.

Next, as shown in fig. 7, a metal filling layer and a metal barrier layer are deposited on the via 21 and the metal wiring groove 22 by using a conventional damascene process, so as to form a via contact 14 in the via 21 and a second metal interconnection line 15 in the wiring groove 22;

next, with continued reference to fig. 2, a chemical mechanical planarization process is used to perform a planarization process, followed by deposition of a second etch stop layer 17.

It is worth noting that in the present embodiment, by depositing the IMD layer twice, the via hole can be formed by 2 times of etching, so that the upper dimension of the via hole can be controlled, the problem that the reliability of the metal interconnection line 11 and IMD (TDDB) is deteriorated is solved, and the performance of the device is improved.

The semiconductor structure in the present embodiment may be a volatile memory device such as a DRAM device, an SRAM device, or a nonvolatile memory device such as a flash memory device, a PRAM device, an MRAM device, an RRAM device, or the like.

Further, the semiconductor structure in this embodiment can be used in various chips.

Further, the chip having the above semiconductor structure may be used in various electronic devices, and specifically, the electronic devices may be a smart phone, a computer, a tablet computer, a wearable smart device, an artificial smart device, a mobile power supply, and the like.

In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.

The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.

Claims (9)

1. A method for fabricating a semiconductor structure, comprising:

providing a semiconductor substrate;

forming a first metal interconnection line on the semiconductor substrate;

forming a first IMD layer above the first metal interconnection line, and patterning the first IMD layer to form a first half through hole penetrating through the first IMD layer;

forming a second IMD layer above the first IMD layer, patterning the second IMD layer, and exposing the top surface of the first metal interconnection line to form a second half via penetrating through the second IMD layer;

the position of the first half through hole corresponds to the position of the second half through hole, and the first half through hole is communicated with the second half through hole to form a through hole;

forming a via contact within the via.

2. The method of claim 1, wherein a wiring trench is formed through the second IMD layer and a portion of the first IMD layer simultaneously with the formation of the second half via, and wherein a second metal interconnection line is formed within the wiring trench simultaneously with the formation of the via contact.

3. The method for manufacturing a semiconductor structure according to claim 2, wherein the thickness H of the first IMD layer is less than H/2, wherein H is the thickness of the IMD layer required for forming the second metal interconnection line.

4. The method of claim 1, further comprising the steps of, prior to forming the first IMD layer:

and forming a first etching stop layer on the first metal interconnection line, wherein the part of the first half via hole is formed in the first etching stop layer.

5. The method of claim 1, wherein the first IMD layer is formed using a step-coverage poor dielectric material.

6. The method of claim 1, further comprising the steps of, after forming the via contact:

and carrying out planarization treatment, and then forming a second etching stop layer on the second IMD layer.

7. The method of claim 1, further comprising the steps of, prior to forming the first metal interconnect line:

forming a third IMD layer on the semiconductor substrate; the first metal interconnection line is formed in the third IMD layer and is flush with the top surface of the third IMD layer.

8. The method of claim 1, wherein the step of patterning the first IMD layer comprises:

and carrying out patterning etching on the first IMD layer by using a first mask plate.

9. The method of claim 1, wherein the step of patterning the second IMD layer comprises:

and carrying out patterning etching on the second IMD layer by using a second mask plate.

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