CN114333706A

CN114333706A - Shifting register and driving method thereof, grid driving circuit and display device

Info

Publication number: CN114333706A
Application number: CN202210022114.0A
Authority: CN
Inventors: 袁志东; 李永谦; 吴仲远
Original assignee: BOE Technology Group Co Ltd; Hefei BOE Zhuoyin Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei BOE Zhuoyin Technology Co Ltd
Priority date: 2022-01-10
Filing date: 2022-01-10
Publication date: 2022-04-12
Anticipated expiration: 2042-01-10
Also published as: CN114333706B

Abstract

The embodiment of the disclosure provides a shift register, a driving method thereof, a gate driving circuit and a display device. The shift register comprises an input sub-circuit, an inverting sub-circuit and an output sub-circuit; the input sub-circuit provides a signal of the signal input end to the first node under the control of the first clock signal end, the inverting sub-circuit controls the potential of the second node under the control of the signal input end, the first clock signal end, the second clock signal end, the first node, the first power supply end and the second power supply end, and the output sub-circuit provides a signal of the first power supply end or the second power supply end to the signal output end under the control of the first node and the second node. The scheme provided by the disclosure realizes the control of the pulse width of the output signal of the signal output end of the shift register through the input of the control signal, thereby realizing the control of the pulse width of the gate drive signal.

Description

Shifting register and driving method thereof, grid driving circuit and display device

Technical Field

The embodiment of the disclosure relates to but is not limited to the technical field of display, and in particular relates to a shift register, a driving method thereof, a gate driving circuit and a display device.

Background

The current mature technologies in the Display field include Liquid Crystal Display (LCD) technology and Organic light-emitting diode (OLED) Display technology. The OLED technology forms a pattern by exciting a spectrum of various wavelengths by direct recombination of electrons and holes. The display device formed by the OLED technology has a fast response speed and can achieve the maximum contrast ratio, so that the OLED display device is expected to become a mainstream product for next generation display.

Since the Pulse Width of the gate driving signal provided by the gate driving circuit to the gate line is related to the operation performance of the pixel driving circuit inside the display panel, it is desirable to provide a control circuit having a Pulse Width Modulation (PWM) function.

Disclosure of Invention

The following is a summary of the subject matter described in detail in this disclosure. This summary is not intended to limit the scope of the claims.

The embodiments of the present disclosure provide a shift register, a driving method thereof, a gate driving circuit, and a display device, so as to control a pulse width of a gate driving signal.

In a first aspect, to implement control of a pulse width of a gate driving signal, the present disclosure provides a shift register, including an input sub-circuit, an inverting sub-circuit, and an output sub-circuit;

the input sub-circuit is respectively connected with the signal input end, the first clock signal end and the first node and is set to provide the signal of the signal input end to the first node under the control of the first clock signal end;

the inverting sub-circuit is respectively connected with the signal input end, the first power end, the second power end, the first clock signal end, the second clock signal end, the first node and the second node, and is configured to control the potential of the second node under the control of the signal input end, the first clock signal end, the second clock signal end, the first node, the first power end and the second power end;

the output sub-circuit is respectively connected with the first power supply end, the second power supply end, the first node, the second node and the signal output end, and is set to provide the signal of the first power supply end or the second power supply end for the signal output end under the control of the first node and the second node.

In an exemplary embodiment, the inverting sub-circuit includes a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a third capacitor;

a control electrode of the second transistor is connected with the second clock signal end, a first electrode of the second transistor is connected with the first power supply end, and a second electrode of the second transistor is connected with a third node;

a control electrode of the third transistor is connected to the signal input terminal, a first electrode of the third transistor is connected to the second clock signal terminal, and a second electrode of the third transistor is connected to the third node;

a control electrode of the fourth transistor is connected with the third node, a first electrode of the fourth transistor is connected with the first clock signal end, and a second electrode of the fourth transistor is connected with a fourth node;

a control electrode of the fifth transistor is connected with the first clock signal end, a first electrode of the fifth transistor is connected with the fourth node, and a second electrode of the fifth transistor is connected with the second node;

a control electrode of the sixth transistor is connected to the first node, a first electrode of the sixth transistor is connected to the second power supply terminal, and a second electrode of the sixth transistor is connected to the second node;

the first pole plate of the third capacitor is connected with the third node, and the second pole plate of the third capacitor is connected with the fourth node.

In an exemplary embodiment, the output sub-circuit includes a seventh transistor, an eighth transistor, a first capacitor, and a second capacitor;

a control electrode of the seventh transistor is connected to the first node, a first electrode of the seventh transistor is connected to the first power supply terminal, and a second electrode of the seventh transistor is connected to the signal output terminal;

a control electrode of the eighth transistor is connected to the second node, a first electrode of the eighth transistor is connected to the second power supply terminal, and a second electrode of the eighth transistor is connected to the signal output terminal;

a first pole plate of the first capacitor is connected with the first node, and a second pole plate of the first capacitor is connected with the signal output end;

the first plate of the second capacitor is connected with the second node, and the second plate of the second capacitor is connected with the second power supply end.

In an exemplary embodiment, the output sub-circuit further includes a ninth transistor; a first electrode of the eighth transistor is connected to the second power supply terminal through the ninth transistor;

a control electrode of the ninth transistor is connected to the second node, a first electrode of the ninth transistor is connected to the second power source terminal, and a second electrode of the ninth transistor is connected to the first electrode of the eighth transistor.

In an exemplary embodiment, the output sub-circuit further includes an eleventh transistor;

a control electrode of the eleventh transistor is connected with the signal output end, a first electrode of the eleventh transistor is connected with the first power supply end, and a second electrode of the eleventh transistor is connected with the fifth node; a first pole of the eighth transistor and a second pole of the ninth transistor are both connected to the fifth node.

In an exemplary embodiment, the output sub-circuit further includes a tenth transistor; a control electrode of the seventh transistor is connected to the first node through the tenth transistor;

a control electrode of the tenth transistor is connected to the first power source terminal, a first electrode of the tenth transistor is connected to the first node, and a second electrode of the tenth transistor is connected to the control electrode of the seventh transistor.

In an exemplary embodiment, the input sub-circuit includes a first transistor;

a control electrode of the first transistor is connected to the first clock signal terminal, a first electrode of the first transistor is connected to the signal input terminal, and a second electrode of the first transistor is connected to the first node.

In an exemplary embodiment, the input sub-circuit includes a first transistor; the inverting sub-circuit comprises a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a third capacitor; the output sub-circuit comprises a seventh transistor, an eighth transistor, a first capacitor and a second capacitor;

a control electrode of the first transistor is connected with the first clock signal end, a first electrode of the first transistor is connected with the signal input end, and a second electrode of the first transistor is connected with the first node;

the first pole plate of the third capacitor is connected with the third node, and the second pole plate of the third capacitor is connected with the fourth node;

In a second aspect, the present disclosure further provides a gate driving circuit, including a plurality of shift registers according to any of the above embodiments

In an exemplary embodiment, the gate driving circuit further includes a first power line, a second power line, a first clock signal line, a second clock signal line, an initial signal line; the plurality of shift registers are connected in cascade;

the first power supply end of each shift register is connected with the first power supply line, the second power supply end of each shift register is connected with the second power supply line, the first clock signal end of the odd-numbered shift register is connected with the first clock signal line, the second clock signal end of the odd-numbered shift register is connected with the second clock signal line, the first clock signal end of the even-numbered shift register is connected with the second clock signal line, the second clock signal end of the even-numbered shift register is connected with the first clock signal line, the signal input end of the first-numbered shift register is connected with the initial signal line, and the signal output end of the ith-numbered shift register is connected with the signal input end of the (i + 1) -th shift register.

In a third aspect, the present disclosure further provides a display device including the gate driving circuit according to any of the above embodiments.

In a fourth aspect, the present disclosure further provides a driving method of a shift register, configured to drive the shift register according to any one of the above embodiments; the shift register comprises an input sub-circuit, an inverting sub-circuit and an output sub-circuit, and the method comprises the following steps:

the input sub-circuit provides a signal of the signal input terminal to the first node under the control of the first clock signal terminal;

the inverting sub-circuit controls the potential of the second node under the control of a signal input end, a first clock signal end, a second clock signal end, a first node, a first power supply end and a second power supply end;

the output sub-circuit supplies the signal of the first power supply terminal or the second power supply terminal to the signal output terminal under the control of the first node and the second node.

The embodiment of the disclosure provides a shift register and a driving method thereof, a gate driving circuit and a display device, wherein an input sub-circuit provides a signal of a signal input end to a first node under the control of a first clock signal end, an inverting sub-circuit controls the potential of a second node under the control of the signal input end, the first clock signal end, a second clock signal end, the first node, a first power end and a second power end, and an output sub-circuit provides a signal of the first power end or the second power end to a signal output end under the control of the first node and the second node, so that the pulse width of an output signal of a signal output end of the shift register is controlled through control of signal input, and the pulse width of a gate driving signal is controlled.

Additional features and advantages of the disclosed embodiments will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the disclosed embodiments. Other advantages of the embodiments of the present disclosure may be realized and attained by the instrumentalities and methods described in the specification and the drawings.

Drawings

The accompanying drawings are included to provide an understanding of the technical solutions of the embodiments of the present disclosure, and are incorporated in and constitute a part of this specification, and together with the embodiments of the present disclosure, serve to explain the technical solutions of the embodiments of the present disclosure and not to limit the technical solutions of the present disclosure.

FIG. 1 is a schematic view of a display device;

FIG. 2 is a schematic plan view of a display substrate;

FIG. 3 is a schematic cross-sectional view of a display substrate;

FIG. 4 is a schematic diagram of an equivalent circuit of a pixel driving circuit;

FIG. 5 is a timing diagram of a pixel driving circuit;

fig. 6 is a schematic structural diagram of a shift register provided in the embodiment of the present disclosure;

fig. 7 is an equivalent circuit diagram of a shift register provided in an exemplary embodiment of the present disclosure;

FIG. 8 is a timing diagram illustrating operation of a shift register according to an exemplary embodiment of the present disclosure;

fig. 9 is an equivalent circuit diagram of a shift register according to another exemplary embodiment of the present disclosure;

fig. 10 is a schematic structural diagram of a shift register according to another exemplary embodiment of the present disclosure;

fig. 11 is an equivalent circuit diagram of a shift register according to another exemplary embodiment of the present disclosure;

fig. 12 is an equivalent circuit diagram of a shift register according to another exemplary embodiment of the present disclosure;

fig. 13 is a schematic structural diagram of a gate driving circuit according to an embodiment of the disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, in the present disclosure, the embodiments and features of the embodiments may be arbitrarily combined with each other without conflict.

Unless otherwise defined, technical or scientific terms used in the disclosure of the embodiments of the present disclosure should have the ordinary meaning as understood by those having ordinary skill in the art to which the present invention belongs. The use of "first," "second," and similar terms in the embodiments of the disclosure is not intended to indicate any order, quantity, or importance, but rather to distinguish one element from another. The word "comprising" or "comprises", and the like, means that a particular element or item appears in front of the word or is detected by mistake, and that the word or item appears after the word or item and its equivalents, but does not exclude other elements or misdetections.

In this specification, for convenience, terms indicating orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to explain positional relationship of constituent elements with reference to the drawings, only for convenience of description and simplification of description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention. The positional relationship of the components is changed as appropriate in accordance with the direction in which each component is described. Therefore, the words described in the specification are not limited to the words described in the specification, and may be replaced as appropriate.

In this specification, the terms "mounted," "connected," and "connected" are to be construed broadly unless otherwise specifically indicated and limited. For example, the connection can be fixed, detachable or integrated; can be mechanically or electrically connected; either directly or indirectly through intervening components, or may be interconnected between two elements. To those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood in conjunction with specific situations.

In the present disclosure, a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (or a drain electrode terminal, a drain connection region, or a drain electrode) and a source electrode (or a source electrode terminal, a source connection region, or a source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, the channel region refers to a region through which current mainly flows.

In the present disclosure, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors of opposite polarities or in the case where the direction of current flow during circuit operation changes, the functions of the "source electrode" and the "drain electrode" may be interchanged. Therefore, in the present disclosure, "source electrode" and "drain electrode" may be interchanged with each other. The gate electrode may also be referred to as a control electrode.

In the present disclosure, "electrically connected" includes a case where constituent elements are connected together by an element having some kind of electrical action. The "element having a certain electric function" is not particularly limited as long as it can transmit and receive an electric signal between connected components. The "element having some kind of electric function" may be, for example, an electrode, a wiring, a switching element such as a transistor, or another functional element such as a resistor, an inductor, or a capacitor.

In the present disclosure, "parallel" means a state in which an angle formed by two straight lines is-10 ° or more and 10 ° or less, and therefore, includes a state in which the angle is-5 ° or more and 5 ° or less. The term "perpendicular" refers to a state in which the angle formed by two straight lines is 80 ° or more and 100 ° or less, and therefore includes a state in which the angle is 85 ° or more and 95 ° or less.

"about" in this disclosure means that the limits are not strictly defined, and that the numerical values are within the tolerances allowed for the process and measurement.

Fig. 1 is a schematic structural diagram of a display device, in which a display substrate may include a timing controller, a data signal driver, a scan signal driver, a light emitting signal driver, and a pixel array, the timing controller is connected to the data signal driver, the scan signal driver, and the light emitting signal driver, respectively, the data signal driver is connected to a plurality of data signal lines (D1 to Dn), the scan signal driver is connected to a plurality of scan signal lines (S1 to Sm), respectively, and the light emitting signal driver is connected to a plurality of light emitting signal lines (E1 to Eo), respectively. The pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one of the sub-pixels Pxij may include a circuit unit and a light emitting device connected to the circuit unit, and the circuit unit may include at least one scan signal line, at least one data signal line, at least one light emitting signal line, and a pixel driving circuit. In an exemplary embodiment, the timing controller may supply a gray value and a control signal suitable for the specification of the data signal driver to the data signal driver, may supply a clock signal, a scan start signal, and the like suitable for the specification of the scan signal driver to the scan signal driver, and may supply a clock signal, an emission stop signal, and the like suitable for the specification of the light emission signal driver to the light emission signal driver. The data signal driver may generate data voltages to be supplied to the data signal lines D1, D2, D3, … …, and Dn using a gray value and a control signal received from the timing controller. For example, the data signal driver may sample a gray value using a clock signal and apply a data voltage corresponding to the gray value to the data signal lines D1 to Dn in units of pixel rows, n may be a natural number. The scan signal driver may generate scan signals to be supplied to the scan signal lines S1, S2, S3, … …, and Sm by receiving a clock signal, a scan start signal, and the like from the timing controller. For example, the scan signal driver may sequentially supply scan signals having on-level pulses to the scan signal lines S1 to Sm. For example, the scan signal driver may be constructed in the form of a shift register, and may generate the scan signals in such a manner that scan start signals provided in the form of on-level pulses are sequentially transmitted to the next stage circuit under the control of a clock signal, and m may be a natural number. The light emitting signal driver may generate emission signals to be supplied to the light emitting signal lines E1, E2, E3, … …, and Eo by receiving a clock signal, an emission stop signal, and the like from the timing controller. For example, the light emitting signal driver may sequentially supply the emission signals having off-level pulses to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be configured in the form of a shift register, and the emission signal may be generated in such a manner that the emission stop signal provided in the form of an off-level pulse is sequentially transmitted to the next stage circuit under the control of a clock signal, and o may be a natural number.

Fig. 2 is a schematic plan view of a display substrate. As shown in fig. 2, the display substrate may include a plurality of pixel units P arranged in a matrix, at least one of the plurality of pixel units P includes a first sub-pixel P1 emitting light of a first color, a second sub-pixel P2 emitting light of a second color, and a third sub-pixel P3 emitting light of a third color, and each of the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 includes a pixel driving circuit and a light emitting device. The pixel driving circuits in the first, second and third sub-pixels P1, P2 and P3 are respectively connected to the scan signal line, the data signal line and the light emitting signal line, and the pixel driving circuits are configured to receive the data voltage transmitted from the data signal line and output corresponding currents to the light emitting devices under the control of the scan signal line and the light emitting signal line. The light emitting devices in the first, second and third sub-pixels P1, P2 and P3 are respectively connected to the pixel driving circuit of the sub-pixel in which they are located, and the light emitting devices are configured to emit light of corresponding luminance in response to a current output from the pixel driving circuit of the sub-pixel in which they are located.

In an exemplary embodiment, the pixel unit P may include therein a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel. In an exemplary embodiment, the shape of the sub-pixels in the pixel unit may be a rectangle, a diamond, a pentagon or a hexagon, and the three sub-pixels may be arranged in a horizontal parallel, a vertical parallel or a delta manner, which is not limited in this disclosure.

Fig. 3 is a schematic cross-sectional structure diagram of a display substrate, illustrating the structure of three sub-pixels of an OLED display substrate. As shown in fig. 3, the display substrate may include a driving circuit layer 102 disposed on a substrate 101, a light emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the substrate 101, and an encapsulation layer 104 disposed on a side of the light emitting structure layer 103 away from the substrate 101, in a plane perpendicular to the display substrate. In some possible implementations, the display substrate may include other film layers, such as spacer pillars, and the like, which are not limited herein.

In an exemplary embodiment, the substrate 101 may be a flexible substrate, or may be a rigid substrate. The driving circuit layer 102 of each sub-pixel may include a plurality of transistors and storage capacitors constituting a pixel driving circuit. The light emitting structure layer 103 may include an anode 301, a pixel defining layer 302, an organic light emitting layer 303, and a cathode 304, the anode 301 is connected to the drain electrode of the driving transistor 210 through a via hole, the organic light emitting layer 303 is connected to the anode 301, the cathode 304 is connected to the organic light emitting layer 303, and the organic light emitting layer 303 emits light of a corresponding color under the driving of the anode 301 and the cathode 304. The encapsulation layer 104 may include a first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403 that are stacked, the first encapsulation layer 401 and the third encapsulation layer 403 may be made of inorganic materials, the second encapsulation layer 402 may be made of organic materials, and the second encapsulation layer 402 is disposed between the first encapsulation layer 401 and the third encapsulation layer 403, which may ensure that external moisture cannot enter the light emitting structure layer 103.

In an exemplary embodiment, the organic light Emitting Layer 303 may include a Hole Injection Layer (HIL), a Hole Transport Layer (HTL), an Electron Blocking Layer (EBL), a light Emitting Layer (EML), a Hole Blocking Layer (HBL), an Electron Transport Layer (ETL), and an Electron Injection Layer (EIL) stacked one on another. In an exemplary embodiment, the hole injection layers of all the sub-pixels may be a common layer connected together, the electron injection layers of all the sub-pixels may be a common layer connected together, the hole transport layers of all the sub-pixels may be a common layer connected together, the electron transport layers of all the sub-pixels may be a common layer connected together, the hole blocking layers of all the sub-pixels may be a common layer connected together, the light emitting layers of adjacent sub-pixels may have a small amount of overlap, or may be isolated, and the electron blocking layers of adjacent sub-pixels may have a small amount of overlap, or may be isolated.

In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, or 7T1C structure. Fig. 4 is an equivalent circuit diagram of a pixel driving circuit. As shown in fig. 4, the pixel driving circuit may include 5 transistors (a first transistor T1 to a fifth transistor T5) and 1 storage capacitor C, and the pixel driving circuit may be connected to 8 signal lines (a data signal line D, a first scan signal line S1, a second scan signal line S2, a third scan signal line S3, a light emitting signal line E, an initial signal line VIN1, a reference voltage signal line VIN2, a first power supply line VDD, and a second power supply line VSS).

In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. The first node N1 is respectively connected to the second pole of the first transistor T1, the second pole of the third transistor T3, and the second end of the storage capacitor C, the second node N2 is respectively connected to the second pole of the second transistor T2, the control pole of the third transistor T3, the second pole of the fourth transistor T4, and the first end of the storage capacitor C, and the third node N3 is respectively connected to the first pole of the third transistor T3 and the second pole of the fifth transistor T5.

In an exemplary embodiment, a first terminal of the storage capacitor C is connected to the second node N2, and a second terminal of the storage capacitor C is connected to the first node N1.

A control electrode of the first transistor T1 is connected to the third scan signal line S3, a first electrode of the first transistor T1 is connected to the initialization signal line VIN1, and a second electrode of the first transistor T1 is connected to the first node N1. A control electrode of the second transistor T2 is connected to the second scan signal line S2, a first electrode of the second transistor T2 is connected to the reference voltage signal line VIN2, and a second electrode of the second transistor T2 is connected to the second node N2.

A control electrode of the third transistor T3 is connected to the second node N2, that is, a control electrode of the third transistor T3 is connected to the first end of the storage capacitor C, a first electrode of the third transistor T3 is connected to the third node N3, and a second electrode of the third transistor T3 is connected to the first node N1. The third transistor T3 may be referred to as a driving transistor, and the third transistor T3 determines the amount of driving current flowing between the first power supply line VDD and the second power supply line VSS according to a potential difference between a control electrode and a first electrode thereof.

A control electrode of the fourth transistor T4 is connected to the first scan signal line S1, a first electrode of the fourth transistor T4 is connected to the data signal line D, and a second electrode of the fourth transistor T4 is connected to the second node N2. The fourth transistor T4 may be referred to as a switching transistor, a scan transistor, or the like, and when an on-level scan signal is applied to the first scan signal line S1, the fourth transistor T4 causes the data voltage of the data signal line D to be input to the pixel driving circuit.

A control electrode of the fifth transistor T5 is connected to the light emitting signal line E, a first electrode of the fifth transistor T5 is connected to the first power source line VDD, and a second electrode of the fifth transistor T5 is connected to the third node N3. The fifth transistor T5 may be referred to as a light emitting transistor.

In an exemplary embodiment, the first to fifth transistors T1 to T5 may be P-type transistors, or may be N-type transistors. The same type of transistors are adopted in the pixel driving circuit, so that the process flow can be simplified, the process difficulty of the display panel is reduced, and the yield of products is improved. In some possible implementations, the first to fifth transistors T1 to T5 may include P-type transistors and N-type transistors.

In an exemplary embodiment, the first scan signal line S1, the second scan signal line S2, the light emitting signal line E, the initialization signal line VIN1, and the reference voltage signal line VIN2 extend in a horizontal direction, and the second power supply line VSS, the first power supply line VDD, and the data signal line D extend in a vertical direction.

In an exemplary embodiment, the light emitting device may be an organic electroluminescent diode (OLED) including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked.

Fig. 5 is a timing diagram of an operation of a pixel driving circuit. An exemplary embodiment will be described below by an operation process of the pixel driving circuit illustrated in fig. 4, the pixel driving circuit in fig. 4 includes 5 transistors (the first transistor T1 to the fifth transistor T5), 1 storage capacitor C, and 8 signal lines (the data signal line D, the first scanning signal line S1, the second scanning signal line S2, the light emitting signal line E, the initial signal line VIN1, the reference voltage signal line VIN2, the first power supply line VDD, and the second power supply line VSS), and each of the 5 transistors is an N-type transistor.

In an exemplary embodiment, the operation of the pixel driving circuit may include:

in the first stage a1, the signal of the first scanning signal line S1 is a low level signal, and the signals of the second scanning signal line S2, the third scanning signal line S3 and the light emitting signal line E are high level signals. The first scanning signal line S1 is a low-level signal, and turns off the fourth transistor T4. The signal of the second scan signal line S2 is a high level signal, which turns on the second transistor T2, the signal of the reference voltage signal line VIN2 is provided to the second node N2, and the compensation voltage Vref is written at the second node N2, which turns on the third transistor T3. The signal of the third scan signal line S3 is a high level signal, turning on the first transistor T1, and the signal of the initialization signal line VIN1 is provided to the first node N1, resetting the first node N1. The signal on the light-emitting signal line E is a high level signal, which turns on the fifth transistor T5, and the signal on the first power line VDD charges the first node N1 through the third node N3 and the third transistor T3, and the voltage on the first node N1 does not reach the voltage for driving the OLED to emit light at this stage, so the OLED does not emit light at this stage.

The signals of the second stage a2, the first scanning signal line S1, and the third scanning signal line S3 are all low level signals. Since the signals of the first scanning signal line S1 and the third scanning signal line S3 are low level signals, the fourth transistor T4 and the first transistor T1 are both turned off. The second stage a2 may include the following three sub-stages according to the signals of the second scan signal line S2 and the light emitting signal line E:

first sub-phase a 21: the signals of the second scanning signal line S2 and the light emitting signal line E are both high level signals. Since the second scan signal line S2 is a high signal, the second transistor T2 is turned on, the compensation voltage Vref of the reference voltage signal line VIN2 is provided to the second node N2, and the third transistor T3 is turned on; since the signal on the light-emitting signal line E is a high-level signal, the fifth transistor T5 is turned on, and the signal on the first power line VDD charges the first node N1 through the third node N3 and the third transistor T3, the voltage on the first node N1 does not reach the voltage for driving the OLED to emit light at this stage, so the OLED does not emit light at this stage.

Second sub-phase a 22: the signal of the second scanning signal line S2 is a low-level signal, and the signal of the light-emitting signal line E is a high-level signal. Since the second scan signal line S2 is a low-level signal, the second transistor T2 is turned off, and since the voltages at the two ends of the storage capacitor C do not change abruptly, the second node N2 maintains the voltage of the previous frame, and the third transistor T3 is turned on; since the signal of the light-emitting signal line E is a high-level signal, the fifth transistor T5 is turned on, and the signal of the first power line VDD charges the first node N1 through the third node N3 and the third transistor T3, so that the voltage of the first node N1 reaches Vref-Vth (Vth is the threshold voltage of the third transistor T3), and the voltage of the first node N1 does not reach the voltage for driving the OLED to emit light at this stage, so the OLED does not emit light at this stage.

Third sub-phase a 23: the second scanning signal line S2 and the light emitting signal line E are both low level signals. Since the second scan signal line S2 and the light emitting signal line E are both low level signals and both the second transistor T2 and the fifth transistor T5 are turned off, the first node N1 maintains the voltage (Vref-Vth) of the previous frame since the voltage across the storage capacitor C does not abruptly change.

Third stage a 3: the signal of the first scanning signal line S1 is a high-level signal, and the signals of the second scanning signal line S2, the third scanning signal line S3, and the light-emitting signal line E are all low-level signals. Since the signal of the first scan signal line S1 is a high level signal, the fourth transistor T4 is turned on, and the data voltage output by the data signal line D is written into the second node N2; since the signals of the second scan signal line S2, the third scan signal line S3, and the light emitting signal line E are all low level signals, the second transistor T2, the first transistor T1, and the fifth transistor T5 are all turned off, and the first node N1 maintains the voltage (Vref-Vth) of the previous frame.

The scan signal driver may also be referred to as a gate driving device or a gate driver, and the gate driving device includes a separate gate driving integrated circuit or a panel gate driving circuit, which is not favorable for a narrow frame and low cost. For example, when the gate driving signal can be used as a scanning signal and a light-emitting control signal, the Pulse widths of the scanning signal and the light-emitting control signal are related to the working performance of the pixel driving circuit inside the display panel, and therefore a control circuit having a Pulse Width Modulation (PWM) function is required to adjust the Pulse Width of the gate driving signal.

In order to realize adjustment of the pulse width of the gate driving signal, the embodiment of the present disclosure provides a shift register, which may include an input sub-circuit, an inverting sub-circuit, and an output sub-circuit;

the input sub-circuit is respectively connected with the signal input end, the first clock signal end and the first node and is arranged to provide a signal of the signal input end for the first node under the control of the first clock signal end;

the phase-inverting sub-circuit is respectively connected with the signal input end, the first power end, the second power end, the first clock signal end, the second clock signal end, the first node and the second node and is arranged to control the potential of the second node under the control of the signal input end, the first clock signal end, the second clock signal end, the first node, the first power end and the second power end;

and the output sub-circuit is respectively connected with the first power supply end, the second power supply end, the first node, the second node and the signal output end and is arranged to provide the signal of the first power supply end or the second power supply end for the signal output end under the control of the first node and the second node.

According to the shift register, the input sub-circuit provides a signal of the signal input end to the first node under the control of the first clock signal end, the inverting sub-circuit controls the potential of the second node under the control of the signal input end, the first clock signal end, the second clock signal end, the first node, the first power end and the second power end, the output sub-circuit provides a signal of the first power end or the second power end to the signal output end under the control of the first node and the second node, and the pulse width of an output signal of the signal output end of the shift register is controlled through control signal input, so that the pulse width of a grid driving signal is controlled.

As shown in fig. 6, which is a schematic diagram of an exemplary shift register, the shift register may include: comprises an input sub-circuit 11, an inverting sub-circuit 12 and an output sub-circuit 13;

an input sub-circuit 11, respectively connected to the signal input terminal IN, the first clock signal terminal CKA, and the first node Q, and configured to provide the signal of the signal input terminal IN to the first node Q under the control of the first clock signal terminal CKA;

the inverting sub-circuit 12 is respectively connected to the signal input terminal IN, the first power supply terminal VGH, the second power supply terminal VGL, the first clock signal terminal CKA, the second clock signal terminal CKB, the first node Q, and the second node QB, and configured to control a potential of the second node QB under the control of the signal input terminal IN, the first clock signal terminal CKA, the second clock signal terminal CKB, the first node Q, the first power supply terminal VGH, and the second power supply terminal VGL;

the output sub-circuit 13 is connected to the first power source terminal VGH, the second power source terminal VGL, the first node Q, the second node QB, and the signal output terminal OUT, and configured to provide the signal of the first power source terminal VGH or the second power source terminal VGL to the signal output terminal OUT under the control of the first node Q and the second node QB.

In an exemplary embodiment, as shown in fig. 7, the input sub-circuit 11 may include a first transistor T1;

a control electrode of the first transistor T1 is connected to the first clock signal terminal CKA, a first electrode of the first transistor T1 is connected to the signal input terminal IN, and a second electrode of the first transistor T1 is connected to the first node Q.

In an exemplary embodiment, the inverting sub-circuit 12 may include a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a third capacitor C3;

a control electrode of the second transistor T2 is connected to the second clock signal terminal CKB, a first electrode of the second transistor T2 is connected to the first power source terminal VGH, and a second electrode of the second transistor T2 is connected to the third node P;

a control electrode of the third transistor T3 is connected to the signal input terminal IN, a first electrode of the third transistor T3 is connected to the second clock signal terminal CKB, and a second electrode of the third transistor T3 is connected to the third node P;

a control electrode of the fourth transistor T4 is connected to the third node P, a first electrode of the fourth transistor T4 is connected to the first clock signal terminal CKA, and a second electrode of the fourth transistor T4 is connected to the fourth node N;

a control electrode of the fifth transistor T5 is connected to the first clock signal terminal CKA, a first electrode of the fifth transistor T5 is connected to the fourth node N, and a second electrode of the fifth transistor T5 is connected to the second node QB;

a control electrode of the sixth transistor T6 is connected to the first node Q, a first electrode of the sixth transistor T6 is connected to the second power source terminal VGL, and a second electrode of the sixth transistor T6 is connected to the second node QB;

the first plate of the third capacitor C3 is connected to the third node P, and the second plate of the third capacitor C3 is connected to the fourth node N.

Signals input by a first clock signal terminal CKA and a second clock signal terminal CKB in the shift register can not directly charge and discharge a capacitor, so that the load of clock signals in the shift register is reduced, the shift register can work efficiently and stably, and the reliability of pulse width adjustment is improved; the inverting sub-circuit does not need to be switched on by means of capacitive coupling to the transistors in the shift register, so that the requirement on the capacity of the capacitor is relatively low, excessive space cannot be occupied due to the fact that the capacity of the capacitor is too large, and narrow frames and large size are facilitated to achieve. Therefore, the shift register provided by the disclosure can improve the reliability of pulse width modulation and is beneficial to realizing the narrow frame and large size of the display panel on the basis of realizing the output of the pulse signal width by the control signal output end.

In an exemplary embodiment, the output sub-circuit 13 may include a seventh transistor T7, an eighth transistor T8, a first capacitor C1, and a second capacitor C2;

a control electrode of the seventh transistor T7 is connected to the first node Q, a first electrode of the seventh transistor T7 is connected to the first power source terminal VGH, and a second electrode of the seventh transistor T7 is connected to the signal output terminal OUT;

a control electrode of the eighth transistor T8 is connected to the second node QB, a first electrode of the eighth transistor T8 is connected to the second power source terminal VGL, and a second electrode of the eighth transistor T8 is connected to the signal output terminal OUT;

a first plate of the first capacitor C1 is connected with the first node Q, and a second plate of the first capacitor C1 is connected with the signal output end OUT;

a first plate of the second capacitor C2 is connected to the second node QB, and a second plate of the second capacitor C2 is connected to the second power source terminal VGL.

In an exemplary embodiment, as shown in fig. 9, the output sub-circuit 13 may further include a ninth transistor T9; a first electrode of the eighth transistor T8 is connected to the second power source terminal VGL through the ninth transistor T9;

a control electrode of the ninth transistor T9 is connected to the second node QB, a first electrode of the ninth transistor T9 is connected to the second power source terminal VGL, and a second electrode of the ninth transistor T9 is connected to the first electrode of the eighth transistor T8.

In an exemplary embodiment, as shown in fig. 11 and 12, the output sub-circuit 13 may further include an eleventh transistor T11;

a control electrode of the eleventh transistor T11 is connected to the signal output terminal OUT, a first electrode of the eleventh transistor T11 is connected to the first power source terminal VGH, and a second electrode of the eleventh transistor T11 is connected to the fifth node M; a first pole of the eighth transistor T8 and a second pole of the ninth transistor T9 are both connected to the fifth node M.

In the present disclosure, the output sub-circuit 13 is provided with the eleventh transistor T11 to prevent the eighth transistor T8 from generating power consumption due to leakage current when the signal output terminal OUT outputs a high level signal for a long time. Meanwhile, the output of the signal output end OUT can be prevented from being influenced by leakage current, and the output stability is improved to a certain extent.

In an exemplary embodiment, as shown in fig. 10 and 12, the output sub-circuit 13 may further include a tenth transistor T10; a control electrode of the seventh transistor T7 is connected to the first node Q through the tenth transistor T10;

a control electrode of the tenth transistor T10 is connected to the first power source terminal VGH, a first electrode of the tenth transistor T10 is connected to the first node Q, and a second electrode of the tenth transistor T10 is connected to the control electrode of the seventh transistor T7.

In the present disclosure, the tenth transistor T10 may prevent the leakage of the first node Q from affecting the output of the first node Q, thereby avoiding the output abnormality of the signal output terminal OUT and improving the stability of the signal output.

In an exemplary embodiment, as shown in fig. 7, the input sub-circuit 11 may include a first transistor T1; the inverting sub-circuit 12 may include a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a third capacitor C3; the output sub-circuit 13 may include a seventh transistor T7, an eighth transistor T8, a first capacitor C1, and a second capacitor C2;

a control electrode of the first transistor T1 is connected to the first clock signal terminal CKA, a first electrode of the first transistor T1 is connected to the signal input terminal IN, and a second electrode of the first transistor T1 is connected to the first node Q;

a first plate of the third capacitor C3 is connected with the third node P, and a second plate of the third capacitor C3 is connected with the fourth node N;

In the present disclosure, fig. 11 is a ninth transistor T9 and an eleventh transistor T11 that are added on the basis of fig. 7, and in some exemplary embodiments, a tenth transistor T10 and an eleventh transistor T11 that are added on the basis of the circuit schematic diagram shown in fig. 9 may also be added, as shown in fig. 12.

In the present disclosure, the first to eleventh transistors T1 to T11 may also be all P-type transistors, or may include both P-type and N-type transistors, or all N-type transistors.

The embodiment of the present disclosure further provides a driving method of a shift register, configured to drive the shift register according to any one of the embodiments; the shift register includes an input sub-circuit, an inverting sub-circuit, and an output sub-circuit, and the driving method may include:

the input sub-circuit provides the signal of the signal input terminal to the first node under the control of the first clock signal terminal;

the inverting sub-circuit controls the potential of the second node under the control of the signal input end, the first clock signal end, the second clock signal end, the first node, the first power supply end and the second power supply end;

Fig. 8 is a timing diagram illustrating an operation of the shift register shown in fig. 7. As shown in fig. 7, an exemplary embodiment relates to a shift register including: 8 switching transistors (T1 to T8), 3 capacitor units (C1, C2, and C3), 3 signal input terminals (ECB, ECK, and IN), 1 signal output terminal (OUT), and 2 power supply terminals (VGH and VGL).

The first to eighth transistors T1 to T8 in the shift register shown in fig. 7 may be N-type transistors or P-type transistors, or a part of the transistors may be N-type transistors and another part of the transistors may be P-type transistors. Taking the first transistor T1 to the eighth transistor T8 in the shift register provided in an exemplary embodiment as an example, the operation process of the shift register provided in an exemplary embodiment is described below, and as shown in fig. 8, may include five stages, i.e., a first stage P1 to a fifth stage P5.

IN the first phase P1, the signal input from the signal input terminal IN is a high level signal, which turns on the third transistor T3, and the first phase P1 may include the following four sub-phases according to the signals input from the first clock signal terminal CKA and the second clock signal terminal CKB:

first sub-phase P11: the signal input from the first clock signal terminal CKA is a low level signal, and the signal input from the second clock signal terminal CKB is a high level signal. Since the signal input from the first clock signal terminal CKA is a low level signal, the first transistor T1 and the fifth transistor T5 are both turned off, the high level signal input from the signal input terminal IN cannot be transmitted to the first node Q through the first transistor T1, the first node Q maintains a high level of a previous frame, the sixth transistor T6 and the seventh transistor T7 are both turned on, since the sixth transistor T6 is turned on, the low level signal of the second power source terminal VGL is transmitted to the second node QB through the sixth transistor T6, the second node QB is a low level, the eighth transistor T8 is turned off, the low level signal of the second power source terminal VGL cannot be written into the signal output terminal OUT through the eighth transistor T8, since the seventh transistor T7 is turned on, the high level signal of the first power source terminal VGH is written into the signal output terminal OUT through the seventh transistor T7, and the signal output terminal OUT outputs a high level signal; since the signal inputted from the second clock signal terminal CKB is a high level signal, the second transistor T2 is turned on, the high level signal of the first power terminal VGH is transmitted to the third node P through the second transistor T2, and since the third transistor T3 is turned on, the high level signal inputted from the second clock signal terminal CKB is written into the third node P through the third transistor T3, the voltage of the third node P is high, the fourth transistor T4 is turned on, the low level signal inputted from the first clock signal terminal CKA is written into the fourth node N through the fourth transistor T4, the fourth node N is low, and since the fifth transistor T5 is turned off, the low level of the fourth node N cannot be transmitted to the second node QB through the fifth transistor T5. The signal output terminal OUT outputs a high level signal in the first sub-phase P11.

Second sub-phase P12: the signals input by the first clock signal terminal CKA and the second clock signal terminal CKB are both low level signals. Since the signal inputted from the first clock signal terminal CKA is a low level signal, the first transistor T1 and the second transistor T5 are both turned off, the high level signal inputted from the signal input terminal IN cannot be transmitted to the first node Q through the first transistor T1, the first node Q maintains the high level of the previous frame, the sixth transistor T6 and the seventh transistor T7 are both turned on, the high level signal of the first power terminal VGH is transmitted to the signal output terminal OUT through the seventh transistor T7, that is, the signal output terminal OUT outputs a high level signal, the low level signal of the second power terminal VGL is transmitted to the second node QB through the sixth transistor T6, the second node QB is a low level, the eighth transistor T8 is turned off, and the low level signal of the second power terminal VGL cannot be written into the signal output terminal OUT through the eighth transistor T8; since the signal inputted from the second clock signal terminal CKB is a low level signal, the second transistor T2 is turned off, the high level signal of the first power terminal VGH cannot be transmitted to the third node P through the second transistor T2, and since the third transistor T3 is turned on, the low level signal of the second clock signal terminal CKB is transmitted to the third node P through the third transistor T3, the third node P is a low level, the fourth transistor T4 is turned off, the low level signal inputted from the first clock signal terminal CKA cannot be written into the fourth node N through the fourth transistor T4, and since the voltages at both ends of the third capacitor C3 do not change abruptly, the fourth node N maintains the low level of the previous frame. The signal output terminal OUT outputs a high level signal in the second sub-phase P12.

Third sub-phase P13: the signal input from the first clock signal terminal CKA is a high level signal, and the signal input from the second clock signal terminal CKB is a low level signal. Since the signal input from the first clock signal terminal CKA is a high level signal, the first transistor T1 and the fifth transistor T5 are both turned on, the high level signal input from the signal input terminal IN is transmitted to the first node Q via the first transistor T1, the first node Q is a high level, the sixth transistor T6 and the seventh transistor T7 are both turned on, the high level signal of the first power terminal VGH is transmitted to the signal output terminal OUT via the seventh transistor T7, that is, the signal output terminal OUT outputs a high level signal, the low level signal of the second power terminal VGL is written into the second node QB via the sixth transistor T6, the second node QB is a low level, the eighth transistor T8 is turned off, and the low level signal of the second power terminal VGL cannot be written into the signal output terminal OUT via the eighth transistor T8; since the signal inputted from the second clock signal terminal CKB is a low level signal, the second transistor T2 is turned off, the high level signal of the first power terminal VGH cannot be transmitted to the third node P through the second transistor T2, and since the third transistor T3 is turned on, the low level signal of the second clock signal terminal CKB is transmitted to the third node P through the third transistor T3, the third node P is a low level, the fourth transistor T4 is turned off, the high level signal inputted from the first clock signal terminal CKA cannot be written into the fourth node N through the fourth transistor T4, and the fourth node N maintains a low level of a previous frame. The signal output terminal OUT outputs a high level signal in the third sub-phase P13.

Fourth sub-phase P14: the signals input by the first clock signal terminal CKA and the second clock signal terminal CKB are both low level signals. Since the signal input by the first clock signal terminal CKA is a low-level signal, the first transistor T1 and the fifth transistor T5 are both turned off, the high-level signal input by the signal input terminal IN cannot be transmitted to the first node Q through the first transistor T1, since the voltage across the first capacitor C1 does not generate a sudden change, the first node Q maintains the high level of the previous frame, the sixth transistor T6 and the seventh transistor T7 are both turned on, the high-level signal of the first power terminal VGH is transmitted to the signal output terminal OUT through the seventh transistor T7, that is, the signal output terminal OUT outputs a high-level signal, the low-level signal of the second power terminal VGL is written into the second node QB through the sixth transistor T6, the second node QB is a low level, the eighth transistor T8 is turned off, and the low-level signal of the second power terminal VGL cannot be written into the signal output terminal OUT through the eighth transistor T8; since the signal inputted from the second clock signal terminal CKB is a low level signal, the second transistor T2 is turned off, the high level signal of the first power terminal VGH cannot be transmitted to the third node P through the second transistor T2, since the third transistor T3 is turned on, the low level signal of the second clock signal terminal CKB is transmitted to the third node P through the third transistor T3, the third node P is a low level, the fourth transistor T4 is turned off, the low level signal of the first clock signal terminal CKA cannot be written into the fourth node N through the fourth transistor T4, and since the voltage at both ends of the third capacitor C3 does not generate a sudden change, the fourth node N maintains a previous frame low level. Therefore, the signal output terminal OUT outputs a high level signal in the fourth sub-stage P14.

In the first stage, the voltage signal of the third node P is completely changed according to the signal inputted from the second clock signal terminal CKB, i.e. the second clock signal terminal CKB controls the voltage signal of the third node P.

IN the second phase P2, the signals inputted from the signal input terminal IN and the first clock signal terminal CKA are both low level signals. Since the signal inputted from the first clock signal terminal CKA is at a low level, the first transistor T1 and the fifth transistor T5 are both turned off, and the low level signal inputted from the signal input terminal IN cannot be written into the first node Q through the first transistor T1; since the signal input terminal IN inputs a low level signal to turn off the third transistor T3, the signal inputted from the second clock signal terminal CKB cannot be written into the third node P through the third transistor T3; the second phase P2 may include the following two sub-phases according to the signal inputted from the second clock signal terminal CKB:

first sub-phase P21: the signal inputted from the second clock signal terminal CKB is a high level signal. Since the signal inputted from the second clock signal terminal CKB is a high level signal, the second transistor T2 is turned on, the high level signal inputted from the first power source terminal VGH is written into the third node P via the second transistor T2, the third node P is a high level, the fourth transistor T4 is turned on, the low level signal inputted from the first clock signal terminal CKA is written into the fourth node N via the fourth transistor T4, and the fourth node N is a low level; since the first transistor T1 is turned off, the low level signal inputted from the signal input terminal IN cannot be written into the first node Q through the first transistor T1, and since the voltage across the first capacitor C1 does not generate a sudden change, the first node Q maintains the high level of the previous frame, the sixth transistor T6 and the seventh transistor T7 are both turned on, the high level signal of the first power terminal VGH is transmitted to the signal output terminal OUT through the seventh transistor T7, that is, the signal output terminal OUT outputs the high level signal, the low level signal of the second power terminal VGL is written into the second node QB through the sixth transistor T6, the second node QB is low level, the eighth transistor T8 is turned off, and the low level signal of the second power terminal VGL cannot be written into the signal output terminal OUT through the eighth transistor T8. Therefore, the signal output terminal OUT outputs a high level signal in the first sub-phase P21.

Second sub-phase P22: the signal inputted from the second clock signal terminal CKB is a low level signal. Since the signal input from the second clock signal terminal CKB is a low level signal, the second transistor T2 is turned off, the high level signal input from the first power terminal VGH cannot be written into the third node P through the second transistor T2, and since the voltage across the third capacitor C3 does not generate a sudden change, the third node P maintains the high level of the previous frame, the fourth transistor T4 is turned on, the low level signal input from the first clock signal terminal CKA is written into the fourth node N through the fourth transistor T4, and the fourth node N is a low level; since the first transistor T1 is turned off, the low level signal inputted from the signal input terminal IN cannot be written into the first node Q through the first transistor T1, and since the voltage across the first capacitor C1 does not generate a sudden change, the first node Q maintains the high level of the previous frame, the sixth transistor T6 and the seventh transistor T7 are both turned on, the high level signal of the first power terminal VGH is transmitted to the signal output terminal OUT through the seventh transistor T7, that is, the signal output terminal OUT outputs the high level signal, the low level signal of the second power terminal VGL is written into the second node QB through the sixth transistor T6, the second node QB is low level, the eighth transistor T8 is turned off, and the low level signal of the second power terminal VGL cannot be written into the signal output terminal OUT through the eighth transistor T8. Therefore, the signal output terminal OUT outputs a high level signal in the second sub-phase P22.

The third stage P3, according to the signals inputted from the signal input terminal IN, the first clock signal terminal CKA and the second clock signal terminal CKB, the third stage P3 may include the following three sub-stages:

IN the first sub-stage P31, the signal inputted from the first clock signal terminal CKA is a high level signal, and the signal inputted from the signal input terminal IN and the signal inputted from the second clock signal terminal CKB are both low level signals. Since the signal inputted from the first clock signal terminal CKA is a high level signal, the first transistor T1 and the fifth transistor T5 are both turned on, the low level signal inputted from the signal input terminal IN is transmitted to the first node Q via the first transistor T1, the first node Q is a low level, the sixth transistor T6 and the seventh transistor T7 are both turned off, the low level signal of the second power terminal VGL cannot be written into the second node QB via the sixth transistor T6, and the high level signal of the first power terminal VGH cannot be transmitted to the signal output terminal OUT via the seventh transistor T7; since the signal inputted from the second clock signal terminal CKB is a low level signal, the second transistor T2 is turned off, the high level signal of the first power terminal VGH cannot be transmitted to the third node P through the second transistor T2, since the signal inputted from the signal input terminal IN is a low level signal, the third transistor T3 is turned off, the low level signal inputted from the second clock signal terminal CKB cannot be transmitted to the third node P through the third transistor T3, since the voltage across the third capacitor C3 does not generate a sudden change, the third node P maintains the high level of the previous frame, the fourth transistor T4 is turned on, the high level signal inputted from the first clock signal terminal CKA is written into the fourth node N through the fourth transistor T4, the fourth node N is a high level, since the fifth transistor T5 is turned on, the high level of the fourth node N is written into the second node QB through the fifth transistor T5, the second node QB is a high level, the eighth transistor T8 is turned on, a low-level signal of the second power source terminal VGL is transmitted to the signal output terminal OUT via the eighth transistor T8, and the signal output terminal OUT outputs the low-level signal.

IN the second sub-stage P32, the signals inputted from the first clock signal terminal CKA, the second clock signal terminal CKB and the signal input terminal IN are all low level signals. Since the signal inputted from the first clock signal terminal CKA is a low level signal, the first transistor T1 and the fifth transistor T5 are both turned off, the low level signal inputted from the signal input terminal IN cannot be transmitted to the first node Q through the first transistor T1, the first node Q maintains a low level signal of a previous frame, the sixth transistor T6 and the seventh transistor T7 are both turned off, the low level signal of the second power terminal VGL cannot be written into the second node QB through the sixth transistor T6, and the high level signal of the first power terminal VGH cannot be transmitted to the signal output terminal OUT through the seventh transistor T7; since the signal inputted from the second clock signal terminal CKB is a low level signal, the second transistor T2 is turned off, the high level signal of the first power terminal VGH cannot be transmitted to the third node P through the second transistor T2, since the signal inputted from the signal input terminal IN is a low level signal, the third transistor T3 is turned off, the low level signal inputted from the second clock signal terminal CKB cannot be transmitted to the third node P through the third transistor T3, since the voltage across the third capacitor C3 does not abruptly change, the third node P maintains the high level of the previous frame, the fourth transistor T4 is turned on, the low level signal inputted from the first clock signal terminal CKA is written into the fourth node N through the fourth transistor T4, the fourth node N is a low level, since the fifth transistor T5 is turned off, the low level of the fourth node N cannot be written into the second node QB through the fifth transistor T5, since the voltage across the second capacitor C2 does not abruptly change, the second node QB maintains the high level of the previous frame, the eighth transistor T8 is turned on, the low level signal of the second power source terminal VGL is transmitted to the signal output terminal OUT via the eighth transistor T8, and the signal output terminal OUT outputs the low level signal.

IN the third sub-stage P33, the signal inputted from the first clock signal terminal CKA is a low level signal, and the signals inputted from the second clock signal terminal CKB and the signal input terminal IN are both high level signals. Since the signal inputted from the first clock signal terminal CKA is a low level signal, the first transistor T1 and the fifth transistor T5 are both turned off, the high level signal inputted from the signal input terminal IN cannot be transmitted to the first node Q through the first transistor T1, the first node Q maintains the low level signal of the previous frame, the sixth transistor T6 and the seventh transistor T7 are both turned off, the low level signal of the second power terminal VGL cannot be written into the second node QB through the sixth transistor T6, and the high level signal of the first power terminal VGH cannot be transmitted to the signal output terminal OUT through the seventh transistor T7; since the signal inputted from the second clock signal terminal CKB is a high level signal, the second transistor T2 is turned on, the high level signal of the first power terminal VGH is transmitted to the third node P through the second transistor T2, since the signal inputted from the signal input terminal IN is a high level signal, the third transistor T3 is turned on, the high level signal inputted from the second clock signal terminal CKB is transmitted to the third node P through the third transistor T3, the third node P is a high level, the fourth transistor T4 is turned on, the low level signal inputted from the first clock signal terminal CKA is written to the fourth node N through the fourth transistor T4, the fourth node N is a low level, since the fifth transistor T5 is turned off, the low level of the fourth node N cannot be written to the second node QB through the fifth transistor T5, the second node QB maintains the high level of the previous frame, the eighth transistor T8 is turned on, and the low level signal of the second power terminal VGL is transmitted to the signal output terminal OUT through the eighth transistor T8, the signal output terminal OUT outputs a low level signal.

IN the fourth phase P4, the signal input from the signal input terminal IN is a high level signal, and the signals input from the first clock signal terminal CKA and the second clock signal terminal CKB are both low level signals. Since the signal inputted from the first clock signal terminal CKA is a low level signal, the first transistor T1 and the fifth transistor T5 are both turned off, the high level signal inputted from the signal input terminal IN cannot be written into the first node Q through the first transistor T1, the first node Q maintains the low level of the previous frame, the sixth transistor T6 and the seventh transistor T7 are both turned off, the low level signal of the second power terminal VGL cannot be written into the second node QB through the sixth transistor T6, and the high level signal of the first power terminal VGH cannot be transmitted to the signal output terminal OUT through the seventh transistor T7; since the signal inputted from the second clock signal terminal CKB is a low level signal, the second transistor T2 is turned off, the high level signal of the first power terminal VGH cannot be written into the third node P through the second transistor T2, since the signal inputted from the signal input terminal IN is a high level signal, the third transistor T3 is turned on, the low level signal inputted from the second clock signal terminal CKB is written into the third node P through the third transistor T3, the third node P is a low level signal, the fourth transistor T4 is turned off, the low level signal inputted from the first clock signal terminal CKA cannot be written into the fourth node N through the fourth transistor T4, since the voltage across the third capacitor C3 does not generate a sudden change, the fourth node N maintains the low level of the previous frame, since the fifth transistor T5 is turned off, the low level of the fourth node N cannot be written into the second node QB through the fifth transistor T5, the second node QB maintains the high level of the previous frame, the eighth transistor T8 is turned on, a low-level signal of the second power source terminal VGL is transmitted to the signal output terminal OUT via the eighth transistor T8, and the signal output terminal OUT outputs the low-level signal.

IN the fifth phase P5, the signal inputted from the signal input terminal IN is a high level signal. Since the signal inputted from the signal input terminal IN is a high level signal and the third transistor T3 is turned on, the fifth phase P5 can be divided into the following sub-phases according to the signals inputted from the first clock signal terminal CKA and the second clock signal terminal CKB:

first sub-phase P51: the signal input from the first clock signal terminal CKA is a high level signal, and the signal input from the second clock signal terminal CKB is a low level signal. Since the signal inputted from the first clock signal terminal CKA is a high level signal, the first transistor T1 and the second transistor T5 are both turned on, the high level signal inputted from the signal input terminal IN is transmitted to the first node Q via the first transistor T1, the voltage of the first node Q is a high level, the sixth transistor T6 and the seventh transistor T7 are both turned on, the high level signal of the first power terminal VGH is transmitted to the signal output terminal OUT via the seventh transistor T7, that is, the signal output terminal OUT outputs a high level signal, the low level signal of the second power terminal VGL is written into the second node QB via the sixth transistor T6, the second node QB is a low level, the eighth transistor T8 is turned off, and the low level signal of the second power terminal VGL cannot be transmitted to the signal output terminal OUT via the eighth transistor T8; since the signal inputted from the second clock signal terminal CKB is a low level signal, the second transistor T2 is turned off, the high level signal of the first power terminal VGH cannot be transmitted to the third node P through the second transistor T2, and since the third transistor T3 is turned on, the low level signal inputted from the second clock signal terminal CKB is written into the third node P through the third transistor T3, the third node P is a low level, the fourth transistor T4 is turned off, the high level signal inputted from the first clock signal terminal CKA cannot be written into the fourth node N through the fourth transistor T4, and since the voltage across the third capacitor C3 does not generate a sudden change, the fourth node N maintains the low level of the previous frame.

Second sub-phase P52: the signals input by the first clock signal terminal CKA and the second clock signal terminal CKB are both low level signals. Since the signal inputted from the first clock signal terminal CKA is a low level signal, the first transistor T1 and the fifth transistor T5 are both turned off, the high level signal inputted from the signal input terminal IN cannot be transmitted to the first node Q through the first transistor T1, the first node Q maintains the high level of the previous frame, the sixth transistor T6 and the seventh transistor T7 are both turned on, the high level signal of the first power terminal VGH is transmitted to the signal output terminal OUT through the seventh transistor T7, that is, the signal output terminal OUT outputs a high level signal, the low level signal of the second power terminal VGL is written into the second node QB through the sixth transistor T6, the second node is a low level, the eighth transistor T8 is turned off, and the low level signal of the second power terminal VGL cannot be transmitted to the signal output terminal OUT through the eighth transistor T8; since the signal inputted from the second clock signal terminal CKB is a low level signal and the second transistor T2 is turned off, the high level signal of the first power terminal VGH cannot be transmitted to the third node P through the second transistor T2, and since the third transistor T3 is turned on, the low level signal inputted from the second clock signal terminal CKB is written into the third node P through the third transistor T3, the third node P is a low level and the fourth transistor T4 is turned off, the high level signal inputted from the first clock signal terminal CKA cannot be written into the fourth node N through the fourth transistor T4, and the fourth node N maintains a low level of a previous frame.

Third sub-phase P53: the signal input from the first clock signal terminal CKA is a low level signal, and the signal input from the second clock signal terminal CKB is a high level signal. Since the signal inputted from the first clock signal terminal CKA is a low level signal, the first transistor T1 and the fifth transistor T5 are both turned off, the high level signal inputted from the signal input terminal IN cannot be transmitted to the first node Q through the first transistor T1, the first node Q maintains the high level of the previous frame, the sixth transistor T6 and the seventh transistor T7 are both turned on, the high level signal of the first power terminal VGH is transmitted to the signal output terminal OUT through the seventh transistor T7, that is, the signal output terminal OUT outputs a high level signal, the low level signal of the second power terminal VGL is written into the second node QB through the sixth transistor T6, the second node is a low level, the eighth transistor T8 is turned off, and the low level signal of the second power terminal VGL cannot be transmitted to the signal output terminal OUT through the eighth transistor T8; since the signal inputted from the second clock signal terminal CKB is a high level signal, the second transistor T2 is turned on, the high level signal of the first power terminal VGH is transmitted to the third node P through the second transistor T2, and since the third transistor T3 is turned on, the high level signal inputted from the second clock signal terminal CKB is written into the third node P through the third transistor T3, the third node P is a high level, the fourth transistor T4 is turned on, the low level signal inputted from the first clock signal terminal CKA is written into the fourth node N through the fourth transistor T4, and the fourth node N is a low level.

Fourth sub-phase P54: the signals input by the first clock signal terminal CKA and the second clock signal terminal CKB are both low level signals. Since the signal inputted from the first clock signal terminal CKA is a low level signal, the first transistor T1 and the fifth transistor T5 are both turned off, the high level signal inputted from the signal input terminal IN cannot be transmitted to the first node Q through the first transistor T1, the first node Q maintains the high level of the previous frame, the sixth transistor T6 and the seventh transistor T7 are both turned on, the high level signal of the first power terminal VGH is transmitted to the signal output terminal OUT through the seventh transistor T7, that is, the signal output terminal OUT outputs a high level signal, the low level signal of the second power terminal VGL is written into the second node QB through the sixth transistor T6, the second node is a low level, the eighth transistor T8 is turned off, and the low level signal of the second power terminal VGL cannot be transmitted to the signal output terminal OUT through the eighth transistor T8; since the signal inputted from the second clock signal terminal CKB is a low level signal, the second transistor T2 is turned off, the high level signal of the first power terminal VGH cannot be transmitted to the third node P through the second transistor T2, and since the third transistor T3 is turned on, the low level signal inputted from the second clock signal terminal CKB is written into the third node P through the third transistor T3, the third node P is a low level, the fourth transistor T4 is turned off, the low level signal inputted from the first clock signal terminal CKA cannot be written into the fourth node N through the fourth transistor T4, and the fourth node N maintains a low level of a previous frame.

The timing sequence of the fifth phase P5 from the first sub-phase P51 to the fourth sub-phase P54 is a sub-cycle, and the timing sequence can be the same as the timing sequence of the first sub-phase P51 to the fourth sub-phase P54, which is not repeated herein.

From the above-mentioned first to fifth stages P1 to P5 and fig. 8, it can be seen that the present disclosure can adjust the pulse width of the signal output terminal OUT by controlling the pulse width of the signal input terminal IN.

As shown in fig. 7 and 8, in the operation sequence from the first stage P1 to the fifth stage P5, the signals input from the first clock signal terminal CKA and the second clock signal terminal CKB do not directly charge or discharge the capacitor, and the two ends of the capacitor do not undergo the process of repeated charging and discharging, so that the load of the clock signal in the shift register is reduced, and the shift register can efficiently and stably operate. For example, the two ends of the third capacitor C3 are the third node P and the fourth node N, and it can be seen from the operation process of the first phase P1 to the fifth phase P5 that the voltages of the third node P and the fourth node N are not changed synchronously with the signals input by the first clock signal terminal CKA and the second clock signal terminal CKB, so that the capacitor is not frequently charged and discharged with the change of the signals of the clock signal terminals, thereby reducing the load of the clock signal of the shift register.

In the exemplary embodiment, the operation timing diagram of the shift register shown in fig. 9 is the same as the operation timing diagram shown in fig. 8, and is not described again here. In the shift register shown in fig. 9, the ninth transistor T9 may be an N-type transistor, and the operation process of the ninth transistor T9 is the same as that of the eighth transistor T8 under the control of the second node QB, which is not described herein again.

In the exemplary embodiment, in fig. 10 and 12, the control electrode of the tenth transistor T10 is connected to the first power source terminal VGH, and the tenth transistor T10 is in a turn-on state under the control of the first power source terminal VGH.

In the exemplary embodiment, in fig. 11 and 12, the eleventh transistor T11 is turned on or off under the control of the signal output terminal OUT. When the signal output terminal OUT outputs the high level signal, the eleventh transistor T11 is turned on, and the high level signal of the first power source terminal VGH is written into the fifth node M through the eleventh transistor T11, so that power consumption of the eighth transistor T8 due to leakage current can be prevented.

In the present disclosure, the operation timing diagram of the shift register shown in fig. 10-12 may be the same as the operation timing diagram shown in fig. 8, and is not described herein again.

The embodiment of the present disclosure further provides a gate driving circuit, which includes a plurality of shift registers according to any one of the above embodiments.

In an exemplary embodiment, as shown in fig. 13, the gate driving circuit may include a first power line VGH, a second power line VGL, a first clock signal line CKA, a second clock signal line CKB, an initial signal line STU; a plurality of shift registers are connected in cascade;

the first power supply terminal VGH of each shift register is connected with the first power supply line VGH, the second power supply terminal VGL of each shift register is connected with the second power supply line VGL, the first clock signal terminal CKA of the odd-numbered shift register is connected with the first clock signal line CKA, the second clock signal terminal CKB of the odd-numbered shift register is connected with the second clock signal line CKB, the first clock signal terminal CKA of the even-numbered shift register is connected with the second clock signal line CKB, the second clock signal terminal CKB of the even-numbered shift register is connected with the first clock signal line CKA, the signal input terminal of the first-numbered shift register is connected with the initial signal line STU, and the signal output terminal OUT of the i-numbered shift register is connected with the signal input terminal IN of the i + 1-numbered shift register.

In fig. 13, goa (i) is the i-th stage shift register, where i is a positive integer from 1 to m, and m is a positive integer greater than or equal to 2. Since the gate driving circuit provided by the above embodiment adopts the above shift register, the gate driving circuit can realize the function of adjusting the pulse width of the output signal. When the gate driving signal output by the gate driving circuit provided by the above embodiment is used as the scanning signal and the light-emitting control signal, the pulse widths of the scanning signal and the light-emitting control signal can be adjusted as required, so that the working performance of the internal pixel circuit is well ensured.

The embodiment of the disclosure further provides a display device, which includes the gate driving circuit described in any of the above embodiments.

In an exemplary embodiment, the display device may be any product or component having a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, and a navigator.

The shift register and the driving method thereof, the gate driving circuit and the display device provided by the embodiments of the present disclosure, the input sub-circuit provides a signal of the signal input terminal to the first node under the control of the first clock signal terminal, the inverting sub-circuit controls a potential of the second node under the control of the signal input terminal, the first clock signal terminal, the second clock signal terminal, the first node, the first power terminal and the second power terminal, the output sub-circuit provides a signal of the first power terminal or the second power terminal to the signal output terminal under the control of the first node and the second node, and the pulse width of the output signal of the signal output terminal of the shift register is controlled by controlling the signal input, so as to control the pulse width of the gate driving signal.

The drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to common designs.

Without conflict, features of embodiments of the present invention, that is, embodiments, may be combined with each other to arrive at new embodiments.

Although the embodiments of the present invention have been described above, the present invention is not limited to the embodiments described above. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A shift register is characterized by comprising an input sub-circuit, an inverting sub-circuit and an output sub-circuit;

2. The shift register according to claim 1, wherein the inverting sub-circuit includes a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a third capacitor;

3. The shift register according to claim 1, wherein the output sub-circuit includes a seventh transistor, an eighth transistor, a first capacitor, and a second capacitor;

4. The shift register of claim 3, wherein the output sub-circuit further comprises a ninth transistor; a first electrode of the eighth transistor is connected to the second power supply terminal through the ninth transistor;

5. The shift register of claim 4, wherein the output sub-circuit further comprises an eleventh transistor;

6. The shift register according to any one of claims 3 to 5, wherein the output sub-circuit further includes a tenth transistor; a control electrode of the seventh transistor is connected to the first node through the tenth transistor;

7. The shift register of claim 1, wherein the input sub-circuit comprises a first transistor;

8. The shift register of claim 1, wherein the input sub-circuit comprises a first transistor; the inverting sub-circuit comprises a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor and a third capacitor; the output sub-circuit comprises a seventh transistor, an eighth transistor, a first capacitor and a second capacitor;

9. A gate driver circuit comprising a plurality of shift registers according to any one of claims 1 to 8.

10. The gate driving circuit according to claim 9, further comprising a first power line, a second power line, a first clock signal line, a second clock signal line, an initial signal line; the plurality of shift registers are connected in cascade;

11. A display device comprising the gate driver circuit according to claim 10.

12. A method of driving a shift register, characterized by being arranged to drive a shift register according to any one of claims 1 to 8; the shift register comprises an input sub-circuit, an inverting sub-circuit and an output sub-circuit, and the method comprises the following steps: