CN114330176A - Chip verification method and device, electronic equipment and storage medium - Google Patents
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Abstract
The disclosure provides a chip verification method, a chip verification device, an electronic device and a storage medium, wherein the method comprises the following steps: determining a module to be verified in a chip and verification related data of the module to be verified, wherein the verification related data comprises: module configuration data, reference input data and corresponding reference output data; configuring the module to be verified according to the module configuration data; inputting the reference input data into a module to be verified to acquire actual output data of the module to be verified; according to the reference output data and the actual output data, the verification result of the module to be verified is determined, so that different modules to be verified in the chip can be verified in the same verification environment, the deployment of a plurality of verification environments is not needed, the verification cost is reduced, the verification time is saved, and the verification efficiency is improved.
Description
Technical Field
The present disclosure relates to the field of integrated circuit technologies, and in particular, to a chip verification method and apparatus, an electronic device, and a storage medium.
Background
As chip technology matures, module-level and system-level verification of chips becomes important. In the chip verification method in the related art, because the verification functions are different, a verification environment is required when module-level verification is performed; when the system level verification is carried out, a verification environment is needed, so that the cost is high during the chip verification, and the chip verification efficiency is poor.
Disclosure of Invention
The present disclosure is directed to solving, at least to some extent, one of the technical problems in the related art.
The disclosure provides a chip verification method to solve the problems of high chip verification cost and poor chip verification efficiency in the related art.
According to a first aspect of the present disclosure, there is provided a chip verification method, including: determining a module to be verified in a chip and verification related data of the module to be verified, wherein the verification related data comprises: module configuration data, reference input data and corresponding reference output data; configuring the module to be verified according to the module configuration data; inputting the reference input data into the module to be verified to acquire actual output data of the module to be verified; and determining a verification result of the module to be verified according to the reference output data and the actual output data.
As a first possible situation of the embodiment of the present disclosure, the determining a module to be verified in a chip and verification-related data of the module to be verified includes: determining the module to be verified in the chip; determining module configuration data and reference input data of the module to be verified; determining the reference output data according to the module configuration data and the reference input data.
As a second possible case of the embodiment of the present disclosure, the determining, according to the reference output data and the actual output data, a verification result of the module to be verified includes: comparing the reference output data with the actual output data to determine whether the reference output data is consistent with the actual output data; when the reference output data is consistent with the actual output data, determining that the verification result is that the verification is passed; and when the reference output data is inconsistent with the actual output data, determining that the verification result is verification failure.
As a third possible case of the embodiment of the present disclosure, the number of the modules to be verified is at least one; the module to be verified is a part of the module in the chip, or all the modules in the chip.
As a fourth possible case of the embodiment of the present disclosure, when the modules to be verified are all the modules in the chip, the reference input data is reference input data of the chip, and the reference output data is reference output data of the chip.
As a fifth possible case of the embodiment of the present disclosure, the module to be verified includes a security module; the number of the safety modules is at least one; all modules or part of modules in the chip are provided with corresponding safety modules; the security module is connected to each module in the chip via an AXI bus.
As a sixth possible case of the embodiment of the present disclosure, the security module is a security module corresponding to a designated area of a DDR memory in the chip; for each function of the security module, corresponding reference input data and reference output data are set.
According to a second aspect of the embodiments of the present disclosure, there is provided a chip verification apparatus including: the device comprises a first determination module and a second determination module, wherein the first determination module is used for determining a module to be verified in a chip and verification related data of the module to be verified, and the verification related data comprises: module configuration data, reference input data and corresponding reference output data; the configuration module is used for configuring the module to be verified according to the module configuration data; the acquisition module is used for inputting the reference input data into the module to be verified so as to acquire actual output data of the module to be verified; and the second determining module is used for determining the verification result of the module to be verified according to the reference output data and the actual output data.
As a first possible situation of the embodiment of the present disclosure, the first determining module is specifically configured to determine the module to be verified in a chip; determining module configuration data and reference input data of the module to be verified; determining the reference output data according to the module configuration data and the reference input data.
As a second possible situation of the embodiment of the present disclosure, the second determining module is specifically configured to compare the reference output data with the actual output data, and determine whether the reference output data is consistent with the actual output data; when the reference output data is consistent with the actual output data, determining that the verification result is that the verification is passed; and when the reference output data is inconsistent with the actual output data, determining that the verification result is verification failure.
As a third possible case of the embodiment of the present disclosure, the number of the modules to be verified is at least one; the module to be verified is a part of the module in the chip, or all the modules in the chip.
As a fourth possible case of the embodiment of the present disclosure, when the modules to be verified are all the modules in the chip, the reference input data is reference input data of the chip, and the reference output data is reference output data of the chip.
As a fifth possible case of the embodiment of the present disclosure, the module to be verified includes a security module; the number of the safety modules is at least one; all modules or part of modules in the chip are provided with corresponding safety modules; the security module is connected to each module in the chip via an AXI bus.
As a sixth possible case of the embodiment of the present disclosure, the security module is a security module corresponding to a designated area of a DDR memory in the chip; for each function of the security module, corresponding reference input data and reference output data are set.
According to a third aspect of the present disclosure, there is provided a chip verification platform comprising: the module configuration component, the reference model component and the comparison component are respectively connected with a module to be verified in the chip through buses; the module configuration component configures the module configuration data and the reference input data of the module to be verified through a bus; the reference model component determines reference output data based on module configuration data in the module to be verified and the reference data output; and the comparison module is used for determining a verification result based on the actual output data and the reference output data of the module to be verified.
According to a fourth aspect of the present disclosure, there is provided an electronic device comprising: a processor; a memory for storing the processor-executable instructions; the processor is configured to execute the instructions to implement the chip verification method provided in the embodiment of the first aspect of the disclosure.
According to a fifth aspect of the present disclosure, there is provided a computer-readable storage medium, wherein instructions, when executed by a processor of an electronic device, enable the electronic device to perform the chip verification method set forth in the disclosure above.
According to a sixth aspect of the present disclosure, there is provided a computer program product comprising a computer program which, when executed by a processor of an electronic device, enables the electronic device to perform the chip verification method set forth in the disclosure above.
Additional aspects and advantages of the present application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the present application.
Drawings
The foregoing and/or additional aspects and advantages of the present application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
FIG. 1 is a flow diagram illustrating a method for chip verification in accordance with an exemplary embodiment;
FIG. 2 is a schematic diagram of the connection of the security module to designated DDR regions and other modules;
FIG. 3 is a schematic diagram of a verification platform architecture of an embodiment of the present disclosure;
FIG. 4 is a schematic diagram of a chip verification apparatus according to an exemplary embodiment;
fig. 5 is a block diagram illustrating an electronic device of a chip verification method according to an example embodiment.
Detailed Description
Reference will now be made in detail to the embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the drawings are exemplary and intended to be illustrative of the present disclosure, and should not be construed as limiting the present disclosure.
As chip technology matures, module-level and system-level verification of chips becomes important. In the chip verification method in the related art, because the verification functions are different, a verification environment is required when module-level verification is performed; when the system level verification is carried out, a verification environment is needed, so that the cost is high during the chip verification, and the chip verification efficiency is poor.
In order to solve the above problems, the present disclosure provides a chip verification method, device, electronic device, and storage medium.
Fig. 1 is a schematic flow chart of a chip verification method according to an exemplary embodiment, and it should be noted that the chip verification method can be applied to a chip verification apparatus. The chip verification device may be, for example, a hardware device that can be connected to the chip through a bus or the like, or a controller in the hardware device, or control software in the hardware device, and may be set according to actual needs.
As shown in fig. 1, the chip verification method includes the following steps:
step 101, determining a module to be verified in a chip and verification related data of the module to be verified, wherein the verification related data comprises: module configuration data, reference input data and corresponding reference output data.
In the embodiment of the present disclosure, the process of the chip verification apparatus executing step 101 may be, for example, determining a module to be verified in the chip; determining module configuration data and reference input data of a module to be verified; and determining reference output data according to the module configuration data and the reference input data. The reference output data is a result that should be theoretically output by the module to be verified under the module configuration data and the reference input data.
In the disclosed embodiment, the number of modules to be verified may be at least one. For example, the module to be verified may be a part of the module in the chip, or all of the module in the chip. And when the modules to be verified are all the modules in the chip, the reference input data is the reference input data of the chip, and the reference output data is the reference output data of the chip. When the module to be verified is a partial module in the chip, the verification process shown in fig. 1 may be performed for each of the partial modules. Wherein, the chip can include the following modules: the bus module, the security module, the CPU module, the DDR memory module and the like can be set according to actual needs.
In the following, a module to be verified is taken as an example of a security module in a chip. The number of the security modules can be at least one, and all or part of the modules in the chip are provided with the corresponding security modules. That is, the other modules in the chip except the security module may respectively correspond to one security module. For example, the bus module corresponds to a security module, the CPU module corresponds to a security module, and the DDR memory module corresponds to a security module. The security module is used for protecting the transmission security of the corresponding module and the like.
It should be noted that the DDR memory module may correspond to a plurality of security modules. For example, the DDR memory module is divided into a plurality of regions, and each region corresponds to one security module; and the security module corresponding to each region is used for protecting the transmission security of the corresponding DDR region. The following description takes the security module as an example for protecting the transmission security of the designated DDR area in the DDR memory module.
In the embodiment of the present disclosure, different modules to be verified have different functions, and thus different module configuration data. The module configuration data is used for configuring logic of the module to be verified for realizing functions. In the application, the module configuration data of the verification module is acquired aiming at different modules to be verified, and the verification module is configured based on the module configuration data so as to be convenient for verification, so that the different modules to be verified in the chip can be verified by adopting the same verification environment, the deployment of a plurality of verification environments is avoided, the verification cost is reduced, the verification time is saved, and the verification efficiency is improved.
The function of the security module for protecting the transmission security of the specified DDR region in the DDR memory module may be as shown in table 1. In table 1, the main functions of the security module are listed.
TABLE 1 Primary Functions of the Security Module
The security module can be connected with a designated DDR area through an AXI bus; the security module may also be connected to other modules accessing the designated DDR area through the AXI bus to secure transmissions between the other modules and the designated DDR area. The connection diagram of the security module with the designated DDR area and other modules may be as shown in fig. 2. In FIG. 2, Fabric represents other modules that access the designated DDR region; firewall represents a security module; DDR denotes a designated DDR area.
And 102, configuring the module to be verified according to the module configuration data.
In the embodiment of the present disclosure, the chip verification apparatus may transmit the module configuration data of the module to be verified to the security module through the register interface of the module to be verified, so as to implement configuration processing of the module to be verified. Taking the module to be verified as the security module corresponding to the designated DDR area as an example, the chip verification device may transmit the module configuration data of the security module to the security module through the register interface of the security module, so as to implement the configuration data of the security module.
In the embodiment of the present disclosure, the chip verification apparatus may be connected to the security module through an Amba bus, and transmit the module configuration data to the register interface through an apb (advanced Peripheral bus) protocol of the Amba bus, so that the security module obtains the module configuration data through the register interface and performs configuration.
Step 103, inputting the reference input data into the module to be verified to obtain the actual output data of the module to be verified.
In the embodiment of the disclosure, after the chip verification device inputs the reference input data into the module to be verified, the module to be verified may process the reference input data according to the processing logic configured by the corresponding module configuration data to obtain a processing result; the processing result is taken as actual output data for the reference input data.
And 104, determining a verification result of the module to be verified according to the reference output data and the actual output data.
In the embodiment of the present disclosure, the process of the chip verification apparatus executing step 104 may be, for example, comparing the reference output data with the actual output data to determine whether the reference output data is consistent with the actual output data; when the reference output data is consistent with the actual output data, determining that the verification result is that the verification is passed; and when the reference output data is inconsistent with the actual output data, determining that the verification result is verification failure.
In summary, by determining a module to be verified in a chip and verification related data of the module to be verified, the verification related data includes: module configuration data, reference input data and corresponding reference output data; configuring the module to be verified according to the module configuration data; inputting the reference input data into a module to be verified to acquire actual output data of the module to be verified; according to the reference output data and the actual output data, the verification result of the module to be verified is determined, so that different modules to be verified in the chip can be verified in the same verification environment, the deployment of a plurality of verification environments is not needed, the verification cost is reduced, the verification time is saved, and the verification efficiency is improved.
FIG. 3 is a schematic diagram of a verification platform architecture according to an embodiment of the disclosure.
As shown in fig. 3, the verification platform includes: the device comprises a DUT, a ref model, a scoreboard and an APB VIP, wherein the DUT is a module to be verified, the APB VIP is a module configuration component, the refmodel is a reference model component, and the scoreboard is a comparison component. And connecting a module to be verified in the chip with the module configuration component, the reference model component and the comparison component through a bus, wherein the bus adopts an AXI protocol.
And the module configuration component is used for configuring the module configuration data and the reference input data of the module to be verified through the bus.
In the embodiment of the present disclosure, the DUT includes a design code of the whole Firewall, ax _ ddr _ mem _ Firewall _ reg is a register used to configure the operating mode of the security module, the register is inside the Firewall, and the configuration register adopts the APB protocol.
The reference model component is used for determining reference output data based on module configuration data and reference data output in the module to be verified; and the comparison module is used for determining a verification result based on the actual output data and the reference output data of the module to be verified.
In the disclosed embodiment, the ref model obtains reference output data from the reference input data and the module configuration data by simultaneously simulating and analyzing the behavior of the DUT. scoreboard compares the actual output data with the reference output data.
The process of verifying the chip is divided into three steps: external excitation, inspection mechanism, coverage. The external excitation is to apply a clock signal to the chip, apply a clock signal to the APB VIP, send out the APB protocol to configure the register, and the DUT, the ref model and the scoreboard are the checking mechanisms.
In the embodiment of the disclosure, firstly, the address and data of the register interface are configured, based on the working state of the security module, a random secure or non-secure transfer sent by a master is sent to the security module and a ref model, the security module outputs actual output data, and the ref model outputs reference output data. And finally, comparing the actual output data with the reference output data by the scoreboard, and outputting a verification result.
Fig. 4 is a schematic structural diagram of a chip verification apparatus according to an exemplary embodiment.
As shown in fig. 4, the chip verification apparatus 400 includes: a first determination module 410, a configuration module 420, an acquisition module 430, and a second determination module 440.
The first determining module 410 is configured to determine a module to be verified in a chip and verification-related data of the module to be verified, where the verification-related data includes: module configuration data, reference input data and corresponding reference output data;
the configuration module 420 is configured to configure the module to be verified according to the module configuration data;
an obtaining module 430, configured to input the reference input data into the module to be verified to obtain actual output data of the module to be verified;
a second determining module 440, configured to determine a verification result of the module to be verified according to the reference output data and the actual output data.
As a possible implementation manner of the embodiment of the present disclosure, the first determining module 410 is specifically configured to determine the module to be verified in a chip; determining module configuration data and reference input data of the module to be verified; determining the reference output data according to the module configuration data and the reference input data.
As a possible implementation manner of the embodiment of the present disclosure, the second determining module 440 is specifically configured to compare the reference output data with the actual output data, and determine whether the reference output data is consistent with the actual output data; when the reference output data is consistent with the actual output data, determining that the verification result is that the verification is passed; and when the reference output data is inconsistent with the actual output data, determining that the verification result is verification failure.
As a possible implementation manner of the embodiment of the present disclosure, the number of the modules to be verified is at least one; the module to be verified is a part of the module in the chip, or all the modules in the chip.
As a possible implementation manner of the embodiment of the present disclosure, when the modules to be verified are all modules in the chip, the reference input data is reference input data of the chip, and the reference output data is reference output data of the chip.
As a possible implementation manner of the embodiment of the present disclosure, the module to be verified includes a security module; the number of the safety modules is at least one; all modules or part of modules in the chip are provided with corresponding safety modules; the security module is connected to each module in the chip via an AXI bus.
As a possible implementation manner of the embodiment of the present disclosure, the security module is a security module corresponding to a designated area of a DDR memory in the chip; for each function of the security module, corresponding reference input data and reference output data are set.
The chip verification device of the embodiment of the disclosure determines a module to be verified in a chip and verification related data of the module to be verified, wherein the verification related data includes: module configuration data, reference input data and corresponding reference output data; configuring the module to be verified according to the module configuration data; inputting the reference input data into a module to be verified to acquire actual output data of the module to be verified; according to the reference output data and the actual output data, the verification result of the module to be verified is determined, so that different modules to be verified in the chip can be verified in the same verification environment, the deployment of a plurality of verification environments is not needed, the verification cost is reduced, the verification time is saved, and the verification efficiency is improved.
In order to implement the foregoing embodiments, the present disclosure further provides an electronic device, as shown in fig. 5, where fig. 5 is a block diagram of an electronic device of a chip verification method according to an exemplary embodiment. As shown in fig. 5, the electronic device 200 may further include:
a memory 210 and a processor 220, a bus 230 connecting different components (including the memory 210 and the processor 220), wherein the memory 210 stores a computer program, and when the processor 220 executes the program, the chip verification method according to the embodiment of the disclosure is implemented.
A program/utility 280 having a set (at least one) of program modules 270, including but not limited to an operating system, one or more application programs, other program modules, and program data, each of which or some combination thereof may comprise an implementation of a network environment, may be stored in, for example, the memory 210. The program modules 270 generally perform the functions and/or methodologies of the embodiments described in this disclosure.
The processor 220 executes various functional applications and data processing by executing programs stored in the memory 210.
It should be noted that, for the implementation process and the technical principle of the electronic device of the embodiment, reference is made to the foregoing explanation of the chip verification method of the embodiment of the present disclosure, and details are not described here again.
The electronic device provided by the embodiment of the disclosure determines a module to be verified in a chip and verification related data of the module to be verified, wherein the verification related data includes: module configuration data, reference input data and corresponding reference output data; configuring the module to be verified according to the module configuration data; inputting the reference input data into a module to be verified to acquire actual output data of the module to be verified; according to the reference output data and the actual output data, the verification result of the module to be verified is determined, so that different modules to be verified in the chip can be verified in the same verification environment, the deployment of a plurality of verification environments is not needed, the verification cost is reduced, the verification time is saved, and the verification efficiency is improved.
In order to implement the above embodiments, the embodiments of the present disclosure also provide a computer-readable storage medium.
Wherein the instructions in the computer readable storage medium, when executed by a processor of the electronic device, enable the electronic device to perform the chip verification method as previously described.
To implement the above embodiments, the present disclosure also provides a computer program product, which, when executed by a processor of an electronic device, enables the electronic device to perform the chip verification method as described above.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
It will be understood that the present disclosure is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.
Claims (18)
1. A method of chip verification, comprising:
determining a module to be verified in a chip and verification related data of the module to be verified, wherein the verification related data comprises: module configuration data, reference input data and corresponding reference output data;
configuring the module to be verified according to the module configuration data;
inputting the reference input data into the module to be verified to acquire actual output data of the module to be verified;
and determining a verification result of the module to be verified according to the reference output data and the actual output data.
2. The method according to claim 1, wherein the determining the module to be verified in the chip and the verification-related data of the module to be verified comprises:
determining the module to be verified in the chip;
determining module configuration data and reference input data of the module to be verified;
determining the reference output data according to the module configuration data and the reference input data.
3. The method according to claim 1, wherein determining the verification result of the module to be verified according to the reference output data and the actual output data comprises:
comparing the reference output data with the actual output data to determine whether the reference output data is consistent with the actual output data;
when the reference output data is consistent with the actual output data, determining that the verification result is that the verification is passed;
and when the reference output data is inconsistent with the actual output data, determining that the verification result is verification failure.
4. The method according to any one of claims 1 to 3, characterized in that the number of modules to be verified is at least one;
the module to be verified is a part of the module in the chip, or all the modules in the chip.
5. The method according to claim 4, wherein when the modules to be verified are all of the modules in the chip, the reference input data is reference input data of the chip, and the reference output data is reference output data of the chip.
6. The method of claim 4, wherein the module to be authenticated comprises a security module; the number of the safety modules is at least one;
all modules or part of modules in the chip are provided with corresponding safety modules; the security module is connected to each module in the chip via an AXI bus.
7. The method according to claim 6, wherein the security module is a security module corresponding to a designated area of a DDR memory in the chip;
for each function of the security module, corresponding reference input data and reference output data are set.
8. A chip verification apparatus, comprising:
the device comprises a first determination module and a second determination module, wherein the first determination module is used for determining a module to be verified in a chip and verification related data of the module to be verified, and the verification related data comprises: module configuration data, reference input data and corresponding reference output data;
the configuration module is used for configuring the module to be verified according to the module configuration data;
the acquisition module is used for inputting the reference input data into the module to be verified so as to acquire actual output data of the module to be verified;
and the second determining module is used for determining the verification result of the module to be verified according to the reference output data and the actual output data.
9. The apparatus according to claim 8, wherein the first determination module is, in particular,
determining the module to be verified in the chip;
determining module configuration data and reference input data of the module to be verified;
determining the reference output data according to the module configuration data and the reference input data.
10. The apparatus according to claim 8, characterized in that the second determination module is, in particular,
comparing the reference output data with the actual output data to determine whether the reference output data is consistent with the actual output data;
when the reference output data is consistent with the actual output data, determining that the verification result is that the verification is passed;
and when the reference output data is inconsistent with the actual output data, determining that the verification result is verification failure.
11. The apparatus according to any one of claims 8 to 10, wherein the number of modules to be verified is at least one;
the module to be verified is a part of the module in the chip, or all the modules in the chip.
12. The apparatus of claim 11, wherein when the modules to be verified are all of the modules in the chip, the reference input data is reference input data of the chip, and the reference output data is reference output data of the chip.
13. The apparatus of claim 11, wherein the module to be authenticated comprises a security module; the number of the safety modules is at least one;
all modules or part of modules in the chip are provided with corresponding safety modules; the security module is connected to each module in the chip via an AXI bus.
14. The apparatus according to claim 13, wherein the security module is a security module corresponding to a designated area of a DDR memory in the chip;
for each function of the security module, corresponding reference input data and reference output data are set.
15. A chip verification platform, comprising:
the module configuration component, the reference model component and the comparison component are respectively connected with a module to be verified in the chip through buses;
the module configuration component configures the module configuration data and the reference input data of the module to be verified through a bus;
the reference model component determines reference output data based on module configuration data in the module to be verified and the reference data output;
and the comparison module is used for determining a verification result based on the actual output data and the reference output data of the module to be verified.
16. An electronic device, comprising:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein the content of the first and second substances,
the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the chip verification method of any one of claims 1-7.
17. A computer-readable storage medium whose instructions, when executed by a processor of an electronic device, enable the electronic device to perform the chip verification method of any one of claims 1-7.
18. A computer program product comprising a computer program which, when executed by a processor of an electronic device, enables the electronic device to perform the chip verification method of any one of claims 1 to 7.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115599618A (en) * | 2022-11-17 | 2023-01-13 | 深圳市楠菲微电子有限公司（Cn） | Register dynamic relocation verification method and device, storage medium and processor |
| CN117034824A (en) * | 2023-08-25 | 2023-11-10 | 广州市粤港澳大湾区前沿创新技术研究院 | Simulation verification system, method, terminal and medium for multiplexing test cases and verification environments |
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2021
- 2021-11-25 CN CN202111415825.6A patent/CN114330176A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115599618A (en) * | 2022-11-17 | 2023-01-13 | 深圳市楠菲微电子有限公司（Cn） | Register dynamic relocation verification method and device, storage medium and processor |
| CN117034824A (en) * | 2023-08-25 | 2023-11-10 | 广州市粤港澳大湾区前沿创新技术研究院 | Simulation verification system, method, terminal and medium for multiplexing test cases and verification environments |
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