CN114328024A - PCIe function level reset implementation method and device, computer equipment and storage medium - Google Patents
PCIe function level reset implementation method and device, computer equipment and storage medium Download PDFInfo
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Abstract
The application relates to a method and a device for realizing PCIe function level reset, computer equipment and a storage medium, wherein the method comprises the following steps: the SSD acquires an FLR interrupt signal sent by the SSD controller, and the firmware jumps to an interrupt processing function to process an FLR event; the SSD goes back to the master state machine to enter a reset state and terminates the ongoing command; after all commands are normally terminated, the firmware sends an NVMe core reset request to the SSD controller; initializing NVMe by the SSD; the firmware writes the FLR completion to the SSD controller and waits for the hardware to report the FLR completion, the SSD reconfigures the PCIe registers. The invention can solve the problem of FLR test failure on the sanblaze test platform and can effectively improve the test efficiency.
Description
Technical Field
The invention relates to the technical field of solid state disks, in particular to a method and a device for realizing PCIe function level reset, computer equipment and a storage medium.
Background
Currently, PCIe Function Level Reset (FLR) is triggered by host software writing bit15 (initflr) of Device control register of PICe, and FLR needs to be completed within 100 ms. The FLR only resets the internal state and registers corresponding to the Function, without affecting the link specific registers.
However, the existing FLR scheme fails the FLR test on the sanblaze (an SSD test software) test platform, and since the SSD is performing the read-write command, the host issues the FLR request without waiting for the read-write command to end, and when the Device receives the FLR interrupt, the NVMe Core is reset in the interrupt, so that the unprocessed node is blocked, and the test cannot be completed smoothly, and finally the test fails.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a method, an apparatus, a computer device, and a storage medium for implementing PCIe function level reset.
A method of implementing a PCIe function hierarchy reset, the method comprising:
the SSD acquires an FLR interrupt signal sent by the SSD controller, and the firmware jumps to an interrupt processing function to process an FLR event;
the SSD goes back to the master state machine to enter a reset state and terminates the ongoing command;
after all commands are normally terminated, the firmware sends an NVMe core reset request to the SSD controller;
initializing NVMe by the SSD;
the firmware writes the FLR completion to the SSD controller and waits for the hardware to report the FLR completion, the SSD reconfigures the PCIe registers.
In one embodiment, the SSD acquires the FLR interrupt signal sent by the SSD controller, and the step of the firmware jumping to the interrupt handling function to process the FLR event further includes:
marking only the FLR event in the FLR interrupt event does not do reset related operations.
In one embodiment, before the step of acquiring, by the SSD, the FLR interrupt signal sent by the SSD controller, the method further includes:
after the SSD is electrified, the command is normally processed, and the FLR test script is executed;
the host sends an FLR reset request to the SSD.
In one embodiment, after the firmware writing FLR completion to the SSD controller and waiting for the hardware to report FLR completion, the step of the SSD reconfiguring PCIe registers further comprises:
and waiting for the host to send a controller configuration register enabling command, and restarting to process the command.
An apparatus for implementing a PCIe function level reset, the apparatus comprising:
the jump module is used for the SSD acquiring an FLR interrupt signal sent by the SSD controller, and the firmware jumps to an interrupt processing function to process an FLR event;
a termination module for the SSD returning to the master state machine to enter a reset state and terminating the ongoing command;
the sending module is used for sending an NVMe core reset request to the SSD controller by the firmware after all commands are normally terminated;
the initialization module is used for initializing the NVMe by the SSD;
and the write completion module is used for writing the FLR completion to the SSD controller by the firmware, waiting for the hardware to report that the FLR is completed, and reconfiguring the PCIe register by the SSD.
In one embodiment, the skip module is further configured to:
marking only the FLR event in the FLR interrupt event does not do reset related operations.
In one embodiment, the apparatus further comprises a request module configured to:
after the SSD is electrified, the command is normally processed, and the FLR test script is executed;
the host sends an FLR reset request to the SSD.
In one embodiment, the apparatus further comprises a waiting module configured to:
and waiting for the host to send a controller configuration register enabling command, and restarting to process the command.
A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps of any of the above methods when executing the computer program.
A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the steps of any of the methods described above.
The PCIe function level reset realization method, the PCIe function level reset realization device, the computer equipment and the storage medium acquire an FLR interrupt signal sent by an SSD controller through the SSD, and a firmware jumps to an interrupt processing function to process an FLR event; the SSD goes back to the master state machine to enter a reset state and terminates the ongoing command; after all commands are normally terminated, the firmware sends an NVMe core reset request to the SSD controller; initializing NVMe by the SSD; the firmware writes the FLR completion to the SSD controller and waits for the hardware to report the FLR completion, the SSD reconfigures the PCIe registers. The invention can solve the problem of FLR test failure on the sanblaze test platform and can effectively improve the test efficiency.
Drawings
FIG. 1 is a flow chart illustrating the FLR implementation in the conventional art;
FIG. 2 is a flow diagram that illustrates a method for implementing a PCIe function level reset in one embodiment;
FIG. 3 is a flow diagram illustrating a method for implementing a PCIe function level reset in another embodiment;
FIG. 4 is a schematic flow chart of an implementation of the FLR in one embodiment;
FIG. 5 is a block diagram of an apparatus for implementing a PCIe function level reset in one embodiment;
FIG. 6 is a block diagram of an apparatus for implementing a PCIe function level reset in another embodiment;
FIG. 7 is a block diagram showing an apparatus for implementing a PCIe function level reset in yet another embodiment;
FIG. 8 is a diagram illustrating an internal structure of a computer device according to an embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
At present, referring to the FLR implementation process in the conventional technology shown in fig. 1, the FLR test of the existing FLR scheme on the sanblaze test platform fails, because the SSD is performing a read-write command, the platform issues an FLR request when the host does not wait for the read-write command to be completed, and when the Device receives an FLR interrupt, the Device resets the NVMe Core in the interrupt, so that the node which has not been processed is blocked, and the test cannot be completed smoothly, and finally the test fails.
Based on the above, the invention provides a method for realizing PCIe function level reset, which aims to solve the problem of FLR test failure on a sanblaze test platform.
In one embodiment, as shown in fig. 2, there is provided a method for implementing a PCIe function hierarchy reset, the method comprising:
step 202, the SSD acquires an FLR interrupt signal sent by the SSD controller, and the firmware jumps to an interrupt handling function to process the FLR event;
step 204, the SSD returns to the main state machine to enter a reset state and terminates the ongoing command;
step 206, after all the commands are normally terminated, the firmware sends an NVMe core reset request to the SSD controller;
step 208, initializing NVMe by the SSD;
step 210, the firmware writes FLR completion to the SSD controller and waits for the hardware to report FLR completion, and the SSD reconfigures the PCIe register.
In this embodiment, an implementation method for PCIe function level reset is provided, and the method may be used for a sanblaze test platform. The simulation and verification products of SanBlaze corporation provide scalable, high performance and configurable simulation test environments for testing initiators (i.e., hosts) and targets (i.e., storage systems or SSD disks) involved in technologies such as FC, FCoE, iSCSI, SAS/SATA, NVMe over Fabric (NVMoF) and NVMe over FC (FC-NVMe). The simulation product of SanBlaze has been widely deployed by the vast majority of mainstream storage hardware and software vendors around the world.
The method can be used for correctly processing the SSD reset scheme when the host sends the FLR request when the SSD is in a read-write command, and the specific implementation process is as follows: firstly, the SSD acquires an FLR interrupt signal sent by the SSD controller, and the firmware jumps to an interrupt processing function to process an FLR event.
In one embodiment, the SSD acquires the FLR interrupt signal sent by the SSD controller, and the step of the firmware jumping to the interrupt processing function to process the FLR event further includes: marking only the FLR event in the FLR interrupt event does not do reset related operations. In this embodiment, when jumping to the interrupt handling function to process the FLR event, only the event is marked at this time, and no reset-related operation is performed.
And then, the SSD returns to the main state machine to enter a reset state and terminates the ongoing command, and after all the commands are normally terminated, the firmware sends an NVMe core reset request to the SSD controller.
Then, the SSD initializes NVMe, the firmware writes FLR completion to the SSD controller and waits for hardware to report the FLR completion, and the SSD reconfigures PCIe registers.
In this embodiment, the SSD acquires the FLR interrupt signal sent by the SSD controller, and the firmware jumps to an interrupt handling function to process the FLR event; the SSD goes back to the master state machine to enter a reset state and terminates the ongoing command; after all commands are normally terminated, the firmware sends an NVMe core reset request to the SSD controller; initializing NVMe by the SSD; the firmware writes the FLR completion to the SSD controller and waits for the hardware to report the FLR completion, the SSD reconfigures the PCIe registers. The problem of FLR test failure on sanblaze test platform can be solved to this scheme, can improve efficiency of software testing effectively.
In one embodiment, as shown in fig. 3, there is provided a method for implementing a PCIe function hierarchy reset, the method comprising:
step 302, after the SSD is powered on, normally processing the command, and executing the FLR test script;
step 304, the host sends a FLR reset request to the SSD;
step 310, after all the commands are normally terminated, the firmware sends an NVMe core reset request to the SSD controller;
step 312, initializing NVMe by the SSD;
step 314, the firmware writes FLR completion to the SSD controller and waits for the hardware to report that the FLR is complete, and the SSD reconfigures the PCIe register;
step 316, wait for the host to send the controller configuration register enable command, and resume processing the command.
In this embodiment, reference may be made to a flow diagram of FLR implementation shown in fig. 4, and a specific implementation process thereof is as follows:
1. after normal power-on, the SSD normally processes the command and executes the FLR test script.
2. The host sends a FLR reset request, which may specifically be triggered by writing bit15 (initflr) of a Device control register (Device control register) of the PICe.
3. The SSD receives an FLR interrupt signal from an SSD Controller.
4. The FW (firmware) jumps to an interrupt handling function to process the FLR event, only the event is marked at this time, and no reset related operation is done.
5. The SSD returns to the main state machine, enters the reset state, and first terminates the ongoing command abort.
6. Waiting for all commands to terminate normally.
7. The FW sends an NVMe core reset request to the SSD Controller.
8. And initializing the SSD by NVMe.
9. The FW writes the FLR done to the SSD controller and waits for the hardware to report the FLR done.
10. The SSD reconfigures PCIe registers.
11. Waiting for the host to issue CC EN (controller configuration register enable), the process command is restarted.
It should be understood that although the various steps in the flow charts of fig. 1-4 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least some of the steps in fig. 1-4 may include multiple sub-steps or multiple stages that are not necessarily performed at the same time, but may be performed at different times, and the order of performance of the sub-steps or stages is not necessarily sequential, but may be performed in turn or alternating with other steps or at least some of the sub-steps or stages of other steps.
In one embodiment, as shown in fig. 5, there is provided an apparatus 500 for implementing a PCIe function level reset, the apparatus comprising:
a jump module 501, configured to obtain, by the SSD, an FLR interrupt signal sent by the SSD controller, and jump the firmware to an interrupt processing function to process an FLR event;
a termination module 502 for the SSD to return to the master state machine to enter a reset state and terminate the ongoing command;
a sending module 503, configured to send, by the firmware, an NVMe kernel reset request to the SSD controller after all the commands are terminated normally;
an initialization module 504 for initializing NVMe by the SSD;
a write complete module 505 for the firmware to write FLR completion to the SSD controller and wait for the hardware to report that the FLR is complete, the SSD to reconfigure the PCIe register.
In one embodiment, the skip module 501 is further configured to:
marking only the FLR event in the FLR interrupt event does not do reset related operations.
In one embodiment, as shown in fig. 6, there is provided an implementation apparatus 500 for PCIe function level reset, the apparatus further comprising a request module 506 for:
after the SSD is electrified, the command is normally processed, and the FLR test script is executed;
the host sends an FLR reset request to the SSD.
In one embodiment, as shown in fig. 7, there is provided an implementation apparatus 500 for PCIe function level reset, the apparatus further comprising a waiting module 507 for:
and waiting for the host to send a controller configuration register enabling command, and restarting to process the command.
For specific limitations of the implementation apparatus for PCIe function level reset, reference may be made to the above limitations of the implementation method for PCIe function level reset, and details are not described here again.
In one embodiment, a computer device is provided, the internal structure of which may be as shown in FIG. 8. The computer apparatus includes a processor, a memory, and a network interface connected by a device bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises a nonvolatile storage medium and an internal memory. The nonvolatile storage medium stores an operating device, a computer program, and a database. The internal memory provides an environment for the operation device in the nonvolatile storage medium and the execution of the computer program. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program is executed by a processor to implement a method for implementing a PCIe function level reset.
Those skilled in the art will appreciate that the architecture shown in fig. 8 is merely a block diagram of some of the structures associated with the disclosed aspects and is not intended to limit the computing devices to which the disclosed aspects apply, as particular computing devices may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.
In one embodiment, a computer device is provided, comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps of the above method embodiments when executing the computer program.
In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the above respective method embodiments.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory, among others. Non-volatile memory can include read-only memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), Rambus Direct RAM (RDRAM), direct bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A method for implementing a PCIe function level reset, the method comprising:
the SSD acquires an FLR interrupt signal sent by the SSD controller, and the firmware jumps to an interrupt processing function to process an FLR event;
the SSD goes back to the master state machine to enter a reset state and terminates the ongoing command;
after all commands are normally terminated, the firmware sends an NVMe core reset request to the SSD controller;
initializing NVMe by the SSD;
the firmware writes the FLR completion to the SSD controller and waits for the hardware to report the FLR completion, the SSD reconfigures the PCIe registers.
2. The method of claim 1, wherein the SSD obtains an FLR interrupt signal sent by the SSD controller, and the step of the firmware jumping to the interrupt handling function to process the FLR event further comprises:
marking only the FLR event in the FLR interrupt event does not do reset related operations.
3. The method of claim 2, wherein the step of the SSD obtaining the FLR interrupt from the SSD controller is preceded by the step of:
after the SSD is electrified, the command is normally processed, and the FLR test script is executed;
the host sends an FLR reset request to the SSD.
4. The method of any of claims 1-3, wherein after the firmware writes the FLR completion to the SSD controller and waits for hardware to report the FLR completion, the SSD reconfiguring PCIe registers step further comprises:
and waiting for the host to send a controller configuration register enabling command, and restarting to process the command.
5. An apparatus for implementing a PCIe function level reset, the apparatus comprising:
the jump module is used for the SSD acquiring an FLR interrupt signal sent by the SSD controller, and the firmware jumps to an interrupt processing function to process an FLR event;
a termination module for the SSD returning to the master state machine to enter a reset state and terminating the ongoing command;
the sending module is used for sending an NVMe core reset request to the SSD controller by the firmware after all commands are normally terminated;
the initialization module is used for initializing the NVMe by the SSD;
and the write completion module is used for writing the FLR completion to the SSD controller by the firmware, waiting for the hardware to report that the FLR is completed, and reconfiguring the PCIe register by the SSD.
6. The apparatus for implementing a PCIe function hierarchy reset of claim 5, wherein the skip module is further configured to:
marking only the FLR event in the FLR interrupt event does not do reset related operations.
7. The apparatus for implementing a PCIe function level reset of claim 6, wherein the apparatus further comprises a request module configured to:
after the SSD is electrified, the command is normally processed, and the FLR test script is executed;
the host sends an FLR reset request to the SSD.
8. The apparatus for implementing a PCIe function hierarchy reset of any one of claims 5 to 7, wherein the apparatus further comprises a wait module configured to:
and waiting for the host to send a controller configuration register enabling command, and restarting to process the command.
9. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the steps of the method of any of claims 1 to 4 are implemented when the computer program is executed by the processor.
10. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method of any one of claims 1 to 4.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116301266A (en) * | 2023-03-03 | 2023-06-23 | 无锡众星微***技术有限公司 | PCIe (peripheral component interconnect express) equipment in-band resetting method and device based on security authentication |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116301266A (en) * | 2023-03-03 | 2023-06-23 | 无锡众星微***技术有限公司 | PCIe (peripheral component interconnect express) equipment in-band resetting method and device based on security authentication |
| CN116301266B (en) * | 2023-03-03 | 2023-11-17 | 无锡众星微***技术有限公司 | PCIe (peripheral component interconnect express) equipment in-band resetting method and device based on security authentication |
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