CN114326496B - High-speed data acquisition instrument and acquisition method thereof - Google Patents
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Abstract
The invention discloses a high-speed data acquisition instrument and an acquisition method thereof, wherein the acquisition method of the high-speed data acquisition instrument is used for acquiring data and comprises the following steps of S1: the data acquisition boards transmit the acquired analog signals to the data processing board, and the data processing board performs data processing on the received analog signals; step S1.1: each data acquisition board is provided with a plurality of independent signal input channels so that the data acquisition board performs multichannel analog signal acquisition. According to the high-speed data acquisition instrument and the acquisition method thereof disclosed by the invention, a single acquisition instrument can acquire vibration, strain, temperature, voltage and other data of a plurality of channels at the same time, and a plurality of acquisition instruments can be used in cascade through Ethernet, so that the real-time, accurate and complete acquisition and storage of the data can be ensured under the condition of realizing multiple channels and high sampling rate.
Description
Technical Field
The invention belongs to the technical field of data acquisition, and particularly relates to a high-speed data acquisition instrument and an acquisition method of the high-speed data acquisition instrument.
Background
The traditional high-speed data acquisition instrument is generally expanded by adopting an x86 system architecture and a PCI, PCIE and other board card architectures, and when the number of channels is increased, the volume, the weight and the power consumption are also increased, the deployment is inconvenient, and the use is inflexible. In addition, the board card type framework is only suitable for laboratory environments, connection looseness is easy to cause under the external field environments of strong vibration and impact, and the reliability of data acquisition is affected. In some small-volume and low-power-consumption data acquisition systems, a singlechip and a DSP are often selected as main controllers, and the devices can realize the acquisition function, but the acquisition signals are single, the sampling frequency is low, the storage bandwidth is low, the data transmission rate is low, and only the low-speed acquisition application fields can be met. In addition, the traditional data acquisition equipment often has only one signal acquisition function for each channel, if different signals are to be acquired, different acquisition boards or adapter plates are required to be configured, the complexity of the system is increased, and the reliability of the system is reduced.
Accordingly, the above problems are further improved.
Disclosure of Invention
The invention mainly aims to provide a high-speed data acquisition instrument and an acquisition method thereof, wherein a single acquisition instrument can acquire vibration, strain, temperature, voltage and other data of a plurality of channels at the same time, and a plurality of acquisition instruments can be used in cascade through Ethernet, so that the real-time, accurate and complete acquisition and storage of the data can be ensured under the condition of realizing multi-channel and high sampling rate, and the requirements of vibration, strain, temperature, voltage and other tests in industries such as aerospace, aviation, ships, high-speed rail, automobiles and the like can be met.
Another object of the present invention is to provide a high-speed data acquisition apparatus and an acquisition method thereof, which have miniaturization, multiple channels, multiple functions, and high-speed data acquisition, and can simultaneously acquire data such as vibration, strain, platinum resistance, thermocouple, voltage, etc. of multiple channels, and can ensure real-time performance, accuracy, and integrity of data under the conditions of high sampling rate and multiple channels.
In order to achieve the above object, the present invention provides a method for collecting data by a high-speed data collector, comprising the following steps:
step S1: the data acquisition boards transmit the acquired analog signals to the data processing board, and the data processing board performs data processing on the received analog signals;
Step S1.1: each data acquisition board is provided with a plurality of independent signal input channels so that the data acquisition board can acquire multichannel analog signals;
Step S1.2: each signal input channel transmits the received analog signals to a respective signal source selection circuit to selectively access different kinds of analog signals and transmits the accessed analog signals to a program-controlled amplifying circuit so as to selectively amplify the analog signals;
Step S1.3: the low-pass filter circuit receives the amplified analog signal and performs filter processing on the analog signal by selecting a matched filter gear;
Step S1.4: the single-ended differential circuit receives the filtered analog signals and conditions the analog signals into input ranges and signal types matched with the ADC acquisition units, and the ADC acquisition units perform data acquisition on all current signal input channels so as to ensure high-precision synchronous data acquisition of all signal input channels of each data acquisition board.
As a further preferable embodiment of the above embodiment, step S1.4 further includes:
step S1.5: the first processing unit of the data processing board performs data access through interfaces with the number corresponding to the signal input channels, so that a plurality of ADC acquisition units are controlled, data are acquired, and acquired data are cached;
Step S1.6: the second processing unit of the data processing board reads the collected data cached in the first processing unit and further stores the collected data so that the second processing unit processes the collected data.
As a further preferable embodiment of the above embodiment, step S1.6 is specifically implemented as the following steps:
Step S1.6.1: the memory bar (DDR 3) of the second processing unit caches the read acquired data, the processor CPU0 stores the acquired data through a memory (EMMC), and the processor CPU0 is provided with a GPS time service interface so as to connect with a GPS module to complete serial time data analysis and time synchronization;
step S1.6.2: the processor CPU1 communicating with the processor CPU0 is provided with a gigabit Ethernet interface, an antenna interface and a real-time clock interface, wherein:
The gigabit Ethernet interface is used for controlling data acquisition, data checking and data downloading through the Ethernet;
The antenna interface is used for wireless data acquisition control and wireless data receiving and transmitting;
The real-time clock interface is used to enable recording of the data acquisition time (in the absence of GPS).
As a further preferable technical solution of the above technical solution, in step S1, buffering data by a ring buffer queue is implemented as the following steps:
T1.1: generating a high-level interrupt after N bytes are fully stored in a FIFO buffer of a first processing unit, so that a buffer space is opened up in a memory bank by a processor CPU1 to serve as a ring buffer queue, and when the processor CPU1 receives the high-level interrupt, starting DMA data movement once to move data (8192) in the FIFO buffer into a memory bank pointer base address Addr 0;
The CPU1 informs the CPU0 to fetch (8192 bytes) data from the memory bank pointer base address by internal interrupt mode, then waits for the next FIFO buffer interrupt, and after the next FIFO buffer interrupt comes, circularly stores the data into the address of the memory bank base address;
After the processor CPU0 receives the interrupt, a file is newly built in the memory according to the data acquisition time, acquisition configuration information is written in, then data in the memory bank queue is circularly stored in the file every time the interrupt of the processor CPU1 is received, the processor CPU1 waits for the FIFO interrupt and simultaneously sends the cache data in the memory bank queue to the upper computer through the gigabit Ethernet, and after the acquisition is finished, the upper computer inquires, deletes and downloads the file stored in the memory.
In order to achieve the above object, the present invention further provides a high-speed data acquisition apparatus, comprising a data processing board and a plurality of data acquisition boards, wherein:
The data acquisition boards transmit the acquired analog signals to the data processing board, and the data processing board performs data processing on the received analog signals;
each data acquisition board is provided with a plurality of independent signal input channels so that the data acquisition board can acquire multichannel analog signals;
Each signal input channel transmits the received analog signals to a respective signal source selection circuit to selectively access different kinds of analog signals and transmits the accessed analog signals to a program-controlled amplifying circuit so as to selectively amplify the analog signals;
The low-pass filter circuit receives the amplified analog signal and performs filter processing on the analog signal by selecting a matched filter gear;
The single-ended differential circuit receives the filtered analog signals and conditions the analog signals into input ranges and signal types matched with the ADC acquisition units, and the ADC acquisition units perform data acquisition on all current signal input channels so as to ensure high-precision synchronous data acquisition of all signal input channels of each data acquisition board.
As a further preferable technical scheme of the above technical scheme, the first processing unit of the data processing board performs data access through interfaces corresponding to the number of the signal input channels, so as to control and data acquisition on the plurality of ADC acquisition units and buffer acquired data;
the second processing unit of the data processing board reads the collected data cached in the first processing unit and further stores the collected data so that the second processing unit processes the collected data.
Drawings
Fig. 1 is a schematic structural diagram of a high-speed data acquisition instrument and an acquisition method thereof according to the present invention.
Fig. 2 is a schematic structural diagram of a data acquisition board of the high-speed data acquisition instrument and the acquisition method thereof.
Fig. 3 is a schematic structural diagram of a data processing board of the high-speed data acquisition instrument and the acquisition method thereof.
Fig. 4 is a source selection circuit diagram of a data processing board of the high-speed data acquisition instrument and the acquisition method thereof of the present invention.
Fig. 5 is a schematic diagram of a programmable amplifier circuit, a low pass filter circuit and a single-ended differential circuit of the high-speed data acquisition instrument and the acquisition method thereof of the present invention.
FIG. 6 is a graph of buffered data from a circular buffer queue for a high-speed data acquisition instrument and method of the present invention.
Detailed Description
The following description is presented to enable one of ordinary skill in the art to make and use the invention. The preferred embodiments in the following description are by way of example only and other obvious variations will occur to those skilled in the art. The basic principles of the invention defined in the following description may be applied to other embodiments, variations, modifications, equivalents, and other technical solutions without departing from the spirit and scope of the invention.
In a preferred embodiment of the invention, it should be noted by those skilled in the art that analog signals and the like to which the invention relates may be regarded as prior art.
Preferred embodiments.
The invention discloses a collection method of a high-speed data collector, which is used for collecting data and comprises the following steps:
step S1: the data acquisition boards transmit the acquired analog signals to the data processing board, and the data processing board performs data processing on the received analog signals;
Step S1.1: each data acquisition board is provided with a plurality of independent signal input channels so that the data acquisition board can acquire multichannel analog signals;
Step S1.2: each signal input channel transmits the received analog signals to a respective signal source selection circuit to selectively access different kinds of analog signals and transmits the accessed analog signals to a program-controlled amplifying circuit so as to selectively amplify the analog signals;
Step S1.3: the low-pass filter circuit receives the amplified analog signal and performs filter processing on the analog signal by selecting a matched filter gear;
Step S1.4: the single-ended differential circuit receives the filtered analog signals and conditions the analog signals into input ranges and signal types matched with the ADC acquisition units, and the ADC acquisition units perform data acquisition on all current signal input channels so as to ensure high-precision synchronous data acquisition of all signal input channels of each data acquisition board.
Specifically, step S1.4 further includes:
step S1.5: the first processing unit of the data processing board performs data access through interfaces with the number corresponding to the signal input channels, so that a plurality of ADC acquisition units are controlled, data are acquired, and acquired data are cached;
Step S1.6: the second processing unit of the data processing board reads the collected data cached in the first processing unit and further stores the collected data so that the second processing unit processes the collected data.
More specifically, step S1.6 is implemented as the following steps:
Step S1.6.1: the memory bar (DDR 3) of the second processing unit caches the read acquired data, the processor CPU0 stores the acquired data through a memory (EMMC), and the processor CPU0 is provided with a GPS time service interface so as to connect with a GPS module to complete serial time data analysis and time synchronization;
step S1.6.2: the processor CPU1 communicating with the processor CPU0 is provided with a gigabit Ethernet interface, an antenna interface and a real-time clock interface, wherein:
The gigabit Ethernet interface is used for controlling data acquisition, data checking and data downloading through the Ethernet;
The antenna interface is used for wireless data acquisition control and wireless data receiving and transmitting;
The real-time clock interface is used to enable recording of the data acquisition time (in the absence of GPS).
Further, in step S1, the data is buffered through the ring buffer queue, which is specifically implemented as the following steps:
T1.1: generating a high-level interrupt after N bytes are fully stored in a FIFO buffer of a first processing unit, so that a buffer space is opened up in a memory bank by a processor CPU1 to serve as a ring buffer queue, and when the processor CPU1 receives the high-level interrupt, starting DMA data movement once to move data (8192) in the FIFO buffer into a memory bank pointer base address Addr 0;
The CPU1 informs the CPU0 to fetch (8192 bytes) data from the memory bank pointer base address by internal interrupt mode, then waits for the next FIFO buffer interrupt, and after the next FIFO buffer interrupt comes, circularly stores the data into the address of the memory bank base address;
After the processor CPU0 receives the interrupt, a file is newly built in the memory according to the data acquisition time, acquisition configuration information is written in, then data in the memory bank queue is circularly stored in the file every time the interrupt of the processor CPU1 is received, the processor CPU1 waits for the FIFO interrupt and simultaneously sends the cache data in the memory bank queue to the upper computer through the gigabit Ethernet, and after the acquisition is finished, the upper computer inquires, deletes and downloads the file stored in the memory.
The invention also discloses a high-speed data acquisition instrument, which comprises a data processing board and a plurality of data acquisition boards, wherein:
The data acquisition boards transmit the acquired analog signals to the data processing board, and the data processing board performs data processing on the received analog signals;
each data acquisition board is provided with a plurality of independent signal input channels so that the data acquisition board can acquire multichannel analog signals;
Each signal input channel transmits the received analog signals to a respective signal source selection circuit to selectively access different kinds of analog signals and transmits the accessed analog signals to a program-controlled amplifying circuit so as to selectively amplify the analog signals;
The low-pass filter circuit receives the amplified analog signal and performs filter processing on the analog signal by selecting a matched filter gear;
The single-ended differential circuit receives the filtered analog signals and conditions the analog signals into input ranges and signal types matched with the ADC acquisition units, and the ADC acquisition units perform data acquisition on all current signal input channels so as to ensure high-precision synchronous data acquisition of all signal input channels of each data acquisition board.
Preferably, the first processing unit of the data processing board performs data access through interfaces with the number corresponding to the signal input channels, so as to control and data acquisition on the plurality of ADC acquisition units and buffer acquired data;
the second processing unit of the data processing board reads the collected data cached in the first processing unit and further stores the collected data so that the second processing unit processes the collected data.
The invention aims to solve the technical problems that: the traditional high-speed data acquisition instrument is based on a board-card type architecture, has large volume, large weight and high power consumption, is easy to cause connection looseness under the external field environment of strong vibration and impact, and influences the reliability of data acquisition; the traditional small-volume and low-power-consumption data acquisition system mainly uses a single chip microcomputer and a DSP as a main controller, and has the advantages of single acquisition signal, low sampling frequency, low storage bandwidth, low data transmission rate, and the sampling rate, the storage bandwidth and the data transmission rate are mainly limited by the processing speed of the main controller. Aiming at the problems of high power consumption, large volume, single acquisition signal, low sampling frequency and low data transmission rate of the existing data acquisition instrument, the miniature, multi-channel, multifunctional and high-speed data acquisition instrument is provided, and the real-time performance, accuracy and integrity of data can be ensured under the conditions of high sampling rate and multi-channel.
The principle of the invention is as follows:
The system composition and the functional block diagram are shown in figure 1. A miniaturized, multi-channel, multi-functional, high-speed data acquisition instrument is preferably composed of 4 data acquisition boards and one data processing board. In the shell, from bottom to top are respectively: data acquisition board 4, data acquisition board 3, data acquisition board 2, data acquisition board 1, data processing board. Each data acquisition board supports the acquisition of 8 paths of analog signals, and supports the acquisition, storage and transmission of 32 paths of analog signals. It should be noted that, in the present invention, the 4 data acquisition boards are combined to form 32 channels, and the combination of the number is not limited to the 4 data acquisition boards and the 32 channels. The data processing board is provided with a gigabit Ethernet interface, a GPS time service interface, an antenna interface and a power interface. The gigabit Ethernet interface is used for user instruction interaction and data acquisition transmission, the GPS timing interface is used for accurate timing of equipment and acquisition synchronization among a plurality of pieces of equipment, the antenna interface is used for wireless acquisition and wireless transmission, and the power interface is used for system power supply.
The composition of the data acquisition plate is shown in fig. 2. A data acquisition board of a miniaturized, multi-channel, multifunctional and high-speed data acquisition instrument consists of a 24-bit 8-channel parallel information source selection circuit, a program-controlled amplifying circuit, a low-pass filter circuit, a single-end-to-differential circuit and a 24-bit 8-channel synchronous sampling ADC. The 24-bit 8-channel parallel processing analog circuit and the 24-bit 8-channel synchronous sampling ADC are adopted, so that the independence of data acquisition of each channel can be ensured, and the damage of one channel can not affect the normal operation of other channels.
The signal source selection circuit adopts a four-out analog switch to realize the access of various analog signals such as vibration, strain, platinum resistance, thermocouple, voltage and the like, and the selection control pin of the analog switch is from the data processing board. The front end of the signal input adopts a multi-core aviation plug, and different cores correspond to different signal inputs.
The program-controlled amplifying circuit mainly completes the amplification of different signals, adopts four instrument amplifiers with different amplification factors, and the amplifying gear selection pins of the instrument amplifiers come from the data processing board.
The low-pass filter circuit adopts a four-gear analog Butterworth low-pass filter, the filtering gears are respectively 100Hz, 1kHz, 10kHz and 50kHz, the selection of the filtering gears adopts analog switch selection, and the selection pins of the filtering gears come from the data processing board.
The single-ended differential circuit is used for conditioning the filtered analog signals into the proper input range and signal type of the ADC chip.
A data acquisition board of a miniaturized, multi-channel, multifunctional and high-speed data acquisition instrument adopts a 24-bit 8-channel synchronous sampling ADC, so that high-precision synchronous data acquisition of all channels is ensured. The 8-channel synchronous sampling ADC is connected with the data processing board through an SPI interface.
The data processing board is shown in fig. 3. The data processing board is used for realizing the collection, processing, transmission and storage of high-speed data by a ZYNQ processor architecture. The ZYNQ processor architecture consists of two parts, namely PL and PS: the PL part is a logic part and is realized by an FPGA; the PS is a system part and consists of a dual-core Cortex-A9 ARM processor.
The FPGA realizes the control and data acquisition of a plurality of AD chips through a plurality of SPI ports, and data are cached in the FIFO inside the FPGA. The FPGA is used as a processor element of a miniaturized, multi-channel, multifunctional and high-speed data acquisition instrument, and has the advantages of high clock frequency, small internal delay, high speed, logic parallel processing and the like, thereby achieving the functions of multi-channel parallel high-speed data acquisition and caching.
The dual-core ARM processor uses DMA mode data ADC to collect and read, and caches the data into DDR3, and realizes logic functions such as Ethernet communication, data storage and the like. The CPU0 of the dual-core ARM processor controls the EMMC chip to realize data storage through the EMMC interface, and completes the serial time data analysis and time synchronization functions of the GPS module. The CPU1 of the dual-core ARM processor realizes the data transmission of the gigabit Ethernet, a user can control data acquisition, check data and download data through the Ethernet, the wireless module is controlled to realize wireless acquisition control and wireless data receiving and transmitting, the real-time clock is controlled to realize a clock function, and the real-time clock is used for realizing the recording function of data acquisition time under the condition without GPS.
The main innovation points and the technical progress points of the miniaturized, multi-channel, multifunctional and high-speed data acquisition instrument are as follows:
(1) The volume is small. The data acquisition instrument is small in size by adopting a mode that four data acquisition plates and one data processing plate are stacked from bottom to top. The volume of the miniaturized, multi-channel, multifunctional and high-speed data acquisition instrument is within 210mm multiplied by 120mm multiplied by 85mm, and the instrument is small, light and convenient to carry.
(2) Multiple channels. Through the optimization of the circuit composition structure, the number of channels is ensured while the volume is small, and the acquisition of up to 32 channels of data is realized by a single data acquisition instrument. And a plurality of data acquisition instruments can be cascaded through gigabit Ethernet, so that data acquisition of more channels is realized.
(3) And (5) multifunctional data acquisition. A data acquisition instrument can compromise multiple signals such as vibration, meeting an emergency, platinum resistance, thermocouple, voltage simultaneously, and the different cores of aviation plug correspond different signal input, need not to adopt the conversion board or change other types of collection integrated circuit boards, and it is more convenient nimble to use, and the use scene is wider.
(4) The sampling frequency is high, and the acquisition accuracy is high. The ZYNQ system architecture of the FPGA and the dual-core Cortex-A9 ARM processor is adopted, and the parallel high-speed data processing of the FPGA and the storage and network performance of the ARM processor are considered. The highest sampling frequency can reach 144KHz by using a 24-bit synchronous ADC chip, the noise level is better than 50uv, and most data acquisition fields are satisfied.
(5) The storage and transmission bandwidth is high. The ZYNQ system architecture of the FPGA and the dual-core Cortex-A9 ARM processor is adopted, the FPGA is responsible for controlling the acquisition and the buffer of the data of the front-end ADC acquisition chip, the ZYNQ stores the data to the local EMMC by utilizing the dual-core Cortex-A9 ARM processor, and the data is sent to the upper computer in real time through the LWIP network protocol stack. Real-time data storage and data transmission are realized, and data double insurance is realized.
(6) The synchronism is high. Each path of signal uses an independent analog conditioning circuit, and a 24-bit synchronous ADC chip is adopted to realize synchronous acquisition, so that the synchronism of multichannel data acquisition is ensured.
(7) The power consumption is low. The ZYNQ system architecture of the FPGA+dual-core Cortex-A9 ARM processor is adopted, the mode based on the x86 architecture and the acquisition board card of the traditional data acquisition instrument is abandoned, the power consumption is greatly reduced, the power consumption is less than 10W, the power can be supplied by adopting a 12V-24V portable power supply or a battery, and the use occasions of various data acquisition and monitoring are met.
Preferably, the invention also discloses a high-speed data acquisition instrument, which is used for data acquisition and comprises a data processing board and a plurality of data acquisition boards, wherein the data acquisition boards are electrically connected with the data processing board, each data acquisition board comprises an ADC acquisition unit and a plurality of signal input channels, and each signal input channel is provided with a signal source selection circuit, a program-controlled amplifying circuit, a low-pass filter circuit and a single-ended differential circuit, wherein:
The input end of the signal source selection circuit inputs an analog signal input from a signal input channel, the output end of the signal source selection circuit is electrically connected with the input end of the program-controlled amplifying circuit, the output end of the program-controlled amplifying circuit is electrically connected with the input end of the low-pass filter circuit, the output end of the low-pass filter circuit is electrically connected with the input end of the single-ended differential circuit, and the output end of the single-ended differential circuit is electrically connected with the input end of a corresponding channel of the ADC acquisition unit.
Specifically, the data processing board comprises a first processing unit and a second processing unit, the first processing unit is electrically connected with the plurality of ADC acquisition units through an SPI interface, and the second processing unit comprises a gigabit Ethernet interface, a GPS time service interface, an antenna interface and a power interface.
More specifically, the source selection circuit includes an aviation plug connection unit J1, an analog switch U2, and a constant current source U1, wherein:
The 2 pins of the aviation plug connection unit J1 are electrically connected with the 5 pins of the analog switch U2, the 6 pins of the aviation plug connection unit J1 are electrically connected with the 12 pins of the analog switch U2, and the 10 pins of the aviation plug connection unit J1 are electrically connected with the 10 pins of the analog switch U2.
It should be noted that the source selection circuit further includes an operational amplifier U3A, the negative input end of the operational amplifier U3A is electrically connected with the 8 pins of the aviation plug connection unit J1, the output end of the operational amplifier U3A is electrically connected with the 7 pins of the aviation plug connection unit J1, the 3 pins of the aviation plug connection unit J1 are grounded through a resistor R5, a resistor R6 and a resistor R7 in sequence, and the common connection end of the resistor R6 and the resistor R7 is connected with the 5 pins of the aviation plug connection unit J1.
Further, the program-controlled amplifying circuit includes an amplifier U4, a1 pin of the amplifier U4 is electrically connected with a 9 pin of the analog switch U2 through a resistor R9, a 10 pin of the amplifier U4 is electrically connected with an 8 pin of the analog switch U2 through a resistor R12, a capacitor C8 is connected between the 1 pin and the 10 pin of the amplifier U4, one end of the capacitor C8 close to the resistor R9 is grounded through a capacitor C7, and one end of the capacitor C8 close to the resistor R12 is grounded through a capacitor C10.
Still further, the low pass filter circuit comprises an operational amplifier U3B and an analog switch U7, wherein:
The 7 pin of the amplifier U4 is electrically connected with the positive input end of the operational amplifier U3B through a resistor R10 and a resistor R11 in sequence;
The common connection end of the resistor R10 and the resistor R11 is electrically connected with the 8 pin of the analog switch U7, the output end of the operational amplifier U3B is electrically connected with the 4 pin of the analog switch U7 through a capacitor C18, and the positive input end of the operational amplifier U3B is electrically connected with the 9 pin of the analog switch U7.
Preferably, the single-ended to differential circuit includes a single-ended to differential unit U6, and an output end of the operational amplifier U3B is electrically connected to an positive input end of the single-ended to differential unit U6 through a resistor R14.
The principle is as follows:
The source selection circuit is shown in fig. 4. The J1 is connected with the multi-core aviation plug, the 10-core aviation plug is respectively connected with 10 pins of the J1, and different signal inputs can be switched through different wiring modes and selection of the analog switch U2. The information source selection circuit adopts a four-out analog switch U2 to realize the access of a plurality of different analog signals such as vibration, strain, platinum resistance, thermocouple, voltage and the like.
U1 is constant current source circuit, and the electric current of constant current source is adjusted to R2, provides the constant current source for ICP type vibration sensor, and C4 and R3 constitute high pass filter circuit, and the vibration signal after the high pass filtration inserts U2's 4 feet, and U2's 13 feet is through pull-down resistor R1 ground connection. If the external vibration sensor is connected with pins 4 and 9 of the J1, the data processing board controls pins 16 and 1 of the analog switch to be respectively set to be low level (namely, gear 00), and then acquisition of vibration signals can be achieved.
R5, R6 and R7 form a strain bridge circuit, an analog switch selects gear 01, and the full bridge, the half bridge, the quarter bridge and the quarter bridge three-wire system connection method can be realized together with J1: if the external strain gauge is connected with pins 1, 2,6 and 9 of J1, a full-bridge strain circuit can be realized; if the external strain gauge is connected with pins 1, 2 and 9 of the J1 and pins 5 and 6 of the aviation plug are short-circuited, a half-bridge strain circuit can be realized; if the external strain gauge is connected with pins 3 and 9 of the J1, and pins 2 and 3 of the aviation plug are short-circuited, and pins 5 and 6 are short-circuited, a quarter bridge strain circuit can be realized; if the external strain gauge is connected with pins 2, 3 and 9 of the J1 (the pins 2 and 3 are connected with one end of the strain gauge and the pin 9 is connected with the other end of the strain gauge), and meanwhile, pins 5 and 6 of the aviation plug are short-circuited, a four-way bridge three-wire system strain circuit can be realized.
U3A and R8 form a second constant current source circuit for providing a precise constant current source for the four-wire platinum thermal resistor, the current is determined by the 3-pin voltage Vref of U3A and R8, and the current is Vref/R8. The four-wire platinum thermal resistor is connected with pins 2, 7, 6 and 8 of the J1, and meanwhile, the analog switch selects gear 10, so that the four-wire precise temperature measuring circuit can be realized.
The resistor R4 provides a direct current loop for the thermocouple, and if the thermocouple is connected with pins 2 and 10 of the J1, the analog switch selects the gear 11, so that the thermocouple measuring circuit can be realized.
If the voltage signal is connected to pins 2 and 6 of J1, the analog switch selects gear 01, and then the measurement of any voltage can be realized.
The program-controlled amplifying circuit, the low-pass filter circuit and the single-end-to-differential circuit are shown in fig. 5. The program-controlled amplifying circuit U4 mainly completes signal amplification, and the pins 4, 5 and 6 of the amplifying gear selection pin U4 come from the data processing board. R9, R12, C7, C8 and C10 realize a radio frequency interference filter circuit.
The four-gear analog Butterworth low-pass filter is formed by the operational amplifier U3B and a resistor and a capacitor near the analog switch U7, the low-pass filtering function is realized, the filtering gears are respectively 100Hz, 1kHz, 10kHz and 50kHz, the 1 pin and the 16 pin of the analog switch U7 realize the function of filtering gear selection, and the filtering gear selection pin is from a data processing board.
An ADC selected by a miniaturized, multi-channel, multifunctional and high-speed data acquisition instrument is of a differential input type. The single-end-to-differential unit U6 is used for conditioning the filtered analog signals into differential signal types suitable for the ADC chip. A data acquisition board of a miniaturized, multi-channel, multifunctional and high-speed data acquisition instrument adopts a 24-bit 8-channel synchronous sampling ADC, so that high-precision synchronous data acquisition of all channels is ensured. The 8-channel synchronous sampling ADC is connected with the data processing board through an SPI interface.
The data processing board is shown in fig. 3. The data processing board is used for realizing the collection, processing, transmission and storage of high-speed data by a ZYNQ processor architecture. The ZYNQ processor architecture consists of two parts, namely PL and PS: the PL part is a logic part and is realized by an FPGA; the PS is a system part and consists of a dual-core Cortex-A9 ARM processor.
The FPGA realizes parallel control and data acquisition of a plurality of AD chips through a plurality of SPI ports, and the acquired data is cached in the FIFO inside the FPGA. The dual-core ARM processor uses DMA mode data ADC to collect and read, and caches the data into DDR3, and realizes logic functions such as Ethernet communication, data storage and the like. The CPU0 of the dual-core ARM processor controls the EMMC chip to realize data storage through the EMMC interface, and completes the serial time data analysis and time synchronization functions of the GPS module. The CPU1 of the dual-core ARM processor realizes the data transmission of the gigabit Ethernet, and a user can control data acquisition, data checking and data downloading through the Ethernet. The CPU1 is connected with the wireless module, and the wireless module can be controlled to realize wireless acquisition control and wireless data receiving and transmitting, so as to realize remote control acquisition control. The CPU1 is connected with a real-time clock, realizes a clock function and is used for realizing a data acquisition time recording function under the condition of no GPS.
The data processing board part of the miniaturized, multi-channel, multifunctional and high-speed data acquisition instrument is mainly used for storing and transmitting ADC sampling data in real time. In order to match the data storage and data transmission speed mismatch, a ring buffer queue is used to buffer the data.
The ring buffer queue dataflow diagram is shown in fig. 6. After the FIFO buffer of the FPGA is full of N bytes (8192 in this example), the FPGA generates a high level interrupt. The CPU1 opens up a 4MB buffer space in the DDR3 to be used as a ring buffer queue, and when the CPU1 receives a high-level interrupt, the CPU starts one time of DMA data movement to move 8192 data in the FIFO to the DDR3 pointer base address Addr 0. The CPU1 informs the CPU0 to fetch 8192 bytes of data from the DDR3 pointer base address in an internal software interrupt mode, waits for the next FIFO interrupt, and circularly stores the data into the address of the DDR3 base address addr0+8192 bytes multiplied by N (the number of FIFO interrupts) pointers after the next FIFO interrupt arrives. When the CPU0 receives the interrupt, a file is newly built in the EMMC according to the data acquisition time, acquisition configuration information is written into the file, and then the data in the DDR3 queue is circularly stored in the file every time the software interrupt of the CPU1 is received. The CPU1 waits for the FIFO interrupt and sends the cache data in the DDR3 queue to the upper computer software through the gigabit Ethernet. After the collection is finished, the files stored in the EMMC can be inquired, deleted and downloaded through the upper computer.
ZYNQ utilizes dual core Cortex-A9MPCore resources to buffer data in FIFO into a data queue of 4MB size. A CPU core stores the data in the queue into a local EMMC so as to facilitate later data viewing and downloading; the other CPU core sends the data in the queue to the upper computer in real time through the LWIP network protocol stack. After the measurement is finished, the upper computer can check the file information (measurement time and file size) stored in the EMMC, and provide a download interface to realize data double insurance.
Compared with the traditional acquisition instrument, the data acquisition instrument has the characteristics of small volume, multiple channels, capability of supporting various types of signal input, low power consumption, high sampling frequency, high precision, synchronous acquisition and the like, can be widely applied to vibration, stress, temperature and voltage test occasions in the fields of aviation, aerospace, ships, automobiles, high-speed rails and the like, and has wide application prospect and good economic benefit.
It should be noted that technical features such as analog signals related to the present application should be regarded as the prior art, and specific structures, working principles, and control modes and spatial arrangements possibly related to the technical features should be selected conventionally in the art, and should not be regarded as the invention point of the present application, which is not further specifically described in detail.
Modifications of the embodiments described above, or equivalents of some of the features may be made by those skilled in the art, and any modifications, equivalents, improvements or etc. within the spirit and principles of the present invention are intended to be included within the scope of the present invention.
Claims (2)
1. The acquisition method of the high-speed data acquisition instrument is used for acquiring data and is characterized by comprising the following steps of:
step S1: the data acquisition boards transmit the acquired analog signals to the data processing board, and the data processing board performs data processing on the received analog signals;
Step S1.1: each data acquisition board is provided with a plurality of independent signal input channels so that the data acquisition board can acquire multichannel analog signals;
Step S1.2: each signal input channel transmits the received analog signals to a respective signal source selection circuit to selectively access different kinds of analog signals and transmits the accessed analog signals to a program-controlled amplifying circuit so as to selectively amplify the analog signals;
Step S1.3: the low-pass filter circuit receives the amplified analog signal and performs filter processing on the analog signal by selecting a matched filter gear;
Step S1.4: the single-ended differential circuit receives the filtered analog signals and conditions the analog signals into input ranges and signal types matched with the ADC acquisition units, and the ADC acquisition units perform data acquisition on all current signal input channels so as to ensure high-precision synchronous data acquisition of all signal input channels of each data acquisition board;
Step S1.4 is followed by:
step S1.5: the first processing unit of the data processing board performs data access through interfaces with the number corresponding to the signal input channels, so that a plurality of ADC acquisition units are controlled, data are acquired, and acquired data are cached;
Step S1.6: the second processing unit of the data processing board reads the acquired data cached in the first processing unit and further stores the acquired data so that the second processing unit processes the acquired data;
Step S1.6 is embodied as the following steps:
step S1.6.1: the memory bar of the second processing unit caches the read acquired data, the processor CPU0 stores the acquired data through the memory, and the processor CPU0 is provided with a GPS time service interface so as to connect with a GPS module to complete serial time data analysis and time synchronization;
step S1.6.2: the processor CPU1 communicating with the processor CPU0 is provided with a gigabit Ethernet interface, an antenna interface and a real-time clock interface, wherein:
The gigabit Ethernet interface is used for controlling data acquisition, data checking and data downloading through the Ethernet;
The antenna interface is used for wireless data acquisition control and wireless data receiving and transmitting;
The real-time clock interface is used for realizing the recording of the data acquisition time;
In step S1, buffering data through the ring buffer queue is implemented as the following steps:
T1.1: generating a high-level interrupt after N bytes are fully stored in a FIFO buffer of a first processing unit, so that a buffer space is opened up in a memory bank by a processor CPU1 to serve as a ring buffer queue, and when the processor CPU1 receives the high-level interrupt, starting DMA data transfer once to transfer data in the FIFO buffer to a pointer base address Addr0 of the memory bank;
The CPU1 informs the CPU0 to fetch data from the memory bank pointer base address in an internal interrupt mode, waits for the next interrupt of the FIFO buffer, and circularly stores the data into the address of the memory bank base address after the next interrupt of the FIFO buffer comes;
When the processor CPU0 receives the interrupt, a file is newly built in the memory according to the data acquisition time, acquisition configuration information is written in, then data in the memory bank queue is circularly stored in the file every time the interrupt of the processor CPU1 is received, the processor CPU1 waits for the FIFO interrupt and simultaneously sends the cache data in the memory bank queue to the upper computer through the gigabit Ethernet, and after the acquisition is finished, the upper computer inquires, deletes and downloads the file stored in the memory;
the first processing unit is electrically connected with the plurality of ADC acquisition units through an SPI interface, and the second processing unit comprises a gigabit Ethernet interface, a GPS time service interface, an antenna interface and a power interface;
The information source selection circuit comprises an aviation plug connection unit J1, an analog switch U2 and a constant current source U1, wherein:
the 2 pins of the aviation plug connection unit J1 are electrically connected with the 5 pins of the analog switch U2, the 6 pins of the aviation plug connection unit J1 are electrically connected with the 12 pins of the analog switch U2, and the 10 pins of the aviation plug connection unit J1 are electrically connected with the 10 pins of the analog switch U2;
The information source selection circuit further comprises an operational amplifier U3A, wherein the negative electrode input end of the operational amplifier U3A is electrically connected with the 8 pins of the aviation plug connection unit J1, the output end of the operational amplifier U3A is electrically connected with the 7 pins of the aviation plug connection unit J1, the 3 pins of the aviation plug connection unit J1 are grounded through a resistor R5, a resistor R6 and a resistor R7 in sequence, and the common connection end of the resistor R6 and the resistor R7 is connected with the 5 pins of the aviation plug connection unit J1;
the program-controlled amplifying circuit comprises an amplifier U4, wherein a1 pin of the amplifier U4 is electrically connected with a 9 pin of the analog switch U2 through a resistor R9, a 10 pin of the amplifier U4 is electrically connected with an 8 pin of the analog switch U2 through a resistor R12, a capacitor C8 is connected between the 1 pin and the 10 pin of the amplifier U4, one end of the capacitor C8, which is close to the resistor R9, is grounded through a capacitor C7, and one end of the capacitor C8, which is close to the resistor R12, is grounded through a capacitor C10;
The low-pass filter circuit comprises an operational amplifier U3B and an analog switch U7, wherein:
The 7 pin of the amplifier U4 is electrically connected with the positive input end of the operational amplifier U3B through a resistor R10 and a resistor R11 in sequence;
The common connection end of the resistor R10 and the resistor R11 is electrically connected with the 8 pin of the analog switch U7, the output end of the operational amplifier U3B is electrically connected with the 4 pin of the analog switch U7 through a capacitor C18, and the positive input end of the operational amplifier U3B is electrically connected with the 9 pin of the analog switch U7;
The single-ended to differential circuit comprises a single-ended to differential unit U6, and the output end of the operational amplifier U3B is electrically connected with the positive input end of the single-ended to differential unit U6 through a resistor R14.
2. A high-speed data acquisition instrument for implementing the acquisition method of the high-speed data acquisition instrument of claim 1, comprising a data processing board and a plurality of data acquisition boards, wherein:
The data acquisition boards transmit the acquired analog signals to the data processing board, and the data processing board performs data processing on the received analog signals;
each data acquisition board is provided with a plurality of independent signal input channels so that the data acquisition board can acquire multichannel analog signals;
Each signal input channel transmits the received analog signals to a respective signal source selection circuit to selectively access different kinds of analog signals and transmits the accessed analog signals to a program-controlled amplifying circuit so as to selectively amplify the analog signals;
The low-pass filter circuit receives the amplified analog signal and performs filter processing on the analog signal by selecting a matched filter gear;
The single-ended differential circuit receives the filtered analog signals and conditions the analog signals into input ranges and signal types matched with the ADC acquisition units, and the ADC acquisition units perform data acquisition on all current signal input channels so as to ensure high-precision synchronous data acquisition of all signal input channels of each data acquisition board;
The first processing unit of the data processing board performs data access through interfaces with the number corresponding to the signal input channels, so that a plurality of ADC acquisition units are controlled, data are acquired, and acquired data are cached;
the second processing unit of the data processing board reads the acquired data cached in the first processing unit and further stores the acquired data so that the second processing unit processes the acquired data;
the first processing unit is electrically connected with the plurality of ADC acquisition units through an SPI interface, and the second processing unit comprises a gigabit Ethernet interface, a GPS time service interface, an antenna interface and a power interface;
The information source selection circuit comprises an aviation plug connection unit J1, an analog switch U2 and a constant current source U1, wherein:
the 2 pins of the aviation plug connection unit J1 are electrically connected with the 5 pins of the analog switch U2, the 6 pins of the aviation plug connection unit J1 are electrically connected with the 12 pins of the analog switch U2, and the 10 pins of the aviation plug connection unit J1 are electrically connected with the 10 pins of the analog switch U2;
The information source selection circuit further comprises an operational amplifier U3A, wherein the negative electrode input end of the operational amplifier U3A is electrically connected with the 8 pins of the aviation plug connection unit J1, the output end of the operational amplifier U3A is electrically connected with the 7 pins of the aviation plug connection unit J1, the 3 pins of the aviation plug connection unit J1 are grounded through a resistor R5, a resistor R6 and a resistor R7 in sequence, and the common connection end of the resistor R6 and the resistor R7 is connected with the 5 pins of the aviation plug connection unit J1;
the program-controlled amplifying circuit comprises an amplifier U4, wherein a1 pin of the amplifier U4 is electrically connected with a 9 pin of the analog switch U2 through a resistor R9, a 10 pin of the amplifier U4 is electrically connected with an 8 pin of the analog switch U2 through a resistor R12, a capacitor C8 is connected between the 1 pin and the 10 pin of the amplifier U4, one end of the capacitor C8, which is close to the resistor R9, is grounded through a capacitor C7, and one end of the capacitor C8, which is close to the resistor R12, is grounded through a capacitor C10;
The low-pass filter circuit comprises an operational amplifier U3B and an analog switch U7, wherein:
The 7 pin of the amplifier U4 is electrically connected with the positive input end of the operational amplifier U3B through a resistor R10 and a resistor R11 in sequence;
The common connection end of the resistor R10 and the resistor R11 is electrically connected with the 8 pin of the analog switch U7, the output end of the operational amplifier U3B is electrically connected with the 4 pin of the analog switch U7 through a capacitor C18, and the positive input end of the operational amplifier U3B is electrically connected with the 9 pin of the analog switch U7;
The single-ended to differential circuit comprises a single-ended to differential unit U6, and the output end of the operational amplifier U3B is electrically connected with the positive input end of the single-ended to differential unit U6 through a resistor R14.
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