CN114300542B - Thin film type vertical structure field effect power transistor - Google Patents

Thin film type vertical structure field effect power transistor Download PDF

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CN114300542B
CN114300542B CN202111665642.XA CN202111665642A CN114300542B CN 114300542 B CN114300542 B CN 114300542B CN 202111665642 A CN202111665642 A CN 202111665642A CN 114300542 B CN114300542 B CN 114300542B
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semiconductor layer
type semiconductor
field effect
power transistor
thin film
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CN114300542A (en
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王伟明
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Shanghai Gallium Core Technology Co ltd
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Abstract

The invention relates to a thin film type vertical structure field effect power transistor. The vertical/horizontal composite structure of n-p-n-n is adopted, so that the working voltage is adjustable, and the on-resistance is reduced; and the III-V semiconductor material is used for carrying out energy band engineering design, so that the electron mobility is improved. The invention can meet the requirements of miniaturization and miniaturization of the power electronic module.

Description

Thin film type vertical structure field effect power transistor
Technical Field
The invention relates to a field effect power transistor with a thin film type vertical structure in the field of semiconductors.
Background
The field effect transistor is the basis of an integrated circuit device and comprises the following components according to structural division: metal Oxide Semiconductor Field Effect Transistors (MOSFETs) and metal semiconductor field effect transistors (MESFETs). In the prior art, the MOSFET is mainly applied to high-power devices on the basis of the characteristics of high breakdown voltage and high current density of the MOSFET; in contrast, MESFETs have low parasitics and are often used in high frequency applications. With the development of materials, particularly the application of III-V thin film type semiconductor materials, MESFETs need to have both high power, high carrier mobility and good thermal conductivity. The power type transistor is a core component of power electronics, and can realize voltage and frequency conversion of high-power, including conversion forms of DC-DC, AC-DC, AC-AC and the like and transmission control.
The power type transistor usually works under the working state of large current and high voltage, and has two core technical indexes: 1) an on-resistance; 2) the maximum breakdown voltage. Under the working condition of large current, the on-resistance determines the heat loss of the power transistor, and further determines the efficiency of the whole power conversion and control system; the on-resistance also determines the switching speed of the power transistor, and the volume of passive devices (capacitance and inductance) in the conventional power circuit can be further increased by increasing the switching speed, so that the miniaturization and the miniaturization of a power circuit module are realized. Under the condition of the same device size, the on-resistance is determined by the electron mobility (U) of a semiconductor material, and generally, the smaller the forbidden bandwidth (Eg) of the semiconductor is, the larger the U value is; the maximum breakdown voltage determines the operating voltage range of the power transistor, and is determined by the maximum electric field strength (Ec) that can be borne by the semiconductor material under the same device size condition, and generally, the larger the forbidden bandwidth (Eg) of the semiconductor material is, the higher the Ec value is. Finally, considering practical application requirements such as voltage, frequency variation and transmission of a power supply, the power transistor is required to be in a normally-off mode (i.e. an Enhanced mode with no external control voltage)
Based on the above basic rules, the existing mature power Transistor is a silicon-based Insulated Gate Bipolar Transistor (IGBT), which has low driving power and reduced saturation voltage, and is very suitable for being applied to the fields of current transformation systems with direct current voltage of 600V or more, such as alternating current motors, frequency converters, switching power supplies, lighting circuits, traction drives, and the like. But because the forbidden band width of the silicon material itself is small (Eg ═ 1.1eV), the maximum electric field value Ec borne by the material is low (only 0.2MV/cm), and it is necessary to provide a high operating voltage by increasing the size.
The GaN-based Field Effect Transistor (FET) is a new generation power transistor, and utilizes the large forbidden bandwidth (Eg ═ 3.4eV) of the GaN semiconductor, the maximum electric field Ec that the material can bear can reach 3.3MV/cm, is one order of magnitude higher than that of the silicon material, and is suitable for working in a high voltage environment. Meanwhile, the GaN-based field effect transistor can be communicated with a GaN/AlGaN heterojunction system to obtain a two-dimensional electron gas conducting structure with high mobility, the electron mobility can reach 1500cm2/V.s and is close to that of a silicon material, but the GaN field effect transistor is a planar device and is difficult to realize a normally-off working mode.
The power transistor based on the SiC material has the advantages that the forbidden band width (Eg is 3.0eV), the maximum bearing electric field Ec can reach 2.0MV/cm, the electron mobility is moderate and reaches 650cm2/V.s, a normally-closed working mode can be realized by adopting a standard silicon process, but the SiC is a material with hardness second to that of diamond, the processing difficulty is high, and the substrate cost is high. Manufacturing costs limit its large-scale application.
Disclosure of Invention
The invention aims to provide a field effect power transistor with a thin film type vertical structure. It adopts N-P-N-N type vertical/horizontal composite structure. The invention realizes the purpose through the following technical scheme:
according to an aspect of the present invention, there is provided a thin film type vertical structure field effect power transistor, sequentially arranged from top to bottom, comprising: a first metal, a first N-type semiconductor layer, a first P-type semiconductor layer, a second N-type semiconductor layer, a third N-type semiconductor layer, a fourth N-type semiconductor layer, a fifth N-type semiconductor layer, and a first insulating layerA layer, and a second metal substrate; wherein the first metal is used for connecting with a source electrode; a grid electrode is arranged on one side of the first N-type semiconductor layer, one side of the first P-type semiconductor layer and one side of the second N-type semiconductor layer, and the third N-type semiconductor layer; a second insulating layer is arranged between the grid electrode and the first N-type semiconductor layer, the first P-type semiconductor layer, the second N-type semiconductor layer and the third N-type semiconductor layer, and the second insulating layer is L-shaped; a drain electrode is arranged between the fifth N-type semiconductor layer and the second metal substrate and is positioned on the same layer as the first insulating layer, and the drain electrode is electrically communicated with the fifth N-type semiconductor layer and the second metal substrate; the main composition of the first N-type semiconductor layer is GalnP or Al x Ga (1-x) ln 0.5 P, wherein x<0.5; the main composition of the first P-type semiconductor layer is GalnP or Al x Ga 1-x ln 0.5 P, wherein x<0.5; the second N-type semiconductor layer mainly comprises GalnP or Al x Ga 1-x ln 0.5 P, wherein x<0.5; the third N-type semiconductor layer mainly comprises GalnP or Al x Ga 1-x ln 0.5 P, wherein x<0.5; the main composition of the fourth N-type semiconductor layer is GaAs; the fifth N-type semiconductor layer mainly comprises GalnP or Al x Ga 1-x ln 0.5 P, wherein x<=0.5。
According to the field effect power transistor of the thin film type vertical structure of one embodiment of the present invention, the doping concentration of the first N type semiconductor layer ranges from 2 x 10 18 cm -3 And 5X 10 18 cm -3 In the meantime.
According to the field effect power transistor of the thin film type vertical structure of one embodiment of the present invention, the doping concentration of the first P-type semiconductor layer ranges from 0.5 × 10 18 cm -3 And 1X 10 18 cm -3 In between.
According to the field effect power transistor with the thin film type vertical structure, the doping concentration of the second N type semiconductor layer is less than 1 x 10 17 cm -3
According to the field effect power transistor with the thin film type vertical structure, the doping concentration range of the third N type semiconductor layer is 1 x 10 18 cm -3 And 100X 10 18 cm -3 To (c) to (d); the doping concentration of the fourth N-type semiconductor layer is less than 1 multiplied by 10 17 cm -3
According to the field effect power transistor with the thin film type vertical structure, the doping concentration range of the fifth N type semiconductor layer is 1 x 10 18 cm -3 And 100X 10 18 cm -3 In the meantime.
According to the field effect power transistor with the thin film type vertical structure, the third N type semiconductor layer, the fourth N type semiconductor layer and the fifth N type semiconductor layer are equal in length extending towards the drain electrode.
According to the field effect power transistor of the thin film type vertical structure of one embodiment of the present invention, the first insulating layer is mainly composed of a silicon oxide, silicon nitride, aluminum oxide or ceramic thin film; the second insulating layer mainly comprises silicon oxide, silicon nitride, aluminum oxide or a ceramic film.
According to the field effect power transistor with the thin film type vertical structure, the second metal substrate mainly comprises one or more of gold and silver, and the thickness of the second metal substrate ranges from 10 micrometers to 100 micrometers.
According to the field effect power transistor with the thin film type vertical structure, the first metal mainly comprises one or more of gold, palladium, silver, platinum, aluminum, indium, copper, nickel and titanium, and the thickness of the first metal ranges from 2 micrometers to 3 micrometers.
The invention has the beneficial effects that:
first, a flexible maximum breakdown voltage can be provided by a vertical thin film type structural design of a two-dimensional L-shape.
Secondly, an N-P-N-N type vertical/horizontal composite structure is adopted, so that the transverse on-resistance can be effectively reduced.
Drawings
Fig. 1 is a schematic structural view of a thin film type vertical structure field effect power transistor according to an exemplary embodiment of the present invention;
fig. 2 is a schematic diagram of the electron movement direction of a thin film type vertical structure field effect power transistor according to an exemplary embodiment of the present invention.
Detailed Description
The technical solutions disclosed in the embodiments of the present invention will be briefly, clearly and practically described in relation to those skilled in the art with reference to the accompanying drawings. In particular, the disclosed embodiments are merely partial illustrations of the invention, and those skilled in the art can, without any inventive effort, derive other embodiments from the disclosed embodiments and still fall within the scope of the invention.
Furthermore, the disclosed embodiments are intended to better understand the nature of the invention and do not limit the invention to the described embodiments. The terms "first" and "second" are used to distinguish one description from another, and are not to be construed as indicating or implying a relative order, or order, of importance. In the description of the embodiments, the concepts of the semiconductor thin film layer upper surface, the semiconductor thin film layer lower surface, and the like are employed. It should be understood that the terms "upper" and "lower" are used herein with respect to the metal substrate of the present invention, i.e., "upper" refers to the side away from the metal substrate and "lower" refers to the side closer to the metal substrate.
The technical solution of the present invention will be described in detail by the examples disclosed below. In embodiments, other embodiments will not be described again after the same or similar concepts are set forth.
The invention provides a thin film type vertical structure field effect power transistor. The high electron mobility of the III-V semiconductor is utilized, and the mobility can reach 7000cm 2 (iv) v.s; moderate forbidden band width (Eg range is 1.9 eV-2.2 eV), excellent heat conduction performance of the film-shaped device (the thickness of the device is less than 10 microns); through energy band engineering design, a vertical/horizontal composite structure of n-p-n-n is adopted to realize 650-1000V-level working voltage and low on-resistanceAnd extremely small leakage current, and can operate in normally off mode (Enhanced mode). Compared with Si, GaN and SiC material systems, the silicon-based high-power-density silicon-based low-voltage power electronic module has the advantages of lower on resistance, faster switching frequency, lower manufacturing cost and higher current density, and meets the requirements of miniaturization and miniaturization of the power electronic module.
As shown in fig. 1, an embodiment 100 of the field effect power transistor with thin film type vertical structure according to the present invention has a structure that sequentially includes, from top to bottom, a first metal 101 mainly composed of one or more of gold, palladium, silver, platinum, aluminum, indium, copper, nickel, and titanium, and having a thickness ranging from 2 μm to 3 μm, for connecting to a source.
A first N-type semiconductor layer 102 as a source region layer of a vertical structure; and is connected with the source electrode through the metal 101. The main component of the alloy can be GalnP or Al x Ga (1-x) ln 0.5 P, wherein x<0.5; with a lattice constant of 0.5653nm and a doping concentration in the range of 2 × 10 18 cm -3 And 5X 10 18 cm -3 In (scientific notation, powers of 10 are denoted by e).
The first P-type semiconductor layer 103 may have a main composition of GalnP or Al x Ga 1-x ln 0.5 P, wherein, x<0.5, lattice constant 0.5653nm, and doping concentration in the range of 0.5 × 10 18 And 1X 10 18 cm -3 And the thickness of the gate is 0.5-3 microns, the gate is used as a gate region of a vertical structure, and the gate voltage is controlled through a lateral insulating layer material.
The second N-type semiconductor layer 104 may be GalnP or Al as a main component x Ga 1-x ln 0.5 P,x<0.5, lattice constant 0.5653nm, doping concentration less than 1 × 10 17 cm -3 And the thickness is 3-10 microns, and the vertical structure is used as a drain region (drain region) of the vertical structure. By applying a voltage V between source 101 and gate 111 during regulation GS The first N-type semiconductor layer 102 of the source region and the second N-type semiconductor layer 104 of the source region are electrically connected. Specifically, when V GS When the value is 0, an NPN structure is formed between the first metal 101 communicated with the source and the drain 110, and no conductive channel exists; when V is GS >0 (i.e., when a positive voltage is applied to the gate electrode), the positive charges at the interface between the first P-type semiconductor layer 103 and the insulating layer 112 begin to leave the interface under the action of an electric field, forming a high-resistance depletion region when V is applied GS When the amount is further increased, the interface between the first P-type semiconductor layer 103 and the insulating layer 112 begins to invert, and electrons are accumulated at the interface to form a conductive channel, V GS The larger the conducting channel, the stronger the conducting capacity, thus forming a voltage-controlled current working model.
A gate electrode 111 is provided on the third N-type semiconductor layer 105; a second insulating layer 112 having an L-shape is disposed between the first N-type semiconductor layer 102, the first P-type semiconductor layer 103, the second N-type semiconductor layer 104, and the gate electrode 111. As shown in fig. 1, the second insulating layer 112 has an L-shape, which means a two-dimensional pattern having an L-shape in cross section. The main composition of the insulating layer 112 may be silicon oxide, silicon nitride, aluminum oxide, ceramic film or other organic polymer material.
A third N-type semiconductor layer 105 disposed below the L-shaped second insulating layer 112 and mainly composed of GalnP or Al x Ga 1-x ln 0.5 P,x<0.5, lattice constant 0.5653nm, doping concentration range of 1 × 10 18 cm -3 And 100X 10 18 cm -3 And the thickness of the conductive layer is 0.3-1 micron, and the conductive layer is used as an electronic limiting layer for transverse conduction.
A fourth N-type semiconductor layer 106 consisting essentially of GaAs with a lattice constant of 0.5653nm and a doping concentration of less than 1 × 10 17 cm -3 And the thickness is 0.3-3 microns, and the film is used as an electron transport layer for transverse conduction.
The fifth N-type semiconductor layer 107 may have a main composition of GalnP or Al x Ga 1-x ln 0.5 P,x<0.5, lattice constant 0.5653nm, doping concentration range of 1 × 10 18 cm -3 And 100X 10 18 cm -3 And the thickness of the conductive layer is 0.3-1 micron, and the conductive layer is used as an electronic limiting layer for transverse conduction. A first insulating layer 108 is disposed between the fifth N-type semiconductor layer 107 and the metal substrate 109. The main component of the insulating layer 108 can be silicon oxide, silicon nitride, aluminum oxide, ceramic film or other organic polymer materialThe thickness of the material is 1-3 microns.
The lateral conduction distance L can be set according to the operating voltage to which the transport is subjected. Between the fifth N-type semiconductor layer 107 and the metal substrate 109, a drain electrode 110 is disposed in parallel with the first insulating layer 108, and the fifth N-type semiconductor layer 107, the metal substrate 109 and the drain electrode 110 are electrically connected.
The metal substrate 109 is made of a metal material having high electrical and thermal conductivity, such as copper, silver, or an alloy, and has a thickness controlled to be between 10 and 100 micrometers.
Fig. 2 shows a schematic diagram of the electron movement direction in the embodiment 100. The maximum bearable electric field of the GalnP semiconductor is 1MV/cm, and in order to bear 1000V of working voltage, the thickness D of the second N-type semiconductor layer 104 needs to be 10 micrometers; in order to further increase the voltage, the thickness of the second N-type semiconductor layer 104 may be further increased, or the lengths of the third N-type semiconductor layer 105, the fourth N-type semiconductor layer 106, and the fifth N-type semiconductor layer 107 extending toward the drain electrode 110 may be equal to each other. Preferably, the fourth N-type semiconductor layer 106 and the fifth N-type semiconductor layer 107 have the same length extending toward the drain electrode 110. The tolerable maximum electric field of the GaAs semiconductor is 0.4MV/cm if lateral expansion of the third N-type semiconductor layer 105, the fourth N-type semiconductor layer 106, and the fifth N-type semiconductor layer 107 is adjustable; if the extension is 10 microns, the voltage of 400V can be increased. In this structure, D and L are both 10 μm, and the cumulative withstanding voltage is 1400V.
The device structure of the invention provides a design mode for flexibly adjusting the highest bearing voltage, and a quasi-two-dimensional electron gas structure is formed by a double-heterojunction structure of GalnP/GaAs/GalnP, so that the electron mobility of a GaAs layer is further improved, and the transverse on-resistance is reduced.
The above embodiments are only preferred embodiments of the present invention, and are not intended to limit the technical solutions of the present invention. Without departing from the spirit of the invention, the present invention shall be deemed to fall within the scope of the claims of the present patent application by the following claims and their equivalents.

Claims (10)

1. A field effect power transistor of a thin film type vertical structure is characterized in that the field effect power transistor comprises the following components in sequence from top to bottom:
a first metal, a second metal, a third metal,
a first N-type semiconductor layer formed on the substrate,
a first P-type semiconductor layer formed on the substrate,
a second N-type semiconductor layer formed on the substrate,
a third N-type semiconductor layer formed on the substrate,
a fourth N-type semiconductor layer formed on the substrate,
a fifth N-type semiconductor layer formed on the substrate,
a first insulating layer, and,
a second metal substrate; wherein,
the first metal is used for connecting with a source electrode;
a grid electrode is arranged on one side of the first N-type semiconductor layer, one side of the first P-type semiconductor layer and one side of the second N-type semiconductor layer, and the third N-type semiconductor layer;
a second insulating layer is arranged between the grid electrode and the first N-type semiconductor layer, the first P-type semiconductor layer, the second N-type semiconductor layer and the third N-type semiconductor layer, and the second insulating layer is L-shaped;
a drain electrode is arranged between the fifth N-type semiconductor layer and the second metal substrate and is positioned on the same layer as the first insulating layer, and the drain electrode is electrically communicated with the fifth N-type semiconductor layer and the second metal substrate;
the main composition of the first N-type semiconductor layer is GalnP or Al x Ga (1-x) ln 0.5 P, wherein x<=0.5;
The main composition of the first P-type semiconductor layer is GalnP or Al x Ga 1-x ln 0.5 P, wherein x<=0.5;
The second N-type semiconductor layer mainly comprises GalnP or Al x Ga 1-x ln 0.5 P, wherein x<=0.5;
The third N-type semiconductor layer mainly comprises GalnP or Al x Ga 1-x ln 0.5 P, wherein x<=0.5;
The main composition of the fourth N-type semiconductor layer is GaAs;
the fifth N-type semiconductor layer mainly comprises GalnP or Al x Ga 1-x ln 0.5 P, wherein x<=0.5。
2. The thin film vertical structure field effect power transistor of claim 1, wherein: the doping concentration range of the first N-type semiconductor layer is 2 multiplied by 10 18 cm -3 And 5X 10 18 cm -3 In the meantime.
3. The thin film vertical structure field effect power transistor of claim 2, wherein: the doping concentration range of the first P-type semiconductor layer is 0.5 multiplied by 10 18 cm -3 And 1X 10 18 cm -3 In the meantime.
4. The thin film vertical structure field effect power transistor of claim 3, wherein: the doping concentration of the second N-type semiconductor layer is less than 1 x 10 17 cm -3
5. The thin film vertical structure field effect power transistor of claim 4, wherein: the doping concentration range of the third N-type semiconductor layer is 1 multiplied by 10 18 cm -3 And 100 x 10 18 cm -3 To (c) to (d); the doping concentration of the fourth N-type semiconductor layer is less than 1 multiplied by 10 17 cm -3
6. The thin film vertical structure field effect power transistor of claim 5, wherein: the doping concentration range of the fifth N-type semiconductor layer is 1 x 10 18 cm -3 And 100X 10 18 cm -3 In the meantime.
7. The thin film type vertical structure field effect power transistor according to any one of claims 1 to 6, wherein: the third N-type semiconductor layer, the fourth N-type semiconductor layer and the fifth N-type semiconductor layer have the same length extending towards the drain electrode.
8. The thin film type vertical structure field effect power transistor according to claim 7, characterized in that: the first insulating layer mainly comprises silicon oxide, silicon nitride, aluminum oxide or a ceramic film; the second insulating layer mainly comprises silicon oxide, silicon nitride, aluminum oxide or a ceramic film.
9. The thin film vertical structure field effect power transistor of claim 8, wherein: the second metal substrate mainly comprises one or more of gold and silver, and the thickness range of the second metal substrate is 10-100 mu m.
10. The thin film vertical structure field effect power transistor of claim 9, wherein: the main composition of the first metal is one or more of gold, palladium, silver, platinum, aluminum, indium, copper, nickel and titanium, and the thickness range of the first metal is 2-3 mu m.
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CN103426910A (en) * 2012-05-24 2013-12-04 杰力科技股份有限公司 Power semiconductor element and edge termination structure thereof
CN103633139A (en) * 2012-08-23 2014-03-12 联华电子股份有限公司 High-voltage metal oxide semiconductor transistor element

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US7019344B2 (en) * 2004-06-03 2006-03-28 Ranbir Singh Lateral drift vertical metal-insulator semiconductor field effect transistor
TWI256134B (en) * 2005-04-21 2006-06-01 Pyramis Holding Ltd Power semiconductor device with L-shaped source region
US7335943B2 (en) * 2005-05-06 2008-02-26 Atmel Corporation Ultrascalable vertical MOS transistor with planar contacts
CN103151391B (en) * 2013-03-18 2015-08-12 北京大学 The short grid tunneling field-effect transistor of vertical non-uniform doped channel and preparation method

Patent Citations (3)

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Publication number Priority date Publication date Assignee Title
CN101924139A (en) * 2010-06-25 2010-12-22 北京大学 Strain channel field-effect transistor and preparation method thereof
CN103426910A (en) * 2012-05-24 2013-12-04 杰力科技股份有限公司 Power semiconductor element and edge termination structure thereof
CN103633139A (en) * 2012-08-23 2014-03-12 联华电子股份有限公司 High-voltage metal oxide semiconductor transistor element

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