CN114300529A - Semiconductor structure and preparation method thereof - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 120
- 238000002360 preparation method Methods 0.000 title claims description 10
- 230000007480 spreading Effects 0.000 claims abstract description 109
- 238000003892 spreading Methods 0.000 claims abstract description 109
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims abstract description 8
- 229910044991 metal oxide Inorganic materials 0.000 claims description 9
- 150000004706 metal oxides Chemical class 0.000 claims description 9
- 230000004888 barrier function Effects 0.000 claims description 8
- 230000005669 field effect Effects 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 239000002184 metal Substances 0.000 description 12
- 238000010586 diagram Methods 0.000 description 8
- 230000015556 catabolic process Effects 0.000 description 6
- 150000002500 ions Chemical class 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 238000011084 recovery Methods 0.000 description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 4
- 230000005684 electric field Effects 0.000 description 3
- 229910010271 silicon carbide Inorganic materials 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- -1 phosphorus ions Chemical class 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
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Abstract
A semiconductor structure and a method for fabricating the same, the semiconductor structure comprising: a semiconductor substrate layer; a drift layer on the semiconductor substrate layer; a lateral current spreading layer in the drift layer, the lateral current spreading layer having a same conductivity type as the drift layer, the lateral current spreading layer having a doping concentration greater than the doping concentration of the drift layer; and the active doped region is positioned in the top region of the drift layer and at least positioned above part of the transverse current expansion layer, and the conductivity type of the active doped region is opposite to that of the drift layer. The forward on-resistance of the semiconductor structure is reduced.
Description
Technical Field
The invention relates to the field of semiconductors, in particular to a semiconductor structure and a preparation method thereof.
Background
Common power semiconductor structures include power diodes, vertical metal oxide semiconductor field effect transistors, or insulated gate bipolar transistors.
Among them, the power diode is one of the most commonly used electronic components, and is the most basic constituent unit of power electronic circuit, and its unidirectional conductivity can be used for rectification, clamping and free-wheeling of circuit. The diode in the peripheral circuit mainly plays a role in preventing reverse connection, and prevents the device from being damaged due to reverse current flowing. Conventional power diodes mainly include schottky power diodes (SBDs) and PN junction power diodes. Compared with PN junction power diodes, schottky power diodes utilize metal-to-semiconductor contacts (gold-to-half contacts) to form metal-semiconductor junctions, making their forward turn-on voltage smaller. Furthermore, schottky power diodes are unipolar majority carrier conduction mechanisms, with reverse recovery times ideally zero, without accumulation of excess minority carriers. The Schottky power diode has the characteristics of low conduction voltage drop, good switching characteristic, small reverse recovery current and the like. However, the reverse blocking characteristic of the schottky power diode is poor, and the leakage current is large at high temperature and reverse high voltage. The PN junction power diode has good reverse blocking characteristics, but has higher forward conduction voltage drop than a Schottky power diode, long reverse recovery time, large recovery current and larger energy consumption. Junction Barrier Schottky Diode (JBS) combines Schottky power Diode (SBD) and PN Junction power Diode together, and can shield the surface electric field of Schottky contact region by introducing P-type region, and can realize higher reverse characteristic breakdown characteristic and forward surge performance.
However, the forward on-resistance of the conventional power semiconductor structure still needs to be further reduced.
Disclosure of Invention
The invention aims to solve the technical problem that the forward on-resistance of the semiconductor structure in the prior art needs to be further reduced.
In order to solve the above technical problem, the present invention provides a semiconductor structure, comprising: a semiconductor substrate layer; a drift layer on the semiconductor substrate layer; a lateral current spreading layer in the drift layer, the lateral current spreading layer having a same conductivity type as the drift layer, the lateral current spreading layer having a doping concentration greater than the doping concentration of the drift layer; and the active doped region is positioned in the top region of the drift layer and at least positioned above part of the transverse current expansion layer, and the conductivity type of the active doped region is opposite to that of the drift layer.
Optionally, the doping concentration of the lateral current spreading layer is less than the doping concentration of the active doping region.
Optionally, the doping concentration of the lateral current spreading layer is 1E15atom/cm3～5E20atom/cm3The doping concentration of the drift layer is 1E14atom/cm3～1E17atom/cm3The doping concentration of the active doping region is 1E17atom/cm3～5E20atom/cm3。
Optionally, the lateral current spreading layer is located at the bottom of the active doped region and spaced apart from the active doped region.
Optionally, a distance between the bottom surface of the active doped region and the top surface of the lateral current spreading layer is less than or equal to 2 um.
Optionally, the lateral current spreading layer is adjacent to the active doped region.
Optionally, a lateral dimension of the lateral current spreading layer is larger than a lateral dimension of the active doped region.
Optionally, the difference between the lateral dimension of the lateral current spreading layer and the lateral dimension of the active doped region is 0.1um to 3 um.
Optionally, the number of the active doping regions is several, the active doping regions are separately arranged, and the lateral current spreading layers at the bottoms of the adjacent active doping regions are connected together.
Optionally, a lateral dimension of the lateral current spreading layer is smaller than or equal to a lateral dimension of the active doped region.
Optionally, the thickness of the lateral current spreading layer is 0.1um to 3 um.
Optionally, the semiconductor structure is a junction barrier schottky diode; the semiconductor structure further includes: an anode layer over the drift layer and the active doped region; or the semiconductor structure is a vertical metal oxide semiconductor or an insulated gate bipolar transistor, and the active doped region is used as a well region.
The invention also provides a preparation method of the semiconductor structure, which comprises the following steps: providing a semiconductor substrate layer; forming a drift layer on the semiconductor substrate layer; forming a lateral current spreading layer in the drift layer, wherein the conductivity type of the lateral current spreading layer is the same as that of the drift layer, and the doping concentration of the lateral current spreading layer is greater than that of the drift layer; and forming an active doped region in the drift layer at the top region, wherein the active doped region is at least positioned above part of the transverse current expansion layer, and the conductivity type of the active doped region is opposite to that of the drift layer.
Optionally, the semiconductor structure is a junction barrier schottky diode, and the method for manufacturing the semiconductor structure further includes: forming an anode layer on the drift layer and the active doped region; or, the semiconductor structure is a vertical metal oxide semiconductor field effect transistor or an insulated gate bipolar transistor, and the preparation method of the semiconductor structure further comprises the following steps: forming a gate structure on the drift layer after forming the active doped region; the active doped region is used as a well region; the well region is positioned at two sides of the grid structure; forming an ohmic contact body doping area in the well area, wherein the conductivity type of the ohmic contact body doping area is the same as that of the well area; when the semiconductor structure is a vertical metal oxide semiconductor field effect transistor, the preparation method of the semiconductor structure further comprises the following steps: forming a source region in the well region, wherein the conductivity type of the source region is the same as that of the drift layer; when the semiconductor structure is an insulated gate bipolar transistor, the preparation method of the semiconductor structure further comprises the following steps: and forming an emission region in the well region, wherein the conductivity type of the emission region is the same as that of the drift layer.
The technical method of the invention has the following beneficial effects:
according to the semiconductor structure provided by the technical scheme of the invention, when the semiconductor structure is conducted in the forward direction, current flows to the bottom of the active doping region and the transverse current expansion layer adjacent to the active doping region along the drift layer adjacent to the side part of the active doping region and the active doping region, and then is conducted towards the direction of the semiconductor substrate layer. The lateral current spreading layer is arranged at the bottom of the active doped region, and the doping concentration of the lateral current spreading layer is greater than that of the drift layer, so that the width of a depletion layer formed by the active doped region and the lateral current spreading layer is narrowed, the depletion layer is formed in the middle of the lateral current spreading, and the doping concentration of a region at the bottom of the depletion layer in the lateral current spreading is relatively higher, so that current can be quickly spread to the lateral current spreading layer along the side part of the active doped region, the forward conduction characteristic is improved, and the forward conduction resistance is reduced.
Furthermore, the doping concentration of the transverse current expansion layer is smaller than that of the active doping area, so that the doping concentration of the transverse current expansion layer is not too large, and the influence on the reverse breakdown voltage of the semiconductor structure is avoided being too large.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts;
FIG. 1 is a schematic diagram of a semiconductor structure in embodiment 1 of the present invention;
FIG. 2 is a schematic diagram of a semiconductor structure according to embodiment 2 of the present invention;
FIG. 3 is a schematic diagram of a semiconductor structure according to embodiment 3 of the present invention;
FIG. 4 is a schematic diagram of a semiconductor structure according to embodiment 4 of the present invention;
FIG. 5 is a schematic diagram of a semiconductor structure according to embodiment 5 of the present invention;
fig. 6 is a schematic view of a semiconductor structure according to embodiment 6 of the present invention;
FIG. 7 is a schematic diagram of a semiconductor structure according to embodiment 7 of the present invention;
FIG. 8 is a schematic diagram of a semiconductor structure according to embodiment 8 of the present invention;
fig. 9 is a schematic view of a semiconductor structure in embodiment 9 of the present invention;
fig. 10 is a schematic diagram of a semiconductor structure in embodiment 10 of the invention.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
Example 1
The present invention provides a semiconductor structure, referring to fig. 1, comprising:
a semiconductor substrate layer 100;
a drift layer 120 on the semiconductor substrate layer 100;
a lateral current spreading layer 130 in the drift layer 120, a conductivity type of the lateral current spreading layer 130 being the same as a conductivity type of the drift layer 120, a doping concentration of the lateral current spreading layer 130 being greater than a doping concentration of the drift layer 120;
an active doped region 140 located in a top region of the drift layer 120, the active doped region 140 being located at least above a portion of the lateral current spreading layer 130, the active doped region 140 having a conductivity type opposite to that of the drift layer 120.
In this embodiment, a semiconductor structure is exemplified as a SiC-based semiconductor structure, and accordingly, the semiconductor substrate layer 100 is silicon carbide (SiC) doped with conductive ions. A new generation of semiconductor devices represented by SiC has higher reverse withstand voltage capability, lower forward conduction loss, faster switching frequency, and stronger environmental tolerance, and is therefore considered as a new hope in the field of electric energy conversion. In this embodiment, the material of the semiconductor substrate layer 100 is not limited.
In this embodiment, the drift layer 120 is doped with N-type conductive ions, and the material of the drift layer 120 is silicon carbide doped with N-type conductive ions. It should be noted that, in other embodiments, the material of the drift layer may also be other materials. The N-type conductive ions may be phosphorus ions or nitrogen ions.
The number of the active doped regions 140 may be several, and several active doped regions 140 are separately disposed.
The conductivity type of the lateral current spreading layer 130 is N-type, and the conductivity type of the active doped region 140 is P-type.
In the semiconductor structure of the present embodiment, when conducting in the forward direction, the current flows through the drift layer 120 along the side of the active doped region 140 and adjacent to the active doped region 140 to the bottom of the active doped region 140 and the lateral current spreading layer 130 adjacent to the active doped region 140, and then conducts toward the semiconductor substrate layer 100. Since the lateral current spreading layer 130 is disposed at the bottom of the active doped region 140, and the doping concentration of the lateral current spreading layer 130 is greater than that of the drift layer 120, so that the width of a depletion layer formed by the active doped region 140 and the lateral current spreading layer 130 is narrowed, the depletion layer is partially formed in the lateral current spreading layer 130, and the doping concentration of a region of the lateral current spreading layer 130 located at the bottom of the depletion layer is relatively high, so that a current can quickly spread toward the lateral current spreading layer 130 along the side portion of the active doped region 140, thereby improving the forward conduction characteristic of the semiconductor structure and reducing the forward conduction resistance of the semiconductor structure.
In one embodiment, the doping concentration of the lateral current spreading layer 130 is less than the doping concentration of the active doped region 140, so that the doping concentration of the lateral current spreading layer 130 is not too high, and the reverse breakdown voltage of the semiconductor structure is not affected too much.
Preferably, in a specific embodiment, the doping concentration of the lateral current spreading layer 130 is greater than or equal to 10 times the doping concentration of the drift layer 120 and less than or equal to 50% of the doping concentration of the active doped region 140.
In a specific embodiment, the doping concentration of the lateral current spreading layer 130 is 1E15atom/cm3～5E20atom/cm3For example 1E17atom/cm3(ii) a The doping concentration of the drift layer 120 is 1E14atom/cm3～1E17atom/cm3For example 1E16atom/cm3(ii) a The doping concentration of the active doping region 140 is 1E17atom/cm3～5E20atom/cm3For example 1E18atom/cm3。
In the present embodiment, the lateral current spreading layer 130 is adjacent to the active doped region 140 (refer to fig. 1). Has the advantages that: the lateral current spreading layer 130 stops the active doped region 140 from being depleted towards the lower layer, and can better play the role of reducing the resistance by lateral current spreading when conducting in the forward direction.
In one embodiment, the thickness of the lateral current spreading layer 130 is 0.1um to 3 um. If the thickness of the lateral current spreading layer 130 is too large, the reverse withstand voltage characteristic of the device will be greatly affected; if the thickness of the lateral current spreading layer 130 is excessively small, the effect of lateral current spreading is reduced.
In this embodiment, the lateral dimension of the lateral current spreading layer 130 is greater than the lateral dimension of the active doped region 140. This has the advantages that: the lateral dimension of the lateral current spreading layer 130 is larger than the lateral dimension of the active doped region 140, so that the lateral current spreading capability is improved, the forward conduction characteristic is further improved, and the forward conduction resistance is further reduced. In this embodiment, the lateral current spreading layers 130 at the bottom of the adjacent active doped regions 140 are not connected together, so as to avoid the lateral current spreading layers 130 from having an enhanced influence on the electric field at the surface of the drift layer 120 between the adjacent active doped regions 140, and avoid the reverse breakdown voltage from being reduced.
Preferably, the difference between the lateral dimension of the lateral current spreading layer 130 and the lateral dimension of the active doped region is 0.1um to 3 um. This allows for optimization of the forward conduction characteristic and the reverse breakdown characteristic, and the lateral current spreading layer 130 preferably allows for reduction of the forward conduction resistance and does not greatly affect the electric field of the surface of the drift layer 120 between the adjacent active doped regions 140.
In this embodiment, the doping concentration of the lateral current spreading layer is limited, the thickness of the lateral current spreading layer is limited, and the lateral dimension of the lateral current spreading layer is greater than the lateral dimension of the active doping region, so that the forward conduction characteristic is better improved, the forward conduction resistance is better reduced, and the influence on the reverse breakdown voltage of the semiconductor structure is smaller.
Example 2
This example differs from example 1 in that: referring to fig. 2, the lateral current spreading layer 130a is located at the bottom of the active doped region 140 and spaced apart from the active doped region 140.
The doping condition and lateral dimensions and thickness of the lateral current spreading layer 130a are described with reference to the lateral current spreading layer 130 in embodiment 1.
In one embodiment, the distance between the bottom surface of the active doped region 140 and the top surface of the lateral current spreading layer 130a is less than or equal to 2 um. This has the advantages that: the bottom surface of the active doped region 140 is spaced apart from the top surface of the lateral current spreading layer 130a, so that the lateral current spreading layer 130a is not depleted by contact with the active doped region 140, and lateral spreading of current is achieved without high doping.
In a specific embodiment, the distance between the bottom surface of the active doped region 140 and the top surface of the lateral current spreading layer 130a is less than or equal to 0.5 um.
Other parts of this embodiment that are the same as those of embodiment 1 will not be described in detail.
Example 3
This example differs from example 1 in that: referring to fig. 3, the lateral current spreading layers 130b at the bottom of adjacent active doped regions 140 are connected together.
The doping condition and thickness of the lateral current spreading layer 130b are described with reference to the lateral current spreading layer 130 in embodiment 1.
Other parts of this embodiment that are the same as those of embodiment 1 will not be described in detail.
Example 4
This example differs from example 1 in that: referring to fig. 4, the lateral dimension of the lateral current spreading layer 130c is smaller than the lateral dimension of the active doped region 140.
Other parts of this embodiment that are the same as those of embodiment 1 will not be described in detail.
Example 5
This example differs from example 1 in that: referring to fig. 5, the lateral dimension of the lateral current spreading layer 130d is equal to the lateral dimension of the active doped region 140.
Other parts of this embodiment that are the same as those of embodiment 1 will not be described in detail.
Example 6
This example differs from example 2 in that: referring to fig. 6, the lateral current spreading layers 130e at the bottom of adjacent active doped regions 140 are connected together.
Example 7
The difference between this embodiment and embodiment 2 is that: referring to fig. 7, the lateral dimension of the lateral current spreading layer 130f is smaller than the lateral dimension of the active doped region 140.
Example 8
The difference between this embodiment and embodiment 2 is that: referring to fig. 8, the lateral dimension of the lateral current spreading layer 130g is equal to the lateral dimension of the active doped region 140.
Example 9
This embodiment provides a semiconductor structure, the semiconductor structure is a junction barrier schottky diode, and referring to fig. 9, the semiconductor structure further includes: a semiconductor substrate layer 100; a drift layer 120 on the semiconductor substrate layer 100; a lateral current spreading layer 130h in the drift layer 120, a conductivity type of the lateral current spreading layer 130h being the same as a conductivity type of the drift layer 120, a doping concentration of the lateral current spreading layer 130h being greater than a doping concentration of the drift layer 120; an active doped region 140 located in a top region of the drift layer 120, the active doped region 140 being located at least above a portion of the lateral current spreading layer 130h, the active doped region 140 having a conductivity type opposite to that of the drift layer 120; an anode layer 150 on the drift layer 120 and the active doped region 140; an ohmic contact layer 160 on a side of the semiconductor substrate layer 100 facing away from the drift layer 120.
In this embodiment, the lateral dimension of the lateral current spreading layer 130h is larger than the active doped region 140, and the lateral current spreading layer 130h is adjacent to the active doped region 140. When the semiconductor structure is a junction barrier schottky diode, any one of the lateral current spreading layers in embodiments 1 to 8 can be used as the lateral current spreading layer.
Example 10
The present embodiment provides a semiconductor structure, referring to fig. 10, the semiconductor structure is a vertical metal oxide semiconductor field effect transistor, and the semiconductor structure further includes: a semiconductor substrate layer 100; a drift layer 120 on the semiconductor substrate layer 100; a lateral current spreading layer 130k in the drift layer 120, a conductivity type of the lateral current spreading layer 130k being the same as a conductivity type of the drift layer 120, a doping concentration of the lateral current spreading layer 130k being greater than a doping concentration of the drift layer 120; an active doped region 240 located in a top region of the drift layer 120, the active doped region 240 serving as a well region, the active doped region 240 being located at least above a portion of the lateral current spreading layer 130k, the conductivity type of the active doped region 240 being opposite to the conductivity type of the drift layer 120; a gate structure 260 on the drift layer 120; the well region 240 is located at two sides of the gate structure 260; a source region 250 located in the well region 240, a conductivity type of the source region 250 being the same as a conductivity type of the drift layer 120; an ohmic contact doping region 251 located in the well region 240, wherein the conductivity type of the ohmic contact doping region 251 is the same as that of the well region 240, and the doping concentration of the ohmic contact doping region 251 is greater than that of the well region 240; a source metal region 252 located on the source region 250 and the ohmic contact doping region 251, the source metal region 252 forming an ohmic contact with the source region 250 and the ohmic contact doping region 251; and the drain metal region 160b is positioned on the side of the semiconductor substrate layer 100, which faces away from the drift layer 120.
The gate structure 260 also covers a portion of the well region 240. The gate structure 260 includes: a gate dielectric layer on the drift layer 120; and the gate electrode layer is positioned on the gate dielectric layer.
In this embodiment, the lateral dimension of the lateral current spreading layer 130k is larger than the active doped region 240, and the lateral current spreading layer 130k is adjacent to the active doped region 240. When the semiconductor structure is a vertical mosfet, any one of the lateral current spreading layers in embodiments 1 to 8 can be used as the lateral current spreading layer.
Example 11
The embodiment provides a semiconductor structure which is an insulated gate bipolar transistor.
The present embodiment differs from the semiconductor structure of embodiment 10 in that the source region 250 is replaced with an emitter region; replacing the source metal region 252 with an emitter metal region and the drain metal region 160b with a collector metal region, further comprising: the P-type layer is positioned on the surface of one side, back to the drift layer, of the semiconductor substrate layer; the collector metal region is located on one side of the P-type layer, which faces away from the drift layer.
Example 12
The embodiment also provides a method for manufacturing a semiconductor structure, which includes: providing a semiconductor substrate layer; forming a drift layer on the semiconductor substrate layer; forming a lateral current spreading layer in the drift layer, wherein the conductivity type of the lateral current spreading layer is the same as that of the drift layer, and the doping concentration of the lateral current spreading layer is greater than that of the drift layer; and forming an active doped region in the top region of the drift layer, wherein the active doped region is at least positioned above part of the transverse current expansion layer, the conductivity type of the active doped region is opposite to that of the drift layer, and the doping concentration of the active doped region is higher than that of the transverse current expansion layer.
The detailed description of the lateral current spreading layer refers to the description in embodiment 1 to embodiment 8.
In one embodiment, the semiconductor structure is a junction barrier schottky diode, and the method for manufacturing the semiconductor structure further comprises: forming an anode layer on the drift layer and the active doped region; and forming an ohmic contact layer on one side of the semiconductor substrate layer, which is far away from the drift layer.
In one embodiment, the semiconductor structure is a vertical metal oxide semiconductor field effect transistor or an insulated gate bipolar transistor, and the method for manufacturing the semiconductor structure further includes: forming a gate structure on the drift layer after forming the active doped region; the active doped region is used as a well region; the well region is positioned at two sides of the grid structure; forming a source region in the well region, wherein the conductivity type of the source region is the same as that of the drift layer; an ohmic contact doping region in the well region, the ohmic contact doping region having a conductivity type the same as the conductivity type of the well region; forming a source metal area on the source area and the ohmic contact body doping area; and forming a drain metal region on one side of the semiconductor substrate layer, which is far away from the drift layer.
In one embodiment, the semiconductor structure is an insulated gate bipolar transistor, and the method for manufacturing the semiconductor structure further includes: forming a gate structure on the drift layer after forming the active doped region; the active doped region is used as a well region; the well region is positioned at two sides of the grid structure; forming an emitting region in the well region, wherein the conductivity type of the emitting region is the same as that of the drift layer; forming an ohmic contact body doping area in the well area, wherein the conductivity type of the ohmic contact body doping area is the same as that of the well area; forming an emitter metal region on the emitter region and the ohmic contact doping region; forming a P-type layer on one side of the semiconductor substrate layer, which is far away from the drift layer; and forming a collector metal region on one side of the P-type layer, which is far away from the drift layer.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are within the scope of the invention.
Claims (10)
1. A semiconductor structure, comprising:
a semiconductor substrate layer;
a drift layer on the semiconductor substrate layer;
a lateral current spreading layer in the drift layer, the lateral current spreading layer having a same conductivity type as the drift layer, the lateral current spreading layer having a doping concentration greater than the doping concentration of the drift layer;
and the active doped region is positioned in the top region of the drift layer and at least positioned above part of the transverse current expansion layer, and the conductivity type of the active doped region is opposite to that of the drift layer.
2. The semiconductor structure of claim 1, wherein a doping concentration of the lateral current spreading layer is less than a doping concentration of the active doped region;
preferably, the doping concentration of the transverse current spreading layer is 1E15atom/cm3～5E20atom/cm3The doping concentration of the drift layer is 1E14atom/cm3～1E17atom/cm3The doping concentration of the active doping region is 1E17atom/cm3～5E20atom/cm3。
3. The semiconductor structure of claim 1, wherein the lateral current spreading layer is located at a bottom of the active doped region and spaced apart from the active doped region;
preferably, the distance between the bottom surface of the active doped region and the top surface of the lateral current spreading layer is less than or equal to 2 um.
4. The semiconductor structure of claim 1, wherein the lateral current spreading layer is contiguous with the active doped region.
5. The semiconductor structure of any of claims 1 to 4, wherein a lateral dimension of the lateral current spreading layer is greater than a lateral dimension of the active doped region;
preferably, the difference between the transverse size of the transverse current spreading layer and the transverse size of the active doped region is 0.1 um-3 um;
preferably, the number of the active doping regions is several, the active doping regions are separately arranged, and the transverse current expansion layers at the bottoms of the adjacent active doping regions are connected together.
6. The semiconductor structure of any of claims 1-4, a lateral dimension of the lateral current spreading layer being less than or equal to a lateral dimension of the active doped region.
7. The semiconductor structure of claim 1, wherein the lateral current spreading layer has a thickness of 0.1um to 3 um.
8. The semiconductor structure of claim 1, wherein the semiconductor structure is a junction barrier schottky diode; the semiconductor structure further includes: an anode layer over the drift layer and the active doped region;
or the semiconductor structure is a vertical metal oxide semiconductor field effect transistor or an insulated gate bipolar transistor, and the active doped region is used as a well region.
9. A method of fabricating a semiconductor structure according to any one of claims 1 to 8, comprising:
providing a semiconductor substrate layer;
forming a drift layer on the semiconductor substrate layer;
forming a lateral current spreading layer in the drift layer, wherein the conductivity type of the lateral current spreading layer is the same as that of the drift layer, and the doping concentration of the lateral current spreading layer is greater than that of the drift layer;
and forming an active doped region in the top region of the drift layer, wherein the active doped region is at least positioned above part of the transverse current expansion layer, the conductivity type of the active doped region is opposite to that of the drift layer, and the doping concentration of the active doped region is higher than that of the transverse current expansion layer.
10. The method of claim 9, wherein the semiconductor structure is a junction barrier schottky diode, and further comprising: forming an anode layer on the drift layer and the active doped region;
or, the semiconductor structure is a vertical metal oxide semiconductor field effect transistor or an insulated gate bipolar transistor, and the preparation method of the semiconductor structure further comprises the following steps: forming a gate structure on the drift layer after forming the active doped region; the active doped region is used as a well region which is positioned at two sides of the grid structure; forming an ohmic contact body doping area in the well area, wherein the conductivity type of the ohmic contact body doping area is the same as that of the well area;
when the semiconductor structure is a vertical metal oxide semiconductor field effect transistor, the preparation method of the semiconductor structure further comprises the following steps: forming a source region in the well region, wherein the conductivity type of the source region is the same as that of the drift layer;
when the semiconductor structure is an insulated gate bipolar transistor, the preparation method of the semiconductor structure further comprises the following steps: and forming an emission region in the well region, wherein the conductivity type of the emission region is the same as that of the drift layer.
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007036455A2 (en) * | 2005-09-29 | 2007-04-05 | Siced Electronics Development Gmbh & Co. Kg | Jbs-sic semiconductor component |
| CN102184950A (en) * | 2011-05-09 | 2011-09-14 | 电子科技大学 | Insulated gate bipolar transistor with cavity blocking layer(s) |
| US20130140584A1 (en) * | 2010-06-02 | 2013-06-06 | Norifumi Kameshiro | Semiconductor device |
| CN105742339A (en) * | 2014-12-24 | 2016-07-06 | Abb 技术有限公司 | Junction barrier schottky rectifier |
| CN106684134A (en) * | 2015-11-10 | 2017-05-17 | 株洲南车时代电气股份有限公司 | Power semiconductor device and manufacturing method thereof |
| JP2020188039A (en) * | 2019-05-09 | 2020-11-19 | 国立研究開発法人産業技術総合研究所 | Silicon carbide semiconductor device and manufacturing method thereof |
| CN112713199A (en) * | 2019-10-25 | 2021-04-27 | 株洲中车时代电气股份有限公司 | Silicon carbide Schottky diode and preparation method thereof |
| CN113039650A (en) * | 2018-11-30 | 2021-06-25 | 三菱电机株式会社 | Semiconductor device with a plurality of semiconductor chips |
-
2021
- 2021-12-31 CN CN202111673423.6A patent/CN114300529A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2007036455A2 (en) * | 2005-09-29 | 2007-04-05 | Siced Electronics Development Gmbh & Co. Kg | Jbs-sic semiconductor component |
| EP1929538A2 (en) * | 2005-09-29 | 2008-06-11 | SiCED Electronics Development GmbH & Co KG | Jbs-sic semiconductor component |
| US20130140584A1 (en) * | 2010-06-02 | 2013-06-06 | Norifumi Kameshiro | Semiconductor device |
| CN102184950A (en) * | 2011-05-09 | 2011-09-14 | 电子科技大学 | Insulated gate bipolar transistor with cavity blocking layer(s) |
| CN105742339A (en) * | 2014-12-24 | 2016-07-06 | Abb 技术有限公司 | Junction barrier schottky rectifier |
| CN106684134A (en) * | 2015-11-10 | 2017-05-17 | 株洲南车时代电气股份有限公司 | Power semiconductor device and manufacturing method thereof |
| CN113039650A (en) * | 2018-11-30 | 2021-06-25 | 三菱电机株式会社 | Semiconductor device with a plurality of semiconductor chips |
| JP2020188039A (en) * | 2019-05-09 | 2020-11-19 | 国立研究開発法人産業技術総合研究所 | Silicon carbide semiconductor device and manufacturing method thereof |
| CN112713199A (en) * | 2019-10-25 | 2021-04-27 | 株洲中车时代电气股份有限公司 | Silicon carbide Schottky diode and preparation method thereof |
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