CN114300354A - Manufacturing method of asymmetric semiconductor structure - Google Patents
Manufacturing method of asymmetric semiconductor structure Download PDFInfo
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- CN114300354A CN114300354A CN202111555966.8A CN202111555966A CN114300354A CN 114300354 A CN114300354 A CN 114300354A CN 202111555966 A CN202111555966 A CN 202111555966A CN 114300354 A CN114300354 A CN 114300354A
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Abstract
The invention discloses a manufacturing method of an asymmetric semiconductor structure, which comprises the following steps: providing a first wafer with a first through hole; providing a second wafer, and forming a photoresist layer with a second through hole on the second wafer; the width of the first through hole is larger than that of the second through hole; bonding the first wafer and the second wafer together to enable the first through hole and the second through hole to be communicated to form an asymmetric groove structure; etching the second wafer by taking the first wafer and the photoresist layer as masks to form an asymmetric semiconductor structure on the second wafer; and removing the first wafer and the photoresist layer by debonding. The preparation method comprises the steps of providing a first wafer with a first through hole, then providing a second wafer with a photoresist layer with a second through hole, bonding the first wafer and the second wafer to enable the first through hole and the second through hole to be communicated to form an asymmetric groove structure, and etching the second wafer through the asymmetric groove structure to form the asymmetric semiconductor structure.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a manufacturing method of an asymmetric semiconductor structure.
Background
Plasma etching is a common process for manufacturing microstructures in a wafer, and very good process uniformity can be obtained over the entire wafer, but they are often symmetrical structures, i.e., symmetrical features are shown on different sides of the pattern. In applications where asymmetric structures are particularly desirable, such as photovoltaic devices, asymmetric semiconductor structures allow radiation (e.g., light, heat, etc.) to pass through only one side, but not the other side.
Patent No. CN201910869767.0 provides a method for manufacturing a parallel inclined-hole grating plate and a grating plate, wherein the method includes: carrying out right-angle etching on the substrate to form a groove; performing bevel etching on one side of the groove to form a first bevel; arranging a first dielectric film on the substrate on which the first bevel is formed and bonding wafers to form a bevel; performing bevel etching on the substrate with the chamfer angle to form a second bevel angle; combining the photoetching pattern with the substrate forming the second bevel angle for photoetching to form a parallel inclined platform grating plate; and arranging a second dielectric film on the parallel inclined platform grating plate, and forming the parallel inclined hole structure grating plate by etching. The parallel inclined hole structure grating plate is manufactured in a projection type photoetching mode, the optical holographic imaging effect can be enhanced, and the manufacturing speed is accelerated. However, the asymmetric structure can be obtained only by etching the same wafer twice, the etching twice on the same wafer necessarily requires photolithography and alignment, and photolithography is the most costly link in semiconductor processing, and the alignment requirement of the wafer on the mask and the wafer is high by photolithography and alignment.
Therefore, it is desirable to provide a new method for fabricating an asymmetric semiconductor structure.
Disclosure of Invention
The invention aims to provide a manufacturing method of an asymmetric semiconductor structure, which at least solves the technical problems of complex process and high cost in the manufacturing process of the asymmetric semiconductor structure.
In order to achieve the above object, the present invention provides a method for fabricating an asymmetric semiconductor structure, comprising:
providing a first wafer, and forming a first through hole on the first wafer;
providing a second wafer, and forming a photoresist layer with a second through hole on the second wafer; wherein the width of the first through hole is greater than the width of the second through hole;
bonding the first wafer and the second wafer together so that the first through hole and the second through hole are communicated to form an asymmetric groove structure;
etching the second wafer by taking the first wafer and the photoresist layer as masks to form an asymmetric semiconductor structure on the second wafer;
and removing the first wafer and the photoresist layer by debonding.
Optionally, a first etching selection ratio of the first wafer and the second wafer and a second etching selection ratio of the photoresist layer on the second wafer and the second wafer are both greater than 1: 1.
Optionally, the forming a first through hole on the first wafer includes:
preparing a metal mask layer serving as a first wafer mask on the surface of the first wafer;
carrying out through hole etching on the first wafer to form the first through hole;
and removing the metal mask layer.
Optionally, the metal mask layer includes an adhesion layer, a seed layer, and a main etching mask layer, and the method for preparing the metal mask layer includes:
coating photoresist on the surface of the first wafer, and forming a patterned photoresist mask layer after exposure and development;
sequentially preparing an adhesion layer, a seed layer and a main etching mask layer in an area, which avoids the photoresist mask layer, on the surface of the first wafer;
and removing the photoresist mask layer.
Optionally, the adhesion layer and the seed layer are prepared by a PVD method, and the main etching mask layer is prepared by an electroplating method; the materials of the adhesion layer, the seed layer and the main etching mask layer are respectively titanium, copper and copper.
Optionally, the adhesion layer and the seed layer are prepared by a vacuum thermal evaporation method, and the main etching mask layer is prepared by an electroplating method; the adhesion layer, the seed layer and the main etching mask layer are made of chromium, gold and nickel respectively.
Optionally, before forming the photoresist layer with the second through hole on the second wafer, the method further includes:
and forming an auxiliary etching layer on the surface of the second wafer, wherein the auxiliary etching layer is used for changing the initial etching angle of the second wafer during etching so as to adjust the angle difference value of the asymmetric semiconductor structure.
Optionally, the auxiliary etching layer is a silicon oxide layer, and the thickness of the silicon oxide layer is 10nm to 1000 nm.
Optionally, the etching the second wafer by using the first wafer as a mask includes:
and etching the auxiliary etching layer with the photoresist layer, and forming the initial etching angle when the second wafer is continuously over-etched after the auxiliary etching layer is etched through, wherein the duration of the over-etching stage is 5-20% of the time for the auxiliary etching layer to be etched through.
Optionally, the power range of the lower electrode for etching the auxiliary etching layer and over-etching the second wafer is 50-500W, and the angle difference value can be adjusted to be 5-50 degrees by changing the power of the lower electrode.
Optionally, the debonding comprises heating or irradiation.
The invention has the beneficial effects that:
the manufacturing method comprises the steps of firstly providing a first wafer with a first through hole as an auxiliary wafer, then providing a second wafer with a photoresist layer of a second through hole, bonding the first wafer and the second wafer to enable the first through hole and the second through hole to be communicated to form an asymmetric groove structure, and etching the second wafer through the asymmetric groove structure to form an asymmetric semiconductor structure.
Further, an auxiliary etching layer is formed on the second wafer and used for changing an initial etching angle of the second wafer during etching, so that the angle difference value of the asymmetric semiconductor structure is adjusted.
Additional features and advantages of the invention will be set forth in the detailed description which follows.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent by describing in more detail exemplary embodiments thereof with reference to the attached drawings, in which like reference numerals generally represent like parts throughout.
Fig. 1 to fig. 11 are schematic structural views corresponding to different steps of a method for manufacturing an asymmetric semiconductor structure according to embodiment 1 of the present invention.
Fig. 12 is a schematic structural diagram illustrating steps of a method for fabricating an asymmetric semiconductor structure according to another embodiment of the present invention.
Fig. 13 is a schematic structural diagram corresponding to different steps of a method for fabricating an asymmetric semiconductor structure according to embodiment 1 of the present invention.
Fig. 14 is a schematic structural diagram corresponding to different steps of a method for fabricating an asymmetric semiconductor structure according to embodiment 2 of the present invention.
Fig. 15 is a diagram illustrating an effect of the semiconductor structure after the plasma etching process in embodiment 1 of the present invention.
Fig. 16 and 17 are respectively a diagram showing the effect of the semiconductor structure after the plasma etching process in embodiment 2 of the present invention.
Reference numerals: 10. a first wafer; 11. a photoresist mask layer; 12. a metal mask layer; 121. an adhesion layer; 122. a seed layer; 123. main etching the mask layer; 13. a first through hole; 20. a second wafer; 21. a photoresist layer; 22. a second through hole; 30. a silicon oxide layer.
Detailed Description
Preferred embodiments of the present invention will be described in more detail below. While the following describes preferred embodiments of the present invention, it should be understood that the present invention may be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
It should be noted that, in the present specification, all the embodiments are described in a related manner, and the same and similar parts among the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the structural embodiment, since it is substantially similar to the method embodiment, the description is relatively simple, and for the relevant points, reference may be made to the partial description of the method embodiment.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below.
Example 1
The invention provides a manufacturing method of an asymmetric semiconductor structure, which comprises the following steps:
providing a first wafer, and forming a first through hole on the first wafer;
providing a second wafer, and forming a photoresist layer with a second through hole on the second wafer; the width of the first through hole is larger than that of the second through hole;
bonding the first wafer and the second wafer together to enable the first through hole and the second through hole to be communicated to form an asymmetric groove structure;
etching the second wafer by taking the first wafer and the photoresist layer as masks to form an asymmetric semiconductor structure on the second wafer;
and removing the first wafer and the photoresist layer by debonding.
Referring to fig. 1-6, a first wafer 10 is provided, and a first via 13 is formed on the first wafer 10.
Forming a first via 13 on the first wafer 10 includes:
referring to fig. 1, a first wafer 10 is provided.
The first wafer 10 is an auxiliary wafer, and the material of the first wafer 10 is selected according to the material and etching selection ratio of the subsequent second wafer.
Etch selectivity, defined as the ratio of the etch rate of the material being etched to the etch rate of another material, measures how much the etch rate of one material differs from the etch rate of another material under the same etch conditions.
Referring to fig. 2, a photoresist is coated on the surface of the first wafer 10, and a patterned photoresist mask layer 11 is formed after exposure and development.
Specifically, a photoresist is coated on a first wafer 10, the thickness of the photoresist is 0.5-30 microns, preferably 15 microns, then a photomask plate is arranged right above the first wafer 10, and the photoresist forms a patterned photoresist mask layer 11 after exposure and development, as shown in fig. 2, in the embodiment, the exposure time is in a range of 3-20 seconds, preferably 6 seconds; the developing time ranges from 45 s to 120s, preferably 75s, and the fixing time ranges from 60 s to 300s, preferably 120 s.
Referring to fig. 3, after forming the photoresist mask layer 11, a metal mask layer is prepared on the surface of the first wafer 10 in an area avoiding the photoresist mask layer 11, and the metal mask layer is used as a mask of the first wafer 10, and includes an adhesion layer 121, a seed layer 122, and a main etching mask layer 123.
In the present embodiment, the adhesion layer 121 is formed on the first wafer 10, the seed layer 122 is formed on the adhesion layer 121, and the main etching mask layer 123 is formed on the adhesion layer 121; the adhesion layer 121 is made of titanium, and the thickness of the titanium is 0.05-0.2 micrometer, preferably 0.1 micrometer; the seed layer 122 is made of copper; the thickness of the copper is 0.1-0.5 micrometer, preferably 0.3 micrometer; the main etching mask layer 123 is made of copper, and the thickness of the copper is 0.5-50 micrometers; the adhesion layer 121 and the seed layer 122 are prepared by a PVD method, and the process conditions are as follows: the cavity pressure ranges from 10 mTorr to 100mTorr, the upper electrode power ranges from 750W to 3000W, the lower electrode power ranges from 5W to 500W, and the argon flow ranges from 50 sccm to 500 sccm; the main etch mask layer 123 is prepared by an electroplating method.
It should be noted that, on one hand, the adhesion layer 121 can better adhere the seed layer 122 to the first wafer 10, so as to improve the adhesion between the seed layer 122 and the first wafer 10; on the other hand, the difficulty of removing the metal mask layer can be reduced subsequently.
In another embodiment, the adhesion layer 121 is made of chromium, and the thickness of the chromium is in a range of 1 to 10nm, preferably 5 nm; the seed layer 122 is made of gold, the thickness of the gold is 10-100 nm, and the preferred thickness is 50 nm; the material of the main etching mask layer 123 is nickel, and the thickness range of the nickel is 5-15 micrometers, preferably 10 micrometers; the adhesion layer 121 and the seed layer 122 are prepared by a vacuum thermal evaporation method under the conditions: cavity pressure range 5X 10-5～5×10-4Pa, preferably 1X 10-4Pa, the current range is 1-20 mA, preferably 5mA, and the material of the main etching mask layer 123The main etch mask layer 123 is made of nickel by an electroplating method.
Referring to fig. 4, the photoresist mask layer 11 is removed.
In this embodiment, the photoresist mask layer 11 is removed by wet stripping. After the photoresist mask layer 11 is removed, the metal mask layer 12 remains on the first wafer 10.
Referring to fig. 5 and 6, via etching is performed on the first wafer 10 to form a first via 13; metal masking layer 12 is removed.
The etching process includes dry etching and wet etching, and the embodiment etches the first wafer 10 by the dry etching process to form the first via 13. The process conditions for dry etching the first through hole 13 in this embodiment are shown in table 1:
TABLE 1
Wherein the cavity pressure is 1-30 mTorr, the power of the upper electrode is 600-3000W, the power of the lower electrode is 50-500W, the flow of argon is 10-100 sccm, and CF is4The flow range is 10-100 sccm, and the temperature range of the base cooling liquid is-15-10 ℃; the time is 1-50 min.
After the etching process is completed, the metal mask layer 12 is removed, and a first wafer 10 having a first via 13 is formed, as shown in fig. 6.
It should be noted that the method for removing the metal mask layer 12 is determined by the material of the first wafer 10, and in this embodiment, the metal mask layer 12 is removed by a pickling process, for example, the first wafer 10 is made of glass and can be removed by aqua regia.
The formation of the first wafer 10 with the first via 13 is used to cushion the subsequent formation of the asymmetric semiconductor structure.
Referring to fig. 7 and 8, a second wafer 20 is provided, and a photoresist layer 21 having a second via hole 22 is formed on the second wafer 20; wherein the width of the first through hole 13 is greater than the width of the second through hole 22.
The second wafer 20 is a wafer to be etched, and the second wafer 20 may be any suitable substrate material known to those skilled in the art, such as silicon, silicon oxide, silicon carbide, or aluminum oxide.
The first etching selection ratio of the first wafer 10 and the second wafer 20 and the second etching selection ratio of the photoresist layer 21 on the second wafer 20 and the second wafer 20 are both greater than 1:1, the material of the first wafer 10 is determined by the material of the second wafer 20 and the first etching selection ratio, in this embodiment, the material of the second wafer 20 is silicon, and the material of the first wafer 10 may be glass or sapphire.
Referring to fig. 9 and 10, the first wafer 10 and the second wafer 20 are bonded together, in this embodiment, the bonding is performed by using organic glue, that is, the first wafer 10 is spin-coated with the organic glue, and then the second wafer 20 and the first wafer 10 are pressed and bonded, so that the first through hole and the second through hole are communicated to form an asymmetric groove structure, that is, central axes of the first through hole and the second through hole are not overlapped; .
Referring to fig. 10 and 13, in the present embodiment, the first wafer 10 and the photoresist layer 21 are used as masks, and the second wafer 20 is etched through a plasma etching process to form an asymmetric semiconductor structure on the second wafer 20.
The conditions for fabricating the asymmetric semiconductor structure are as follows: the width of the first through hole 13 of the first wafer 10 is greater than the width of the second through hole 22 on the photoresist layer 21, and the first through hole 13 and the second through hole 22 are communicated to form an asymmetric trench structure, during plasma etching, the inner wall of the first through hole 13 forms a plasma sheath layer as shown by a dotted line, as shown in fig. 13, under the action of the first wafer 10, the plasma sheath layer is bent to cause distortion of an electromagnetic field, that is, the electromagnetic field is perpendicular to the plasma sheath layer, and when the plasma sheath layer (as shown by the dotted line in fig. 13) is changed by the first wafer 10, the electromagnetic field is distorted accordingly, so that deflection of an etching angle is generated, and an asymmetric semiconductor structure is formed.
It should be noted that the second through hole 22 of the photoresist layer 21 may be close to the right side of the first wafer 10, or close to the left side of the first wafer 10; the second via 22 of the photoresist layer 21 of this embodiment is close to the left side of the first wafer 10, and an asymmetric trench structure is formed as shown in fig. 9. In another embodiment, the second via 22 of the photoresist layer 21 is close to the right side of the first wafer 10, and an asymmetric trench structure is formed as shown in fig. 12; the longitudinal section of the asymmetrical groove structure is in a step shape.
FIG. 15 is an illustration of the semiconductor structure after plasma etching with a left sidewall angle of 65.56 degrees and a right sidewall angle of 50.26 degrees, introducing an asymmetry of about 15 degrees; the dry etching process conditions for the asymmetric structure of the second wafer 20 of this embodiment are shown in table 2:
TABLE 2
Wherein, the cavity pressure range is 10-200 mTorr, the central power range of the upper electrode is 600-3000W, the edge power range of the upper electrode is 500-3000W, the power range of the lower electrode is 50-500W, and the center C4F8Flow rate range of 10-1000 sccm, edge C4F8The flow rate ranges from 10 sccm to 1000sccm, and the center O2Flow rate range of 10-1000 sccm, edge O2Flow rate range of 10-1000 sccm, center SF6Flow rate range of 10-1000 sccm, edge SF6The flow rate ranges from 10 sccm to 1000sccm, and the temperature of the base cooling liquid ranges from-15 ℃ to 40 ℃.
Referring to fig. 11, the first wafer 10 and the photoresist layer 21 are removed.
Removing the first wafer 10 and the photoresist layer 21 by a wet method in a manner of bonding; the first method is to heat the bonded first wafer 10 and second wafer 20 to weaken the adhesion of the organic glue, so that the second wafer 20 is separated from the first wafer 10; the other method is to use irradiation (ultraviolet or laser) to modify the organic glue, so as to separate the second wafer 20 from the first wafer 10.
The manufacturing method of the invention is that the first wafer 10 with the first through hole 13 is provided as an auxiliary wafer, then the second wafer 20 with the photoresist layer 21 of the second through hole 20 is provided, the first wafer 10 and the second wafer 20 are bonded to enable the first through hole 13 and the second through hole 22 to be communicated to form an asymmetric groove structure, and the second wafer 20 is etched through the asymmetric groove structure to form an asymmetric semiconductor structure.
Example 2
Referring to fig. 14, the present embodiment further provides a method for fabricating an asymmetric semiconductor structure, which is different from embodiment 1 in that: before forming the photoresist layer 21 with the second through hole 22 on the second wafer 20, the method further includes: an auxiliary etching layer is formed on the surface of the second wafer 20, and the auxiliary etching layer is used for changing the initial etching angle of the second wafer 20 during etching, so as to adjust the angle difference value of the asymmetric semiconductor structure.
Etching the second wafer 20 with the auxiliary etching layer by using the first wafer 10 and the photoresist layer 21 as masks comprises:
and etching the auxiliary etching layer, and forming an initial etching angle when the second wafer 20 is continuously over-etched after the auxiliary etching layer is etched through, wherein the duration of the over-etching stage is 5-20% of the time for etching through the auxiliary etching layer.
The auxiliary etching layer is a silicon oxide layer 30, and the thickness of the silicon oxide layer 30 is 10nm to 1000nm, preferably 50nm in this embodiment.
In the embodiment, the initial etching angle of the second wafer 20 during etching can be changed by changing the thickness of the silicon oxide layer 30 and the etching time, so as to adjust the angle difference value of the asymmetric semiconductor structure.
The principle of the silicon oxide layer 30 for adjusting the angle difference value of the semiconductor structure is as follows: before etching silicon, the silicon oxide layer 30 is etched, after the silicon oxide layer 30 is etched, the silicon is etched by using the process condition for etching the silicon oxide layer 30, so that an inclined initial etching angle is formed on the silicon, and the angle difference value of the asymmetric semiconductor structure can be adjusted by using the initial etching angle because the process condition for etching the silicon oxide layer 30 is different from the process condition for etching the second wafer.
The process of forming the silicon oxide layer 30 includes:
a silicon oxide layer 30 having a thickness of about 50nm is formed on the second wafer 20 through a thermal oxidation process. Firstly, the second wafer 20 is placed in a reaction tube made of quartz glass, the reaction tube is heated by a resistance wire heating furnace to a certain temperature, the common temperature is 750-1500 ℃, preferably 1000 ℃, the temperature can be reduced to below 600 ℃ under special conditions, and when oxygen or water vapor passes through the reaction tube (the air flow velocity is 1 cm/s), oxidation chemical reaction is carried out on the surface of a silicon wafer to generate a silicon oxide layer 30. The process flow comprises the following steps: the first step is as follows: entering a boat; the second step is that: heating; the third step: the temperature is stable; the fourth step: performing a main process; the fifth step: purging with nitrogen; and a sixth step: cooling; the seventh step: taking out of the boat; the working contents of each stage are illustrated as follows: a stage of boat feeding and Wafer loading into a reaction chamber; a temperature rising-temperature rising stage; temperature stabilization-temperature stabilization after temperature rise stage; in the main process-wet oxygen process stage, reaction gases of hydrogen and oxygen are introduced to carry out an oxidation film forming process; nitrogen purging-stopping introducing hydrogen, and entering a nitrogen purging stage; cool down-temperature is lowered and wafer is removed from the reaction chamber. The process formula comprises the following steps: the temperature is 1000 ℃, the flow rate of the reactant hydrogen is 500sccm, the flow rate of the reactant oxygen is 500sccm, the flow rate of the carrier gas oxygen is 500sccm, the partial pressure range of the water vapor is 0.5 atmosphere, and the time is determined according to the thickness of the silicon oxide layer 30 to be grown. After forming the silicon oxide layer 30 on the second wafer 20, spin-coating a photoresist layer 21; the method of forming the photoresist layer 21 with the second via 22 after spin-coating the photoresist layer 21 is similar to that of embodiment 1, and will not be described herein.
Tables 3 and 4 show the etching process conditions for etching the silicon oxide layer 30 and over-etching the second wafer 20, specifically, after the silicon oxide layer 30 is etched, the second wafer 20 is over-etched by using the process conditions for etching the silicon oxide layer 30, the duration of the over-etching stage is 5% -20% of the time for etching the auxiliary etching layer, and after the second wafer 20 is over-etched, the second wafer 20 is etched by using the process conditions of table 2; the etching conditions of the silicon oxide layer 30 and the over-etched second wafer 20 can be as shown in table 3, fig. 16 is a graph of the effect of the semiconductor structure etched by using table 3, and it can be seen from fig. 16 that the sidewall angle of the second wafer 20 is relatively vertical, wherein the left sidewall inclination angle is 73.16 °, the right sidewall inclination angle is 55.07 °, and an asymmetry of about 18 ° is introduced. The etching conditions of the silicon oxide layer 30 and the over-etched second wafer 20 can also be adopted as shown in table 4, fig. 17 is a graph of the effect of the semiconductor structure etched by using table 4, and it can be seen from fig. 17 that the sidewall angle of the second wafer 20 is relatively inclined, wherein the left sidewall inclination angle is 70.97 °, the right sidewall inclination angle is 58.32 °, and an asymmetry of about 12 ° is introduced. From the experimental data and results of tables 3 and 4, it can be seen that: by changing the power of the lower electrode when the silicon oxide layer 30 and the second wafer 20 are etched, the initial etching angle during etching can be changed, and further the angle difference value of the asymmetric structure can be adjusted; the power range of the lower electrode for etching the silicon oxide layer 30 and over-etching the second wafer 20 is 50-500W, and the range of the angle difference value can be adjusted to be 5-50 degrees by changing the power of the lower electrode.
TABLE 3
Wherein, the cavity pressure range is 10-200 mTorr, the central power range of the upper electrode is 600-3000W, the edge power range of the upper electrode is 500-3000W, the power range of the lower electrode is 50-500W, and the center C4F8Flow rate range of 10-1000 sccm, edge C4F8The flow rate ranges from 10 sccm to 1000sccm, and the center O2Flow rate range of 10-1000 sccm, edge O2Flow rate range of 10-1000 sccm, center SF6Flow rate range of 10-1000 sccm, edge SF6The flow rate ranges from 10 sccm to 1000sccm, and the temperature of the base cooling liquid ranges from-15 ℃ to 40 ℃.
TABLE 4
Wherein, the cavity pressure range is 10-200 mTorr, the central power range of the upper electrode is 600-3000W, the edge power range of the upper electrode is 500-3000W, and the power range of the lower electrode50-500W of enclosure and center C4F8Flow rate range of 10-1000 sccm, edge C4F8The flow rate ranges from 10 sccm to 1000sccm, and the center O2Flow rate range of 10-1000 sccm, edge O2Flow rate range of 10-1000 sccm, center SF6Flow rate range of 10-1000 sccm, edge SF6The flow rate ranges from 10 sccm to 1000sccm, and the temperature of the base cooling liquid ranges from-15 ℃ to 40 ℃.
The other contents are the same as those in embodiment 1, and the description of this embodiment is omitted.
Having described embodiments of the present invention, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments.
Claims (11)
1. A method for fabricating an asymmetric semiconductor structure, comprising:
providing a first wafer, and forming a first through hole on the first wafer;
providing a second wafer, and forming a photoresist layer with a second through hole on the second wafer; wherein the width of the first through hole is greater than the width of the second through hole;
bonding the first wafer and the second wafer together so that the first through hole and the second through hole are communicated to form an asymmetric groove structure;
etching the second wafer by taking the first wafer and the photoresist layer as masks to form an asymmetric semiconductor structure on the second wafer;
and removing the first wafer and the photoresist layer by debonding.
2. The method of claim 1, wherein a first etching selectivity of the first wafer and the second wafer and a second etching selectivity of the photoresist layer on the second wafer and the second wafer are both greater than 1: 1.
3. The method of claim 1, wherein the forming a first via on the first wafer comprises:
preparing a metal mask layer serving as a first wafer mask on the surface of the first wafer;
carrying out through hole etching on the first wafer to form the first through hole;
and removing the metal mask layer.
4. The method of claim 3, wherein the metal mask layer comprises an adhesion layer, a seed layer, and a main etch mask layer, and the method of forming the metal mask layer comprises:
coating photoresist on the surface of the first wafer, and forming a patterned photoresist mask layer after exposure and development;
sequentially preparing an adhesion layer, a seed layer and a main etching mask layer in an area, which avoids the photoresist mask layer, on the surface of the first wafer;
and removing the photoresist mask layer.
5. The production method according to claim 4, wherein the adhesion layer and the seed layer are produced by a PVD method, and the main etching mask layer is produced by an electroplating method; the materials of the adhesion layer, the seed layer and the main etching mask layer are respectively titanium, copper and copper.
6. The production method according to claim 4, wherein the adhesion layer and the seed layer are produced by a vacuum thermal evaporation method, and the main etching mask layer is produced by an electroplating method; the adhesion layer, the seed layer and the main etching mask layer are made of chromium, gold and nickel respectively.
7. The method of claim 1, wherein before forming the photoresist layer with the second via on the second wafer, further comprising:
and forming an auxiliary etching layer on the surface of the second wafer, wherein the auxiliary etching layer is used for changing the initial etching angle of the second wafer during etching so as to adjust the angle difference value of the asymmetric semiconductor structure.
8. The method according to claim 7, wherein the auxiliary etching layer is a silicon oxide layer, and the thickness of the silicon oxide layer is 10nm to 1000 nm.
9. The method of claim 7, wherein the etching the second wafer with the first wafer as a mask comprises:
and etching the auxiliary etching layer with the photoresist layer, and forming the initial etching angle when the second wafer is continuously over-etched after the auxiliary etching layer is etched through, wherein the duration of the over-etching stage is 5-20% of the time for the auxiliary etching layer to be etched through.
10. The method according to claim 9, wherein the power of the lower electrode for etching the auxiliary etching layer and over-etching the second wafer is 50-500W, and the angle difference can be adjusted to be 5-50 ° by changing the power of the lower electrode.
11. The method of claim 1, wherein the debonding comprises heating or irradiation.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115259679A (en) * | 2022-07-26 | 2022-11-01 | Oppo广东移动通信有限公司 | Substrate etching method, housing assembly and electronic device |
| CN115799049A (en) * | 2022-11-28 | 2023-03-14 | 湖北江城芯片中试服务有限公司 | Preparation method of semiconductor structure |
-
2021
- 2021-12-17 CN CN202111555966.8A patent/CN114300354A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115259679A (en) * | 2022-07-26 | 2022-11-01 | Oppo广东移动通信有限公司 | Substrate etching method, housing assembly and electronic device |
| CN115259679B (en) * | 2022-07-26 | 2024-02-27 | Oppo广东移动通信有限公司 | Etching method of substrate, shell assembly and electronic equipment |
| CN115799049A (en) * | 2022-11-28 | 2023-03-14 | 湖北江城芯片中试服务有限公司 | Preparation method of semiconductor structure |
| CN115799049B (en) * | 2022-11-28 | 2023-08-08 | 湖北江城芯片中试服务有限公司 | Method for preparing semiconductor structure |
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