CN114284333A - Semiconductor structure, device and manufacturing method - Google Patents
Semiconductor structure, device and manufacturing method Download PDFInfo
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- CN114284333A CN114284333A CN202110615640.3A CN202110615640A CN114284333A CN 114284333 A CN114284333 A CN 114284333A CN 202110615640 A CN202110615640 A CN 202110615640A CN 114284333 A CN114284333 A CN 114284333A
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Abstract
The present disclosure relates to a semiconductor structure, a device and a method of manufacturing, wherein the semiconductor structure comprises: a first region having a first conductivity type; a second region of the first conductivity type and/or the second conductivity type on the first region; a third region on the second region and having a conductivity type opposite to that of the second region; the third region includes: a channel region and a drift region; the source region is positioned on the second region and is adjacent to one side of the third region, and the drain region is positioned on the second region and is adjacent to the other side of the third region; the conductivity type of the source region and the drain region is the same as that of the adjacent third region. According to the scheme, the drift region is introduced into the fin structure of the FinFET, so that the voltage consumption of the high-voltage semiconductor structure is increased, and the high-voltage semiconductor structure has a longer circuit path by matching with the isolation groove structure, so that the high voltage can be dissipated, and the high-voltage semiconductor structure can maintain high-voltage operation under the voltage of 1.8V or 3.3V.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor structure, a device and a manufacturing method, wherein the semiconductor structure, the device and the manufacturing method can maintain high-voltage operation under the voltage of 1.8V or 3.3V.
Background
With the development of the semiconductor industry, semiconductor processes have entered the nanometer-scale process era. While pursuing higher device density, higher performance and lower cost, it also presents new manufacturing and design challenges for three-dimensional semiconductor designs.
Fin field effect transistors (finfets) are used as three-dimensional semiconductor devices, and unlike non-planar FETs, finfets can carry more devices and circuits in a limited space, thereby further increasing the speed of the semiconductor devices. The fin of a FinFET is a narrow vertical semiconductor structure that serves as a channel between the source and drain, the outside of the fin being covered with a thin insulating material, and a gate covering two or three sides of the fin covered with the insulating material. Finfets improve the density and gate control of the device channel. Applications are found in many three-dimensional devices, such as Static Random Access Memories (SRAMs) and logic devices.
Disclosure of Invention
The present scheme is intended to provide a semiconductor structure, device and method of manufacture that has solved the problem that conventional junction-free finfets cannot operate at high voltages.
In order to achieve the purpose, the technical scheme is as follows:
in a first aspect, the present scheme provides a semiconductor structure comprising:
a first region having a first conductivity type;
a second region of the first conductivity type and/or the second conductivity type on the first region;
a third region on the second region and having a conductivity type opposite to that of the second region; the third region includes: a channel region and a drift region;
the source region is positioned on the second region and is adjacent to one side of the third region, and the drain region is positioned on the second region and is adjacent to the other side of the third region; the conductivity type of the source region and the drain region is the same as that of the adjacent third region.
In a preferred embodiment, the first conductivity type is P-type, and the second conductivity type is N-type; or, the first conductivity type is N-type, and the second conductivity type is P-type.
In a preferred embodiment, the second region has a plurality of first trench structures uniformly arranged therein;
the first groove structure divides the second area into a plurality of conductive areas;
each conductive region has a portion of the third region thereon; the part of the third area is a plurality of fin structures formed by dividing the third area;
the source region and the drain region abut on both sides of the fin structure on the conductive region in a direction of the first trench structure.
In a preferred embodiment, the first region includes: a substrate having a first conductivity type and an epitaxial layer having the first conductivity type on the substrate.
In a preferred embodiment, the second region of the first conductivity type and the second region of the second conductivity type have a second trench structure between them.
In a preferred embodiment, the source region adjoins the channel region; the drain region is adjacent to the drift region.
In a preferred embodiment, the method further comprises: a gate structure located over the channel region in the third region;
the gate structure includes: a gate insulating layer on the third region, a gate on the gate insulating layer, and spacers on sides of the gate.
In a preferred embodiment, the first trench structure and/or the second trench structure are filled with tetraethylorthosilicate TEOS.
In a preferred embodiment, the source region and/or the drain region have a diamond structure.
In a second aspect, the present solution provides a semiconductor device comprising: a plurality of high voltage semiconductor structures as described above arranged in an array.
In a third aspect, the present disclosure provides a method for manufacturing a semiconductor structure, the method comprising:
forming a first region having a first conductivity type;
forming a second region having a first conductive type and/or a second conductive type on the first region;
forming a third region having a conductivity type opposite to that of the second region on the second region; the third region includes: a channel region and a drift region;
forming a source region adjacent to one side of the third region on the second region, and forming a drain region adjacent to the other side of the third region on the second region; the conductivity type of the source region and the drain region is the same as that of the adjacent third region.
In a preferred embodiment, the first conductivity type is P-type, and the second conductivity type is N-type; or, the first conductivity type is N-type, and the second conductivity type is P-type.
In a preferred embodiment, the step of forming the first region having the first conductivity type includes:
forming a substrate having a first conductivity type;
forming an epitaxial layer having a first conductivity type on the substrate; wherein the second region is formed on the epitaxial layer.
In a preferred embodiment, the step of forming a third region having an opposite conductivity type to the second region on the second region is followed by:
penetrating through the third region, and forming a plurality of second groove structures arranged in a transverse array manner in the second region; wherein the direction in which the second region having the first conductivity type and the second region having the second conductivity type adjoin is a lateral direction;
the second groove structure divides the second area into a plurality of conductive areas;
the third region is divided into a plurality of fin structures while penetrating through the third region, and each conductive region is provided with one fin structure;
covering a TEOS layer on the second region, the groove structure and the fin structure;
and removing the TEOS layer on the fin structure and above the groove.
In a preferred embodiment, the step of forming a plurality of second trench structures arranged in a lateral array in the second region through the third region is followed by:
forming a second trench structure between the second region of the first conductivity type and the second region of the second conductivity type through the third region;
a portion of the first trench structure is located within the second region of the first conductivity type and another portion thereof is located within the second region of the second conductivity type.
In a preferred embodiment, the step of forming a source region adjacent to one side of the third region on the second region and forming a drain region adjacent to the other side of the third region on the second region comprises: and forming a gate structure on the third region.
In a preferred embodiment, the step of forming a gate structure on the third region comprises: forming an etch stop layer on the fin structure;
forming an insulator layer over the trench structure and on the etch stop layer;
sequentially forming a hard mask and a bottom anti-reflection coating on the insulator layer;
removing the insulator layer, the hard mask and the bottom anti-reflection coating above the groove structure and on the fin structure outside the preset area; the predetermined region is a region on the fin structure in the third region as a channel region and a drift region
Removing the bottom anti-reflection coating on the insulator layer in the preset area and the insulator on the drift region in the fin structure in the preset area;
forming a gate layer on top of the insulator layer;
forming a spacer layer on the gate layer;
the insulator layer on top of the gate layer and over the drift region is removed.
In a preferred embodiment, the step of removing the bottom anti-reflection coating on the insulator layer in the predetermined region and the insulator on the drift region in the fin structure in the predetermined region includes:
patterning the hard mask after removing the bottom anti-reflection coating;
reserving the hard mask above the channel region, and removing the hard mask above the drift region;
and then removing the bottom anti-reflection coating of the predetermined area.
In a preferred embodiment, the step of forming a source region adjacent to one side of the third region on the second region, and forming a drain region adjacent to the other side of the third region on the second region includes:
removing the fin structures outside the preset area;
forming a source region adjacent to the channel region on one side of the channel region;
a source region is formed adjacent to the drift region on one side of the drift region.
In a preferred embodiment, the step of removing the fin structure outside the predetermined region comprises:
when a source region and a drain region are formed above the second region of the first conductivity type, the drift regions in the fin structures on the second region of the second conductivity type and the second region of the first conductivity type cover the SiCN mask layer and the bottom anti-reflection coating;
when a source region and a drain region are formed above the second region of the second conductivity type, the drift region in the fin structure on the second region of the first conductivity type and on the second region of the second conductivity type covers the SiCN mask layer and the BARC layer.
In a preferred embodiment, the step of forming a source region adjacent to one side of the third region on the second region and forming a drain region adjacent to the other side of the third region on the second region includes, after:
and removing the SiCN mask layer and the bottom anti-reflection coating above the second region of the first conduction type and the second region of the first conduction type.
Advantageous effects
According to the scheme, the drift region is introduced into the fin structure of the FinFET, so that the voltage consumption of the high-voltage semiconductor structure is increased, and the high-voltage semiconductor structure has a longer circuit path by matching with the isolation groove structure, so that the high voltage can be dissipated, and the high-voltage semiconductor structure can maintain high-voltage operation under the voltage of 1.8V or 3.3V.
Drawings
Fig. 1 is a schematic diagram illustrating a prior art finfet structure;
fig. 2 shows a right side view of the semiconductor structure according to the present scheme.
Fig. 3 is a schematic diagram illustrating a method for manufacturing a semiconductor structure according to the present embodiment.
Fig. 4 shows a cross-sectional view of a structure at a stage in the manufacturing process of a semiconductor memory device according to an embodiment of the present scheme.
Fig. 5 shows a cross-sectional view of a structure at a stage in the manufacturing process of a semiconductor memory device according to an embodiment of the present scheme.
Fig. 6 shows a cross-sectional view of a structure at a stage in the manufacturing process of a semiconductor memory device according to an embodiment of the present scheme.
Fig. 7 shows a cross-sectional view of a structure at a stage in the fabrication of a semiconductor memory device according to an embodiment of the present scheme.
Fig. 8 is a cross-sectional view of a structure at a stage in the fabrication of a semiconductor memory device according to an embodiment of the present scheme.
Fig. 9 is a cross-sectional view of a structure at a stage in the fabrication of a semiconductor memory device according to an embodiment of the present scheme.
Fig. 10 is a cross-sectional view of a structure at a stage in the fabrication of a semiconductor memory device according to an embodiment of the present scheme.
Fig. 11 is a cross-sectional view of a structure at a stage in the fabrication of a semiconductor memory device according to an embodiment of the present scheme.
Fig. 12-1 shows a front view of a cross-sectional structure of a stage in the fabrication of a semiconductor memory device according to an embodiment of the present scheme.
Fig. 12-2 shows a right side view of a cross-sectional structure of a stage in the fabrication of a semiconductor memory device according to one embodiment of the present scheme.
Fig. 13 is a cross-sectional view of a structure at a stage in the fabrication of a semiconductor memory device according to an embodiment of the present scheme.
Fig. 14 is a cross-sectional view of a structure at a stage in the fabrication of a semiconductor memory device according to an embodiment of the present scheme.
Fig. 15 shows a schematic diagram of a high-voltage semiconductor device according to the present embodiment.
Description of the reference symbols
1. A first region; 101. a substrate layer; 102. an epitaxial layer;
2. a second region; 201. a conductive region; 202. a first trench structure; 203. a second trench structure;
3. a third region; 301. a fin structure; 302. a channel region; 303. a drift region;
4. a gate structure; 401. an insulator layer; 402. a gate layer; 403. a spacer layer;
5. a source region;
6. a drain region;
7. an etch stop layer;
8. a hard mask;
9. a bottom anti-reflective coating.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity, position relationship and proportion of the components in actual implementation can be changed freely on the premise of implementing the technical solution of the present invention, and the layout form of the components may be more complicated. Thus, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, exemplary embodiments should not be construed as limited to the particular shapes of regions illustrated in the drawings, but may also include deviations in shapes that result, for example, from manufacturing processes. In the drawings, the length and size of some layers and regions may be exaggerated for clarity. Like reference numerals in the drawings denote like parts. It will also be understood that when a layer is referred to as being "on" another layer or a separate layer, it can be directly on the other layer or the separate layer, or intervening layers may also be present.
As shown in fig. 1, through research and analysis, a conventional FinFET is fabricated by etching away a portion of the silicon layer of the substrate and extending a relatively thin vertical "fin" (or fin structure) from the substrate, with the channel of the FinFET being formed based on the vertical fin structure. And forming a wrapping type grid structure on the fin structure, and controlling the opening and closing of the channel by using the grid structure. Selectively grown silicon germanium (SiGe) is utilized as a strained material for the source/drain (S/D) portion of the FinFET, thereby enhancing carrier mobility. However, such conventional finfet cannot maintain high voltage operation, for example, 1.8V or 3.3V.
Therefore, the scheme is intended to provide a high-voltage semiconductor structure, the consumption of the high-voltage semiconductor structure to voltage is improved by introducing the drift region into the fin structure in the high-voltage semiconductor structure, and the high-voltage semiconductor structure is provided with a longer circuit path by matching with the isolation trench structure, so that the high-voltage semiconductor structure can help dissipate the high voltage, and the high-voltage semiconductor structure can maintain the high-voltage operation under the voltage of 1.8V or 3.3V. The high voltage semiconductor structure may be a fin field effect transistor.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 2 is a schematic diagram of a structure (i.e., a fin field effect transistor) of an embodiment of the high voltage semiconductor structure according to the present disclosure. The high voltage semiconductor structure includes: a first region 1 having a first conductivity type; a second region 2 of the first conductivity type and/or the second conductivity type located on the first region 1; a third region 3 located on the second region 2; the third region 3 has a conductivity type opposite to that of the second region 2 to which the third region 3 is projectively corresponding in the vertical direction; the third region 3 includes: a channel region 302 and a drift region 303; a source region 5 located on the second region 2 adjacent to one side of the third region 3, and a drain region 6 located on the second region 2 adjacent to the other side of the third region 3; the conductivity type of the source region 5 and the drain region 6 is the same as the conductivity type of the adjoining third region 3.
In this embodiment, the first region 1 may serve as a substrate structure of the high voltage semiconductor structure, and thus serves as a process platform for forming the high voltage semiconductor structure. Specifically, the first region 1 may include: a substrate layer 101 having a first conductivity type and an epitaxial layer 102 having the first conductivity type located on the substrate layer 101.
In other embodiments, the material of the substrate structure can also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, which can also be a silicon-on-insulator substrate, a germanium-on-insulator substrate, or a III-V compound substrate (e.g., a gallium nitride base or gallium arsenide substrate, etc.).
When the conductivity type of the first region 1 is P-type, the first region 1 is composed of a P-type heavily doped silicon substrate and a P-type lightly doped epitaxial layer 102. In one embodiment, the conductivity type of the first region 1 of the high voltage semiconductor structure is P-type, the first region 1 is doped with P-type impurity ions, and the P-type impurity ions may be one or more of boron ions, gallium ions and indium ions.
When the conductivity type of the first region 1 is N-type, the first region 1 is composed of a heavily N-type doped silicon substrate layer 101 and a lightly N-type doped silicon epitaxial layer 102. In one embodiment, the conductivity type of the first region 1 of the high voltage semiconductor structure is N-type, the first region 1 is doped with N-type impurity ions, and the N-type impurity ions are one or more of phosphorus ions, arsenic ions and antimony ions.
In this embodiment, the second region 2 is a Deep Well (DW), and the second region 2 is formed on the first region 1. The conductivity type of the second region 2 may be one or two. Specifically, deep wells of one or both conductivity types are formed on a silicon substrate structure. In one embodiment, the first region 1 is a P-type substrate structure on which an N-type deep well (DNW) is formed. In another embodiment, the first region 1 is a P-type substrate structure on which an adjacent N-type deep well and P-type deep well (DPW) are formed. In other embodiments, the first region 1 is an N-type substrate structure on which a P-type deep well (DPW) is formed.
In this case, the third region 3 is located on the second region 2 and has a conductivity type opposite to that of the second region 2. Wherein, the third area 3 includes: a channel region 302 and a drift region 303, the channel region 302 serving as a channel between a source and a drain, and a gate structure 4 is subsequently formed on the channel region 302. The drift region 303 may increase the voltage consumption of the high voltage semiconductor structure, enabling the high voltage semiconductor structure to maintain operation at higher voltages. In one embodiment, the third region 3 is located on the second region 2 of P-type conductivity, and the third region 3 is of N-type conductivity. In another embodiment, the third region 3 is located on the second region 2 of N-type conductivity, and the third region 3 is of P-type conductivity.
In this embodiment, a plurality of first trench structures 202 are formed in the second region 2 by using a mask process and an etching process, and at the same time, the third region 3 is separated into a plurality of fin structures 301. The plurality of first trench structures 202 divide the second region 2 into a plurality of conductive regions 201; one fin structure 301 is on each conductive region 201. The one or more predetermined regions in the fin structure 301 on each conductive region 201 are adjacent channel regions 302 and drift regions 303.
In addition, if the second region 2 of two different conductivity types is formed on the first region 1, the second trench structure 203 may be formed between the second region 2 of the first conductivity type and the second region 2 of the second conductivity type together when the first trench structure 202 is formed.
In one embodiment, the first trench structure 202 and the second trench structure 203 are Shallow Trench Isolations (STI), and the first trench structure 202 and the second trench structure 203 may be filled with an insulating material after the trench structures are formed. The insulator can be tetraethoxysilane TEOS, silicon dioxide and other materials.
In this scheme, a gate structure 4 is formed on the channel region 302 on each fin structure 301 in the third region 3. Specifically, a thin insulator layer 401 is first formed over the channel region 302 in the fin structure 301, and a gate layer 402 and a spacer layer 403 are then formed over the insulator layer 401, thereby forming a wrapped-around gate structure 4 over the fin structure 301, with the switching of the channel region 302 being controlled by the gate structure 4. The insulator layer 401 may be an oxide of silicon; the gate layer 402 may be made of polysilicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, amorphous carbon, or other materials; the spacer layer 403 may be formed using silicon oxide or silicon nitride. In one embodiment, the channel region 302 in the fin structure 301 is half-wrapped with silicon dioxide, and polysilicon is deposited on the silicon dioxide and silicon nitride is formed on the sides of the polysilicon.
In this embodiment, the conductivity type of the source region 5 and the drain region 6 is the same as the conductivity type of the adjacent third region 3. Specifically, the source region 5 is located at one side of the channel region 302 in the fin structure 301, and is adjacent to the channel region 302; the drain region 6 is located on one side of the drift region 303 in the fin structure 301 and abuts the drift region 303. The other side of the channel region 302 is adjacent to the other side of the drift region 303. In one embodiment, the fin structure 301 except for the channel region 302 and the drift region 303 is removed, and the source region 5 is formed on one side of the channel region 302 and the drain region 6 is formed on one side of the drift region 303 by epitaxial growth. The source region 5 and the drain region 6 have the same conductivity type as the fin structure 301 adjacent to both. For example, the second region 2 is N-type, the fin structure 301 on the second region 2 is P-type, and the source region 5 and the drain region 6 adjacent to the fin structure 301 are N-type. In the example where the second region 2 is P-type, the fin structure 301 on the second region 2 is N-type, and the source region 5 and the drain region 6 adjacent to the fin structure 301 are P-type. Wherein, the material of the source region 5 and the drain region 6 may be silicon germanium (SiGe). In addition, in this embodiment, the source region 5 and the drain region 6 may be designed to have a diamond structure.
Accordingly, as shown in fig. 15, the present aspect also provides a high voltage semiconductor device including: a plurality of high voltage semiconductor structures as described above arranged in an array. The high voltage semiconductor device can be applied to three-dimensional devices or equipment such as Static Random Access Memories (SRAMs) and logic equipment.
Correspondingly, the scheme also provides a manufacturing method of the high-voltage semiconductor structure. The high voltage semiconductor structure made by the method is capable of maintaining operation at high voltages. Fig. 2 to 11 are schematic structural diagrams of some embodiments of a method for manufacturing a high voltage semiconductor structure according to the present invention and corresponding steps. In particular, the amount of the solvent to be used,
fig. 3 is a flow chart of a method for manufacturing a high voltage semiconductor structure according to this embodiment. The method comprises the following steps:
step S1, forming a first region 1 having a first conductivity type;
step S2, forming a second region 2 having the first conductivity type and/or the second conductivity type on the first region 1;
a step S3 of forming a third region 3 having a conductivity type opposite to that of the second region 2 on the second region 2; the third region 3 includes: a channel region 302 and a drift region 303;
step S4, forming a gate structure 4 on the third region 3;
a step S5 of forming a source region 5 adjacent to one side of the third region 3 on the second region 2 and forming a drain region 6 adjacent to the other side of the third region 3 on the second region 2; the conductivity type of the source region 5 and the drain region 6 is the same as the conductivity type of the adjoining third region 3.
Next, a detailed description will be given of a specific process of the method for forming a semiconductor device according to the present embodiment, with reference to fig. 4 to 14.
As shown in fig. 4, in step S1, the first region 1 is a substrate structure, which includes: the substrate layer 101 and the epitaxial layer 102 are of the same conductivity type. In one embodiment, a wafer is provided, a first layer is heavily P-doped to form a P-type silicon substrate layer, and a second layer is lightly P-doped to form a P-type silicon epitaxial layer. In another embodiment, a wafer is provided, the first layer is heavily doped with N-type dopant to form an N-type silicon substrate layer, and the second layer is lightly doped with N-type dopant to form an N-type silicon epitaxial layer. In other embodiments, the material of the substrate structure can also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, which can also be a silicon-on-insulator substrate, a germanium-on-insulator substrate, or a III-V compound substrate (e.g., a gallium nitride base or gallium arsenide substrate, etc.). Wherein, the P-type impurity can be one or more of boron ion, gallium ion and indium ion. The N-type impurity can be one or more of phosphorus ion, arsenic ion and antimony ion.
In step S2, a second region 2 is formed on the first region 1, the second region 2 being a deep well. As shown in fig. 5, a deep well of one conductivity type may be formed on the first region 1. In one embodiment, the first region 1 is of P-type conductivity, and the second region 2 may be of N-type conductivity; alternatively, the first region 1 is of N-type conductivity and the second region 2 is of P-type conductivity. As shown in fig. 6, a deep well of two conductivity types may also be formed on the first region 1. In one embodiment, the first region 1 is of P-type conductivity, and adjacent P-type deep well and N-type deep well may be formed thereon at the same time. In another embodiment, the first region 1 is of P-type conductivity, and adjacent P-type deep well and N-type deep well may be formed thereon at the same time.
As shown in fig. 7, in step S3, a third region 3 is formed on the second region 2, the conductivity type of the third region 3 being opposite to that of the second region 2. Wherein predetermined regions in the third region 3 serve as the channel region 302 and the drift region 303. In an embodiment, the conductivity type of the second region 2 is P-type, and the third region 3 thereon forms the third region 3 of N-type conductivity by means of N-type light doping. In another embodiment, the conductivity type of the second region 2 is N-type, and the third region 3 thereon forms the third region 3 of P-type conductivity type by means of P-type light doping.
As shown in fig. 8, after the third region 3 is formed, the third region 3 needs to be separated into a plurality of fin structures 301, and meanwhile, a plurality of conductive regions 201 are formed on the second region 2, so as to prepare for the subsequent formation of the wrapped-around gate structure 4. Specifically, a plurality of second trench structures 203 arranged in a transverse array are formed in the second region 2 through the third region 3; wherein the direction in which the second region 2 having the first conductivity type and the second region 2 having the second conductivity type adjoin is a lateral direction; the second trench structure 203 divides the second region 2 into a plurality of conductive regions 201; while passing through the third region 3, the third region 3 is divided into a plurality of fin structures 301, one fin structure 301 being provided on each conductive region 201; covering a TEOS layer on the second region 2, the groove structure and the fin structure 301; the TEOS layer over the fin structures 301 and over the trenches is removed. The separation of the third region 3 and the division of the second region 2 are completed by one etching process, so that a plurality of conductive regions 201 on the second region 2 and a fin structure 301 on each conductive region 201 are formed.
In an embodiment, a first pattern layer (not shown in the figure) is formed on the surface of the third region 3, the first pattern layer has an opening exposing a portion of the third region 3, the exposed third region 3 is etched along the opening by using the first pattern layer as a mask until reaching a predetermined position in the second region 2, a plurality of first trench structures 202 are formed on the second region 2, and at the same time, the third region 3 is divided into a plurality of fin structures 301. The plurality of first trench structures 202 divides the second region 2 into a plurality of conductive regions 201, each conductive region 201 having a fin structure 301 thereon.
In addition, as shown in fig. 9, the first region 1 has the second region 2 of two different conductivity types, and the second trench structure 203 may be formed between the second region 2 of the first conductivity type and the second region 2 of the second conductivity type at the same time when the first trench structure 202 is formed. In an embodiment, the first pattern layer is a mask, and is provided with an opening for forming the second trench structure 203 in addition to the opening for forming the first trench structure 202, and the exposed third region 3 is etched along the opening for forming the second trench structure 203 until reaching a predetermined position at the boundary of the second regions 2 with different conductivity types, so as to form the second trench structure 203 on the second region 2. A part of the second trench structure 203 is located in the second region 2 of the first conductivity type and another part is located in the second region 2 of the second conductivity type. The first trench structure 202 and the second trench structure 203 may be STI trenches.
As shown in fig. 9, after the first trench structure 202 and the second trench structure 203 are formed, the first trench structure 202 and the second trench structure 203 are filled with an insulator. The insulator may be tetraethylorthosilicate TEOS, an oxide of silicon, a nitride of silicon, or the like.
In this embodiment, when the first trench structure 202 and the second trench structure 203 are filled, an insulator such as silicon nitride is formed on the fin structure 301, and the insulator needs to be removed to ensure that the subsequent processes are performed smoothly. In one embodiment, the removal of the insulator material on the fin structures 301 may be performed by a phosphorous oxide etch at a temperature of 140 ℃ for 20 minutes to remove the remaining silicon nitride on the fin structures 301.
After the fin structure 301 in the third region 3 is formed, the gate structure 4 needs to be formed in the channel region 302 in the fin structure 301. As shown in fig. 10, an etch stop layer 7 is formed on the fin structure 301; forming an insulator layer 401 over the trench structure and on the etch stop layer 7; a hard mask 8 and a bottom anti-reflection coating 9 are sequentially formed on the insulator layer 401. In one embodiment, a layer of approximately 20 angstroms thick is first grown over the exposed fin structures 301
Will act as an Etch stop layer 7(Etch-stop layer, ESL) for the fin structure 301. This etch stop layer 7 may provide etch stop protection between the fin structure 301 and the amorphous silicon layer. In one embodiment, after the insulator layer 401 is formed over the trench structure and on the etch stop layer 7, the surface of the insulator layer 401 is polished by a chemical mechanical polishing CMP process to make the surface more flat and smooth. In one embodiment, the insulation after polishingA relatively thick layer of amorphous carbon is deposited over layer 401 using a vapor deposition process and this layer of amorphous carbon serves as hard mask 8. Subsequently, a bottom anti-reflection coating 9 is formed on the hard mask 8.
As shown in fig. 11, the insulator layer 401 and the bottom anti-reflection coating 9 above the trench structure and on the fin structure 301 outside the predetermined region are removed; the predetermined region is a region on the fin structure 301 in the third region 3, which is used as a channel region 302 and a drift region 303; the BARC layer 9 on the insulator layer 401 in the predetermined region and the insulator on the drift region 303 in the fin structure 301 in the predetermined region are removed. In one embodiment, a thick photoresist layer is spun onto the wafer and patterned, then trimmed to the target dimensions, then the wafer is baked to give the resist some structural integrity, and then the resist is exposed and developed. Then, the resulting photoresist pattern is subjected to PEB treatment to finally define the photoresist pattern, and the photoresist is converted into a cross-linked imidized substance to resist etching. Next, the hard mask 8 is etched to the etching stop layer 7 on the fin structure 301; the photoresist is removed, the wafer is cleaned, the hard mask 8 under the photoresist is stripped, the insulator layer 401 (amorphous silicon) is continuously etched, a thin layer of insulator remains on the channel region 302, and the insulator layer 401 on the drift region 303 is etched away. Furthermore, when the first region 1 has the second regions 2 of two different conductivity types thereon, the above-described operations may be performed simultaneously, with the gate structures 4 being formed simultaneously for the two regions of different conductivity types.
As shown in fig. 12-1 and 12-2, a gate layer 402 is formed on an insulator layer 401; forming a spacer layer on the gate layer 402; the insulator layer 401 is removed on top of the gate layer 402 and over the drift region 303. In one embodiment, after cleaning the wafer, a vapor deposition process is used to grow a thickness of about 15 angstroms on the insulator layer 401
Gate layer 402 (polysilicon). Subsequently, a gate layer 402 is deposited to a thickness of about 500 angstroms
Spacer layer 403 (silicon nitride). After deposition is complete, the spacer layer 403 on top of the gate layer 402 is removed.
One problem with finfets fabricated in the manner described above is that there are two intersecting vertical structures for the gate layer 402 and the channel region 302. This means that during the spacer layer etch, spacers are left on the sidewalls of the fin structure 301 as well as on the sidewalls of the gate layer 402. Therefore, in this embodiment, as shown in fig. 13, the fin structure 301 except for the channel region 302 and the drift region 303 in the fin structure 301 is removed, and the source region 5 and the drain region 6 are formed near the channel region 302 and the drift region 303 again by epitaxial growth.
Removing the fin structures 301 outside the predetermined region; forming a source region 5 adjacent to the channel region 302 at one side of the channel region 302; a source region 5 adjoining the drift region 303 is formed on the drift region 303 side. In one embodiment, in the case of the second region 2 having two different conductivity types on the first region 1, i.e. including DNW and DPW, before the source region 5 and the drain region 6 are epitaxially grown on the DNW region, the DPW region is covered with a mask layer of silicon carbon nitride SiCN, and then the fin structure 301 except the channel region 302 and the drift region 303 in the fin structure 301 on each conductive region 201 in the DNW region is removed; subsequently, a silicon germanium (SiGe) source region 5 is formed by epitaxial growth on the side of the channel region 302 in the DNW region, and a silicon germanium (SiGe) drain region 6 is formed by epitaxial growth on the side of the drift region 303, thereby completing the fabrication of the source region 5 and the drain region 6 near the channel region 302 and the drift region 303 on each conductive region 201 on the DNW region. Before epitaxial growth of the source region 5 and the drain region 6 is carried out on the DPW region, a silicon carbon nitrogen SiCN mask layer, a bottom anti-reflection coating 9 and photoresist are required to be sequentially covered on the DNW region where the source region 5 and the drain region 6 are formed and a drift region 303 on the DPW region, and then the fin structure 301 outside a channel region 302 and the drift region 303 in the fin structure 301 on each conductive region 201 in the DPW region and the silicon carbon nitrogen SiCN mask layer and the bottom anti-reflection coating 9 covered on the fin structure 301 are removed; subsequently, a silicon germanium (SiGe) source region 5 is formed by epitaxial growth on the side of the channel region 302 in the DPW region, and a silicon germanium (SiGe) drain region 6 is formed by epitaxial growth on the side of the drift region 303, thereby completing the fabrication of the source region 5 and the drain region 6 near the channel region 302 and the drift region 303 on each of the conductive regions 201 on the DNW region. As shown in fig. 14, the source region 5 and the drain region 6 in this embodiment are both diamond-shaped structures, and the structure diagram of the drain region 6 is not shown, which is a front view of the high-voltage semiconductor structure.
In addition, if on the same conductive region 201, there are a plurality of adjacent channel regions 302 and drift regions 303; alternatively, if there are a plurality of adjacent channel regions 302 and drift regions 303 over different conductive regions in the same deep well region, a plurality of source regions 5 and drain regions 6 may be formed at once in the manner described above.
And finally, removing the SiCN mask layer and the bottom anti-reflection coating 9 removed from the second region 2 of the first conductivity type and the second region 2 of the first conductivity type to finish the manufacturing process of the high-voltage semiconductor structure and form the high-voltage semiconductor structure or device.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (21)
1. A semiconductor structure, comprising:
a first region having a first conductivity type;
a second region of the first conductivity type and/or the second conductivity type on the first region;
a third region located on the second region, the third region having a conductivity type opposite to a conductivity type of the second region to which the third region is projectively corresponding in a vertical direction; the third region includes: a channel region and a drift region;
the source region is positioned on the second region and is adjacent to one side of the third region, and the drain region is positioned on the second region and is adjacent to the other side of the third region; the conductivity type of the source region and the drain region is the same as that of the adjacent third region.
2. The high voltage semiconductor structure of claim 1, wherein the first conductivity type is P-type and the second conductivity type is N-type; or, the first conductivity type is N-type, and the second conductivity type is P-type.
3. The high-voltage semiconductor structure according to claim 1 or 2, wherein the second region has a plurality of first trench structures uniformly arranged therein;
the first groove structure divides the second area into a plurality of conductive areas;
each conductive region has a portion of the third region thereon; the part of the third area is a plurality of fin structures formed by dividing the third area;
the source region and the drain region abut on both sides of the fin structure on the conductive region in a direction of the first trench structure.
4. The high voltage semiconductor structure of claim 1, wherein the first region comprises: a substrate layer having a first conductivity type and an epitaxial layer having the first conductivity type on the substrate.
5. The high voltage semiconductor structure of claim 3, wherein a second trench structure is provided between the second region of the first conductivity type and the second region of the second conductivity type.
6. The high voltage semiconductor structure of claim 3, wherein the source region is adjacent to the channel region; the drain region is adjacent to the drift region.
7. The high voltage semiconductor structure of claim 3, further comprising: a gate structure located over the channel region in the third region;
the gate structure includes: a gate insulating layer on the third region, a gate on the gate insulating layer, and spacers on sides of the gate.
8. The high voltage semiconductor structure of claim 5, wherein the first trench structure and/or the second trench structure is filled with TEOS.
9. The high voltage semiconductor structure of claim 7, wherein the source and/or drain regions are diamond shaped structures.
10. A semiconductor device, comprising: a high voltage semiconductor structure as claimed in any one of claims 1 to 9.
11. A method of fabricating a semiconductor structure, the method comprising the steps of:
forming a first region having a first conductivity type;
forming a second region having a first conductive type and/or a second conductive type on the first region;
forming a third region on the second region; the third region has a conductivity type opposite to that of the second region corresponding to the third region projected in the vertical direction; the third region includes: a channel region and a drift region;
forming a source region adjacent to one side of the third region on the second region, and forming a drain region adjacent to the other side of the third region on the second region; the conductivity type of the source region and the drain region is the same as that of the adjacent third region.
12. The method of claim 11, wherein the first conductivity type is P-type and the second conductivity type is N-type; or, the first conductivity type is N-type, and the second conductivity type is P-type.
13. The method of claim 11, wherein the step of forming the first region having the first conductivity type comprises:
forming a substrate layer having a first conductivity type;
forming an epitaxial layer having a first conductivity type on the substrate; wherein the second region is formed on the epitaxial layer.
14. The method of claim 11, wherein the step of forming a third region on the second region having an opposite conductivity type to the second region is followed by:
penetrating through the third region, and forming a plurality of second groove structures arranged in a transverse array manner in the second region; wherein the direction in which the second region having the first conductivity type and the second region having the second conductivity type adjoin is a lateral direction;
the second groove structure divides the second area into a plurality of conductive areas;
the third region is divided into a plurality of fin structures while penetrating through the third region, and each conductive region is provided with one fin structure;
covering a TEOS layer on the second region, the groove structure and the fin structure;
and removing the TEOS layer on the fin structure and above the groove.
15. The method of claim 14, wherein the step of forming a plurality of second trench structures arranged in a lateral array in the second region through the third region is followed by:
forming a second trench structure between the second region of the first conductivity type and the second region of the second conductivity type through the third region;
a portion of the first trench structure is located within the second region of the first conductivity type and another portion thereof is located within the second region of the second conductivity type.
16. The method of claim 14, wherein the step of forming a source region on the second region adjacent one side of the third region and a drain region on the second region adjacent the other side of the third region comprises, prior to the step of forming a drain region on the second region adjacent the other side of the third region: and forming a gate structure on the third region.
17. The method of claim 16, wherein the step of forming a gate structure over the third region comprises: forming an etch stop layer on the fin structure;
forming an insulator layer over the trench structure and on the etch stop layer;
sequentially forming a hard mask and a bottom anti-reflection coating on the insulator layer;
removing the insulator layer, the hard mask and the bottom anti-reflection coating above the groove structure and on the fin structure outside the preset area;
the predetermined region is a region serving as a channel region and a drift region on the fin structure in the third region;
removing the bottom anti-reflection coating on the insulator layer in the preset area and the insulator on the drift region in the fin structure in the preset area;
forming a gate layer on top of the insulator layer;
forming a spacer layer on the gate layer;
the insulator layer on top of the gate layer and over the drift region is removed.
18. The method of claim 17, wherein the step of removing the BARC layer on the insulator layer in the predetermined region and the insulator on the drift region in the fin structure in the predetermined region comprises:
patterning the hard mask after removing the bottom anti-reflection coating;
reserving the hard mask above the channel region, and removing the hard mask above the drift region;
and then removing the bottom anti-reflection coating of the predetermined area.
19. The method of claim 17, wherein forming a source region on the second region adjacent one side of the third region, and forming a drain region on the second region adjacent the other side of the third region comprises:
removing the fin structures outside the preset area;
forming a source region adjacent to the channel region on one side of the channel region;
a source region is formed adjacent to the drift region on one side of the drift region.
20. The method of claim 19, wherein the step of removing the fin structure outside the predetermined area is preceded by: when a source region and a drain region are formed above the second region of the first conductivity type, the drift regions in the fin structures on the second region of the second conductivity type and the second region of the first conductivity type cover the SiCN mask layer and the bottom anti-reflection coating; when a source region and a drain region are formed above the second region of the second conductivity type, the drift region in the fin structure on the second region of the first conductivity type and on the second region of the second conductivity type covers the SiCN mask layer and the BARC layer.
21. The method of claim 19, wherein the step of forming a source region on the second region adjacent one side of the third region and a drain region on the second region adjacent the other side of the third region is followed by the step of:
and removing the SiCN mask layer and the bottom anti-reflection coating above the second region of the first conduction type and the second region of the first conduction type.
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