CN114284302A - Array substrate, display panel and display device - Google Patents
Array substrate, display panel and display device Download PDFInfo
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- CN114284302A CN114284302A CN202111615525.2A CN202111615525A CN114284302A CN 114284302 A CN114284302 A CN 114284302A CN 202111615525 A CN202111615525 A CN 202111615525A CN 114284302 A CN114284302 A CN 114284302A
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- 239000000758 substrate Substances 0.000 title claims abstract description 67
- 229910052751 metal Inorganic materials 0.000 claims abstract description 101
- 239000002184 metal Substances 0.000 claims abstract description 101
- 239000004020 conductor Substances 0.000 claims abstract description 42
- 230000007704 transition Effects 0.000 claims description 14
- 230000007423 decrease Effects 0.000 claims description 3
- 230000003247 decreasing effect Effects 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 12
- 230000008054 signal transmission Effects 0.000 abstract description 4
- 238000005530 etching Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 7
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000012876 topography Methods 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910021389 graphene Inorganic materials 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 1
- 229910001887 tin oxide Inorganic materials 0.000 description 1
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
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Abstract
The application provides an array substrate, display panel and display device, array substrate includes: a substrate having a display region and a non-display region; the pixel unit is arranged in the display area; the driving chip is arranged in the non-display area, a wiring area is formed between the driving chip and the display area, and the wiring area comprises a central conductor area and fan-out areas which are respectively arranged on two sides of the central conductor area; the fan-out structure is arranged in the wiring area so as to electrically connect the driving chip with the pixel unit; the fan-out structure comprises a central wire arranged in the central wire area and a plurality of fan-out wires arranged in the fan-out area; the length of the central conductor is less than that of each fan-out conductor; the fan-out conductor comprises a first metal layer, a second metal layer and an insulating layer positioned between the first metal layer and the second metal layer; the insulating layer is provided with a conductive hole, and the first metal layer and the second metal layer are conducted in parallel through the conductive hole. The array substrate can reduce the delay degree of signal transmission so as to improve the display effect of a display area.
Description
Technical Field
The application belongs to the technical field of display, and particularly relates to an array substrate, a display panel and a display device.
Background
The display substrate comprises a display area and a driving circuit area (or called a peripheral circuit area and a peripheral circuit area); the driving circuit area is provided with a driving circuit to output signals; a display structure layer is arranged in the display area to display a picture; and a lead for transmitting corresponding signals to the display area is arranged between the two areas.
In order to increase the area of the display region, the conductive lines between the two regions are designed to be concentrated toward the driving circuit region having a smaller area, so that the conductive lines between the two regions are gathered into a Fan-shaped structure, which is generally called a Fan-out region (i.e., Fan-out).
In the fan-out area, each conducting wire has different length due to different relative positions between each conducting wire and the driving circuit area. Generally, the length of the wire in the middle of the sector is the shortest, and the length of the wire on both sides of the sector is longer. Since each conductive line is usually made of the same conductive material (i.e., has the same resistivity) and is formed by the same patterning process, the line width and the thickness of each conductive line are correspondingly equal (or very close), so that the resistance of each conductive line increases with the increase of the length of each conductive line.
Due to the length difference between different conducting wires, a larger impedance difference (namely, a resistance difference value Rmax-Rmin) exists between the conducting wires, and the larger the length difference between the conducting wires is, the larger the impedance difference is. When displaying, signal transmission delay occurs, which causes color shift, uneven brightness (i.e. Mura) and other defects of the displayed picture, and affects the display effect.
Disclosure of Invention
The embodiment of the application provides an array substrate, a display panel and a display device, and aims to solve the problem that the display effect of the existing display panel is poor.
In a first aspect, an embodiment of the present application provides an array substrate, including:
a substrate having a display region and a non-display region;
the pixel unit is arranged in the display area;
the driving chip is arranged in the non-display area, a wiring area is formed between the driving chip and the display area, and the wiring area comprises a central conductor area and fan-out areas which are respectively arranged on two sides of the central conductor area;
the fan-out structure is arranged in the wiring area so as to electrically connect the driving chip with the pixel unit; the fan-out structure comprises a central wire arranged in the central wire area and a plurality of fan-out wires arranged in the fan-out area; the length of the central conductor is less than that of each fan-out conductor;
the fan-out conductor comprises a first metal layer, a second metal layer and an insulating layer positioned between the first metal layer and the second metal layer; the insulating layer is provided with a conductive hole, and the first metal layer and the second metal layer are conducted in parallel through the conductive hole.
Optionally, the projection portions of the first metal layer and the second metal layer on the substrate are staggered.
Optionally, a projection of the first metal layer on the substrate is staggered from a projection of the second metal layer on the substrate by a width of less than or equal to 3 μm.
Optionally, the array substrate further includes a metal flat line, the metal flat line is disposed between the fan-out wire and the central wire, and the metal flat line is parallel to the central wire.
Optionally, the extending length of each fan-out conductor in the fan-out area decreases progressively along the direction away from the central conductor.
Optionally, the routing area further includes a fan-out compensation area, and the fan-out compensation area is located on one side of the fan-out area close to the display area; the fan-out wires extend from the fan-out area to the fan-out compensation area, and the extending lengths of the fan-out wires of the fan-out area in the fan-out compensation area are sequentially decreased in the direction away from the central wire.
Optionally, the fan-out region, the fan-out compensation region and the central conductor region together enclose a region to be flattened, and the array substrate further includes a metal flattening layer, where the metal flattening layer is disposed in the region to be flattened.
Optionally, the routing area further includes a transition area, and the transition area is located between the fan-out area and the fan-out compensation area; the fan-out conductor extends from the fan-out area to the transition area and then extends from the transition area to the fan-out compensation area.
In a second aspect, an embodiment of the present application further provides a display panel, where the display panel includes the array substrate as described above.
In a third aspect, embodiments of the present application further provide a display device, where the display device includes the display panel described above.
According to the array substrate provided by the embodiment of the application, each fan-out wire is arranged into a first metal layer, an insulating layer and a second metal layer which are stacked, and the first metal layer and the second metal layer are conducted in parallel through the conductive holes in the insulating layer; by utilizing the principle that the total resistance of the plurality of resistors after being connected in parallel is smaller than any one of the resistors, the overall impedance of the fan-out wire is reduced after the first metal layer and the second metal layer are connected in parallel, so that the impedance difference between the longer fan-out wire and the shorter central wire can be reduced, the delay degree of signal transmission can be reduced, and the display effect of the display area can be improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings used in the description of the embodiments will be briefly described below. It is obvious that the drawings in the following description are only some embodiments of the application, and that other drawings can be derived from these drawings by a person skilled in the art without inventive effort.
For a more complete understanding of the present application and its advantages, reference is now made to the following descriptions taken in conjunction with the accompanying drawings. Wherein like reference numerals refer to like parts in the following description.
Fig. 1 is a schematic plan view of an array substrate according to an embodiment of the present application.
Fig. 2 is a schematic plan view of a wiring region in the array substrate shown in fig. 1.
Fig. 3 is a cross-sectional view of a fan-out wire in the array substrate shown in fig. 1.
Fig. 4 is a schematic projection view of a fan-out wire in the array substrate shown in fig. 1.
| Reference numerals | Name (R) | Reference numerals | Name (R) | Reference numerals | Name (R) |
| 100 | |
10 | |
11 | |
| 12 | Non-display |
20 | |
30 | |
| 13 | |
131 | |
132 | Fan-out |
| 41 | |
42 | Fan-out conductor | 421 | A |
| 422 | |
423 | |
424 | |
| 50 | Metal |
133 | Fan- |
134 | |
| 60 | Metallic planarization layer |
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The embodiment of the application provides an array substrate 100, a display panel and a display device, so as to solve the problem that the display effect of the existing display panel is not good. Which will be described below with reference to the accompanying drawings.
The array substrate 100 provided in the embodiment of the present application can be applied to manufacture a display panel, for example, refer to fig. 1, fig. 2, and fig. 3. Fig. 1 is a schematic plan view of an array substrate 100 according to an embodiment of the present disclosure. Fig. 2 is a schematic plan view of the routing area 13 in the array substrate 100 shown in fig. 1. Fig. 3 is a cross-sectional view of a fan-out wire 42 in the array substrate 100 shown in fig. 1.
The array substrate 100 includes a substrate 10, a pixel unit 20, a driving chip 30, and a fan-out structure. The substrate 10 has a display region 11 and a non-display region 1211. The pixel unit 20 is disposed in the display area 11. The driving chip 30 is disposed in the non-display area 1211, a wiring area 13 is formed between the driving chip 30 and the display area 11, and the wiring area 13 includes a central conductive line area 131 and fan-out areas 132 respectively disposed at two sides of the central conductive line area 131. The fan-out structure is disposed in the routing area 13 to electrically connect the driving chip 30 and the pixel unit 20. The fan-out structure comprises a central conductor 41 arranged in a central conductor area 131, and a plurality of fan-out conductors 42 arranged in a fan-out area 132; the length of the central conductor 41 is less than the length of each fan-out conductor 42. The fan-out conductor 42 includes a first metal layer 421, a second metal layer 422, and an insulating layer 423 between the first metal layer 421 and the second metal layer 422; the insulating layer 423 is formed with a conductive via 424, and the first metal layer 421 and the second metal layer 422 are conducted in parallel through the conductive via 424.
The substrate 10 is provided with a plurality of data lines and a plurality of scan lines, and the data lines and the scan lines are criss-cross to define a plurality of pixel regions. The number of the pixel units 20 is plural, and the plural pixel units 20 are distributed in plural pixel regions. The driving chips 30 are connected to the plurality of data lines in a one-to-one correspondence through the fan-out structure to charge the corresponding pixel units 20. The fan-out structure includes a center wire 41 and a plurality of fan-out wires 42, the center wire 41 is connected to the middle of the driving chip 30; the fan-out wires 42 are divided into two groups, and the two groups of fan-out wires 42 are respectively disposed at two sides of the central wire 41 and connected to two sides of the middle portion of the driving chip 30. The central wire 41 may extend linearly or may extend in a meandering manner, which is not limited herein. The fan-out wires 42 may extend linearly or may extend in a meandering manner, which is not limited herein. The center conductive lines 41 and the fan-out conductive lines 42 are arranged in the width direction, and the line widths of the center conductive lines 41 and the fan-out conductive lines 42 are the same to facilitate the collective processing formation.
The first metal layer 421 and the second metal layer 422 of the fan-out conductor 42 may be made of the same material, or may be made of different materials, which is not limited herein. The first metal layer 421, the insulating layer 423, and the second metal layer 422 are stacked in the thickness direction of the substrate 10. The insulating layer 423 is used to separate the first metal layer 421 from the second metal layer 422, so as to prevent the first metal layer 421 and the second metal layer 422 from being directly merged. The conductive vias 424 are used for electrically connecting the first metal layer 421 and the second metal layer 422; specifically, the walls of the conductive holes 424 may be covered with a conductive film to electrically connect the first metal layer 421 and the second metal layer 422. The conductive film may be formed of at least one of ITO (Indium tin Oxide), IZO (Indium Zinc Oxide), FTO (Fluorine-Doped tin Oxide), and graphene. By utilizing the principle that the total resistance of a plurality of resistors connected in parallel is smaller than any one of the resistors, the first metal layer 421 and the second metal layer 422 are connected in parallel, so that the resistance of the fan-out wire 42 can be effectively reduced. In order to avoid the resistance of the fan-out wires 42 being reduced to be smaller than the center wires 41, the length of the center wires 41 is set to be smaller than any of the fan-out wires 42. The greater the wire length, the greater the resistance, and therefore the effective balance of the resistance of the center wire 41 and the fan-out wire 42.
In the array substrate 100 provided in the embodiment of the present application, each fan-out wire 42 is provided as a first metal layer 421, an insulating layer 423, and a second metal layer 422 that are stacked, and the first metal layer 421 and the second metal layer 422 are conducted in parallel through a conductive hole 424 on the insulating layer 423; by using the principle that the total resistance of the plurality of resistors connected in parallel is smaller than any one of the resistors, after the first metal layer 421 and the second metal layer 422 are connected in parallel, the overall impedance of the fan-out wire 42 is reduced, so that the impedance difference between the longer fan-out wire 42 and the shorter central wire 41 can be reduced, the delay degree of signal transmission can be reduced, and the display effect of the display area 11 can be improved.
In the process of manufacturing the center wires 41 and the fan-out wires 42, two metal layers and the insulating layer 423 located between the two metal layers may be laid on the substrate 10, and then the first metal layer 421, the second metal layer 422 and the insulating layer 423 of the fan-out wires 42 may be formed by etching on the two metal layers and the insulating layer 423, respectively. It will be appreciated that the center conductor 41 formed in this manner also has a three-layer structure, and therefore, one of the metal layers of the center conductor 41 needs to be disconnected during the wiring process.
For example, referring to fig. 4, fig. 4 is a schematic projection view of the fan-out wire 42 in the array substrate 100 shown in fig. 1. The projection parts of the first metal layer 421 and the second metal layer 422 on the substrate 10 are staggered. In combination with the above embodiment of forming the fan-out wire 42 by the etching process, the etching amount of the edge of the trace may be uneven due to the difference in layer height during the etching process of the first metal layer 421 and the second metal layer 422, and if the first metal layer 421 and the second metal layer 422 are completely overlapped, the final etching effect may be affected. Therefore, the projection parts of the first metal layer 421 and the second metal layer 422 on the substrate 10 are staggered, so that the etching amount of the first metal layer 421 and the second metal layer 422 at the edge of the trace in the etching process can be more balanced, and the finally formed trace effect can be improved. Specifically, the projection of the first metal layer 421 on the substrate 10 is shifted from the projection of the second metal layer 422 on the substrate 10 by a width d of less than or equal to 3 μm. The width d of the staggered portion, i.e. the distance between the edge of the first metal layer 421 and the edge of the second metal layer 422, may be a distance in the width direction of the fan-out wire 42, or may be a distance in the length direction of the fan-out wire 42. Setting the pitch to not more than μm can reduce the occupied area of each fan-out conductor 42 in the fan-out area 132, thereby improving the effective utilization of the fan-out area 132.
Illustratively, as shown in fig. 2, the array substrate 100 further includes a metal flat line 50, the metal flat line 50 is disposed between the fan-out conductive line 42 and the central conductive line 41, and the metal flat line 50 is parallel to the central conductive line 41. The central wire 41 extends linearly, and the fan-out wire 42 may extend in an arcuate meandering manner, so that the total length of the fan-out wire 42 is greater than that of the central wire 41, thereby compensating for the impedance difference between the fan-out wire 42 and the central wire 41 caused by the parallel connection of the first metal layer 421 and the second metal layer 422. Since the fan-out wire 42 extends in a bow-shaped meandering manner, the routing width of the fan-out wire 42 is larger than that of the central wire 41; this results in low land areas formed between two sides of the central conductive line 41 and the adjacent fan-out conductive lines 42 on the substrate 10, which results in uneven array substrate 100, uneven array substrate 100 may cause uneven light emission of the display panel, and finally, display effect is affected. Therefore, the metal flat lines 50 parallel to the central conductive line 41 are disposed on both sides of the central conductive line 41, so that the overall topography of the array substrate 100 can be more flat, and the light emitting effect can be improved. It should be noted that the metal flat line 50 is not electrically connected to the driving chip 30 or the pixel unit 20.
Illustratively, as shown in fig. 2, the extension length of each fan-out conductor 42 in the fan-out area 132 decreases in a direction away from the central conductor 41. In the fan-out area 132, the fan-out wires 42 closer to the central wire 41 have longer routing lengths, so as to reduce the difference in routing lengths of the wires extending from the driving chip 30 to the display area 11, thereby reducing the impedance difference between any two fan-out wires 42 and improving the final display effect of the display panel.
Illustratively, as shown in fig. 2, the routing area 13 further includes a fan-out compensation area 133, where the fan-out compensation area 133 is located on a side of the fan-out area 132 close to the display area 11; the fan-out wires 42 extend from the fan-out area 132 to the fan-out compensation area 133, and the extending length of each fan-out wire 42 of the fan-out area 132 in the fan-out compensation area 133 is gradually reduced in the direction away from the central wire 41. As can be seen from the above embodiments, the closer the fan-out conductor 42 is to the central conductor 41, the longer the required routing length is. Therefore, for the fan-out wires 42 closer to the central wire 41 in the fan-out area 132, taking the fan-out wires 42 adjacent to the central wire 41 as an example, the required routing length of the fan-out wires 42 is the longest. The fan-out area 132 does not have enough area for it to extend, so the fan-out line 42 needs to continue to extend in the fan-out compensation area 133 to reach the predetermined length. For the fan-out wires 42 in the fan-out area 132 further away from the central wire 41, taking the fan-out wire 42 farthest from the central wire 41 as an example, the required routing length of the fan-out wire 42 is shortest, so that the fan-out compensation area 133 may not need to be extended to lengthen the length. That is, the longer the fan-out line 42 is from the center line 41, the shorter the extended length of the fan-out compensation region 133 is, so that the occupied space of the fan-out compensation region 133 can be reduced, thereby leaving the routing space for the fan-out line 42 closer to the center line 41. Therefore, for the fan-out wires 42 closer to the central wire 41, the routing width of the fan-out compensation area 133 can be increased appropriately to effectively extend the total length thereof. That is, the routing width of each fan-out conductor 42 at the fan-out compensation region 133 is greater than the routing width at the fan-out region 132.
Illustratively, as shown in fig. 2, the routing area 13 further includes a transition area 134, and the transition area 134 is located between the fan-out area 132 and the fan-out compensation area 133; the fan-out conductor 42 extends from the fan-out region 132 to the transition region 134 and then from the transition region 134 to the fan-out compensation region 133. The transition region 134 is used for orderly arranging the fan-out wires 42 of the fan-out region 132 before entering the fan-out compensation region 133, so as to avoid the crossing of a plurality of fan-out wires 42 in the fan-out compensation region 133, thereby ensuring the routing order of the fan-out wires 42.
Illustratively, as shown in fig. 2, the fan-out region 132, the fan-out compensation region 133 and the central line region 131 together enclose a region to be planarized, and the array substrate 100 further includes a metal planarization layer 60, where the metal planarization layer 60 is disposed in the region to be planarized. The number of the areas to be flattened is two, and the two areas to be flattened are arranged on two sides of the central lead 41. The number of the metal flat layers 60 is two, and the two metal flat layers 60 are respectively arranged in two regions to be flat. The metal planarization layer 60 can fill up the topographic height difference generated in the region to be planarized, so that the overall topography of the array substrate 100 is more planar, thereby further improving the light emitting effect.
On the basis of the foregoing embodiments, another aspect of the embodiments of the present invention further provides a display panel, which includes the array substrate 100 provided in the foregoing embodiments. The display panel may be, for example, a liquid crystal panel or an OLED panel. When the display panel is a liquid crystal panel, the display panel further includes a color film substrate 10 which is paired with the array substrate 100. When the display panel is an OLED panel, the display panel further comprises a packaging layer, a polarizer layer and other structures.
Further, in another aspect, an embodiment of the present invention further provides a display device, including the display panel described above. The display device can be specifically used for products or components with any display function, such as a display, a television, a mobile phone, a tablet computer, a navigator, a digital photo frame, a wearable display product (such as a smart watch) and the like. For example, when the display panel is a liquid crystal panel, the display device may further include a backlight module for providing backlight, and the specific structure may refer to related technologies, which is not described in detail herein.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
In the description of the present application, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. The array substrate provided by the embodiments of the present application is described in detail above, and the principles and embodiments of the present application are explained herein by applying specific examples, and the description of the embodiments is only used to help understanding the method and the core concept of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (10)
1. An array substrate, comprising:
a substrate having a display region and a non-display region;
the pixel unit is arranged in the display area;
the driving chip is arranged in the non-display area, a wiring area is formed between the driving chip and the display area, and the wiring area comprises a central conductor area and fan-out areas which are respectively arranged on two sides of the central conductor area;
the fan-out structure is arranged in the wiring area so as to electrically connect the driving chip with the pixel unit; the fan-out structure comprises a central wire arranged in the central wire area and a plurality of fan-out wires arranged in the fan-out area; the length of the central conductor is less than that of each fan-out conductor;
the fan-out conductor comprises a first metal layer, a second metal layer and an insulating layer positioned between the first metal layer and the second metal layer; the insulating layer is provided with a conductive hole, and the first metal layer and the second metal layer are conducted in parallel through the conductive hole.
2. The array substrate of claim 1, wherein the projections of the first and second metal layers on the substrate are staggered.
3. The array substrate of claim 2, wherein the projection of the first metal layer on the substrate is staggered from the projection of the second metal layer on the substrate by a width of less than or equal to 3 μm.
4. The array substrate of any one of claims 1 to 3, wherein the array substrate further comprises a metal flat line, the metal flat line is disposed between the fan-out conductive line and the central conductive line, and the metal flat line is parallel to the central conductive line.
5. The array substrate of any one of claims 1 to 3, wherein the extension length of each fan-out conductor in the fan-out area decreases in a direction away from the central conductor.
6. The array substrate of claim 1, wherein the routing area further comprises a fan-out compensation area, and the fan-out compensation area is located on one side of the fan-out area close to the display area; the fan-out wires extend from the fan-out area to the fan-out compensation area, and the extending lengths of the fan-out wires of the fan-out area in the fan-out compensation area are sequentially decreased in the direction away from the central wire.
7. The array substrate of claim 6, wherein the fan-out region, the fan-out compensation region and the central conductive line region together enclose a region to be planarized, and the array substrate further comprises a metal planarization layer disposed in the region to be planarized.
8. The array substrate of claim 6, wherein the routing region further comprises a transition region, the transition region being located between the fan-out region and a fan-out compensation region; the fan-out conductor extends from the fan-out area to the transition area and then extends from the transition area to the fan-out compensation area.
9. A display panel comprising the array substrate according to any one of claims 1 to 8.
10. A display device characterized by comprising the display panel according to claim 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111615525.2A CN114284302A (en) | 2021-12-27 | 2021-12-27 | Array substrate, display panel and display device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111615525.2A CN114284302A (en) | 2021-12-27 | 2021-12-27 | Array substrate, display panel and display device |
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| CN114284302A true CN114284302A (en) | 2022-04-05 |
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| CN202111615525.2A Pending CN114284302A (en) | 2021-12-27 | 2021-12-27 | Array substrate, display panel and display device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115223450A (en) * | 2022-07-25 | 2022-10-21 | 京东方科技集团股份有限公司 | Display panel, preparation method thereof and display device |
| CN115830995A (en) * | 2022-12-29 | 2023-03-21 | Tcl华星光电技术有限公司 | Display panel |
-
2021
- 2021-12-27 CN CN202111615525.2A patent/CN114284302A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115223450A (en) * | 2022-07-25 | 2022-10-21 | 京东方科技集团股份有限公司 | Display panel, preparation method thereof and display device |
| CN115223450B (en) * | 2022-07-25 | 2023-11-14 | 京东方科技集团股份有限公司 | Display panel, preparation method thereof and display device |
| CN115830995A (en) * | 2022-12-29 | 2023-03-21 | Tcl华星光电技术有限公司 | Display panel |
| CN115830995B (en) * | 2022-12-29 | 2024-06-11 | Tcl华星光电技术有限公司 | Display panel |
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