CN114281251A

CN114281251A - Data distribution and reprogramming optimization method for 3D TLC flash memory

Info

Publication number: CN114281251A
Application number: CN202111506480.5A
Authority: CN
Inventors: 龙林波; 黄金鹏; 蒋溢; 彭崎翔; 郑健聪
Original assignee: Chongqing University of Post and Telecommunications
Current assignee: Chongqing University of Post and Telecommunications
Priority date: 2021-12-10
Filing date: 2021-12-10
Publication date: 2022-04-05
Anticipated expiration: 2041-12-10
Also published as: CN114281251B

Abstract

The invention relates to a data distribution and reprogramming optimization method for a 3D TLC flash memory, and belongs to the technical field of flash memory performance. The method comprises the following steps: s1: caching the temporarily accessed request data by means of a flash memory controller buffer area, and dividing the data into cold and hot read-write data according to the access characteristics of the request data; s2: classifying the hot-written data according to the heat of the hot-written data, and establishing a multi-level heat linked list; s3: according to the type and the heat degree of the request data, combining two hot write data with the highest heat degree and one hot read data, and respectively storing the two hot write data and the one hot read data in CSB (CSB), LSB (least significant bit) and MSB (most significant bit) pages of a word line; s4: and designing a reprogramming method based on the number of the limited layers according to the number of the limited layers of the 3D flash memory reprogramming. The invention provides a corresponding data distribution algorithm and reprogramming, realizes a flash memory controller layer and improves the read-write performance of a flash memory.

Description

Data distribution and reprogramming optimization method for 3D TLC flash memory

Technical Field

The invention belongs to the technical field of flash memory performance, and relates to a data distribution and reprogramming optimization method for a 3D TLC flash memory.

Background

With the advent of the big data era, higher requirements are put on the capacity, performance, reliability and other aspects of the storage system. In a conventional memory system, a flat flash memory is mainly used. Unlike two-dimensional flash memory, three-dimensional flash memory increases capacity by stacking flash memory cells in a vertical direction. A typical three-dimensional flash block is made up of hundreds of layers. Typically, each wordline contains 64K to 128K flash cells, which may be SLC (single layer cell mode), MLC (double layer cell mode), TLC (double triple layer cell mode), or QLC (four layer cell mode). A flash memory cell is a floating gate transistor that can store different charges in the floating gate, resulting in different voltages. The range of voltages may be divided into a plurality of voltage intervals to represent different values. In recent years, advanced memory devices are now based on 3D flash memory due to the better performance and storage density of three-dimensional stacked (3D) flash memory. Therefore, how to optimize the 3D flash memory becomes a research hotspot in the storage field at present.

The read time delay is different for reading different positions of data on the flash memory cells of LSB (least significant bit), CSB (middle significant bit) and MSB (most significant bit). To reduce the number of times that the CSB or MSB voltages are identified if the data on the LSB or CSB is invalid, an invalid data sensing (IDA) encoding technique is designed to incorporate the repeated voltage states. As shown in FIG. 3, if the LSB and CSB bits are invalid, the voltage states P1, P2, and P5 may move to P5, while P0, P3, and P4 may move to P7. Likewise, if the LSB bit is invalid, P1, P2, P3, or P4 may be moved to P8, P7, P6, or P5, respectively. This may cause the read delay of the CSB page to approach the read delay of the LSB page, and the read delay of the MSB page to approach the read delay of the CSB page or LSB page, respectively. And its validity is limited by the location of invalid data, which is likely to be present on LSB, CSB and SLC pages the same.

After experimental verification, it is found that a considerable proportion of data is frequently updated, and the data with larger hot reading accounts for a large proportion of the data, that is, a part of the data is updated in a shorter time, and the prior art has no technology for optimizing and improving the aspect.

Disclosure of Invention

In view of the above, the present invention provides a data distribution and reprogramming optimization method for a 3D TLC flash memory. Through cold and hot data identification, cold and hot distinguishing is carried out on the data, and the distribution mode of the data is modified, so that the performance of the traditional reprogramming method is optimized.

In order to achieve the purpose, the invention provides the following technical scheme:

a data distribution and reprogramming optimization method for a 3D TLC flash memory comprises the following steps:

s1: caching the temporarily accessed request data by means of a buffer area of a flash memory controller, and dividing the data into hot read data, hot write data, cold read data and cold write data according to the access characteristics of the request data;

s2: according to the heat degree of the hot writing data, further classifying the hot writing data, and establishing a multi-level heat degree linked list, wherein the higher the level of the linked list is, the higher the heat degree of the data is;

s3: according to the category and the heat degree of the request data, a new data distribution optimization method is provided, two hot write data with the highest heat degree and one hot read data are combined and respectively stored in a CSB (common sense bus), an LSB (least significant bit) page and an MSB (most significant bit) page of a word line, so that the average write request performance is improved;

s4: and designing a reprogramming method based on the number of the limited layers according to the number of the limited layers for reprogramming the 3D flash memory, and improving the reading performance of the thermal read data of the corresponding MSB page after the CSB and the LSB page are updated.

Further, the step S1 includes: setting a controller of the SSD to store data through a request buffer area, and distinguishing cold and hot data through a hot filter; when the request queue enters the heat filter, firstly judging whether data is written for the first time, if so, recording the writing time of the data, and storing the data into a traditional programming area for traditional programming operation; if not, the data is subjected to cold and hot differentiation through a hot filter, and the differentiated hot data is saved in a request buffer area.

Further, step S1 is specifically to divide the data into read data and write data according to the access operation of the request data, calculate a time interval between two accesses of the request data, divide the data into hot read data or hot write data if the time interval is less than one second, and divide the data into cold read data or cold write data otherwise.

Further, in step S2, a plurality of special linked lists are maintained in the request buffer of the controller to store the hot data with the same update time, all the data stored in the same linked list have the same hot degree, the data will be updated at the same time point, and there is always a timeline in the linked lists, and the timeline will automatically advance every other time period, and the data stored in the linked list will be migrated to the linked list corresponding to the current update time; setting a specified fixed time period as m, storing the hot data in the request buffer area into a linked list corresponding to the updating time of the hot data, judging whether the time m passes through the data linked list, and if so, migrating the data in the original data linked list into the linked list corresponding to the updating time m of the data.

Further, the step S2 specifically includes: the heat of the data represents the expected time for the data to be accessed next time, and the higher the level of the linked list is, the higher the heat is, the data is accessed more quickly; the step of establishing the hot link list comprises the following steps:

s21: adding new request data into a corresponding linked list by taking the time interval of the last two accesses as the heat;

s22: and updating the heat of the data in the linked list at intervals of m, subtracting the time m from the heat of the data, and adding a new linked list again.

Further, the step S3 specifically includes: the method comprises the steps of taking simultaneously updated hot data at the front end parts of two chain tables, sending a cold data request to a hot filter by a buffer space, writing the requested frequently read cold data and the hot write data in the chain tables into a TLC flash memory unit, writing the two simultaneously updated hot data into first two bits LSBs and CSBs of the flash memory unit, writing the frequently read cold data into last MSBs of the flash memory unit, when the data are updated, invalidating the first two bits LSBs and CSBs of the flash memory unit, only leaving the most significant bit MSB, then applying a reprogramming method, merging original eight voltage states of the TLC, merging overlapped parts into the last two valid voltage states, and when the most significant bit MSB stores the frequently read data, the reprogramming performance can be effectively improved.

Further, in step S3, when there is a new data request, the allocation is performed according to a new data allocation optimization method, which includes the following steps:

s31: judging whether the request data is thermal read data, if so, reading the data and marking the data, otherwise, executing a step S32;

s32: judging whether the request data is cold read data, reading the data, and otherwise, executing the step S33;

s33: judging whether the request data is hot-written data, if so, executing step S34, otherwise, executing step S35;

s34: judging whether a buffer area in the FLASH controller has a free space, if so, storing the request data into the buffer area, otherwise, directly writing the request data into a FLASH memory;

s35: and judging whether the hot-write request data in the request buffer area is larger than 2, if so, selecting the two hot-write request data of the request buffer area and the currently requested cold write data to be written into the flash memory together, placing the two hot-write request data on the LSB and the CSB on the same word line, placing the cold write request on the MSB, and otherwise, directly writing the request data into the flash memory.

Further, in step S4, when the data enters the request buffer area, it is determined whether the buffer space is full, if the buffer space is full, it is determined whether there is removable data at the front end of the linked list, if there is removable data, it is determined whether the buffer space is full again, and if there is no removable data, the data and other data in the cache are written back to the flash memory together, so that the present invention cannot ensure that there are two data updated simultaneously during each write back; if the buffer space is not full, the operations of step S2 and step S3 are performed.

Further, in the step S4, the reprogramming method based on the number of layers is limited to include the steps of:

s41: checking invalid LSB pages and CSB pages within the maximum limit layer number each time when a new layer of the 3D flash memory is formed;

s42: when LSB and CSB on the same word fail at the same time, reprogramming is carried out, which can reduce the number of times of reading data detection voltage on MSB and reduce the time delay of reading data on MSB;

s43: and reprogramming invalid LSBs and the wordlines of the CSBs, and simultaneously writing newly written data into the flash memory blocks to share the reprogramming expense.

The invention has the beneficial effects that: the invention improves the performance of the hot and cold data layout to the reprogramming operation, reduces the data reading and writing time expenditure and the erasing frequency for determining the unit durability, improves the programming speed, increases the memory space and optimizes the service life and the performance of the flash memory.

Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the means of the instrumentalities and combinations particularly pointed out hereinafter.

Drawings

For the purposes of promoting a better understanding of the objects, aspects and advantages of the invention, reference will now be made to the following detailed description taken in conjunction with the accompanying drawings in which:

FIG. 1 illustrates a data allocation for an I/O request;

FIG. 2 illustrates a data allocation method during data migration;

FIG. 3 illustrates four cases of data allocation;

FIG. 4 is a voltage state transition diagram for an inactive perceptual coding technique.

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present invention in a schematic way, and the features in the following embodiments and examples may be combined with each other without conflict.

Wherein the showings are for the purpose of illustrating the invention only and not for the purpose of limiting the same, and in which there is shown by way of illustration only and not in the drawings in which there is no intention to limit the invention thereto; to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product; it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.

The same or similar reference numerals in the drawings of the embodiments of the present invention correspond to the same or similar components; in the description of the present invention, it should be understood that if there is an orientation or positional relationship indicated by terms such as "upper", "lower", "left", "right", "front", "rear", etc., based on the orientation or positional relationship shown in the drawings, it is only for convenience of description and simplification of description, but it is not an indication or suggestion that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and therefore, the terms describing the positional relationship in the drawings are only used for illustrative purposes, and are not to be construed as limiting the present invention, and the specific meaning of the terms may be understood by those skilled in the art according to specific situations.

Referring to fig. 1 to 4, the present invention uses the hot and cold data to distinguish and arrange the data in the ideal position of the flash memory unit, and invokes the new reprogramming method of the present invention to improve the performance of the flash memory. In the process, data enters the buffer space through the heat filter, and if the flash memory space is full and the data chain table does not have the data which can be removed, the data and other data in the buffer memory are written back to the flash memory page together.

FIG. 1 is a flow chart of data allocation of I/O requests, starting from step 101, where the read case is denoted as r, the write case is denoted as w, the cold case is denoted as c, and the hot case is denoted as h, and then:

step 102: setting a request buffer area in a controller of the SSD to store data, making a difference value according to the request time of the page twice, setting the request as a hot request when the difference value is smaller than a certain threshold value, setting the request as a cold request when the difference value is larger than the threshold value, and executing a step 103 if the request is judged to be a hot read request; if the request is a cold read request, go to step 104; if the request is a hot write request, go to step 105; other execution step 108

Step 103: if the request is a hot request as determined in step 102 and the request is to read data at a location on a flash memory page, the location data is read normally and the data page is marked

Step 104: if the read data in the read request is determined to be cold read data in step 102, the data at the location is read normally

Step 105: if the request condition is judged to be the hot writing in step 102, judging whether a buffer in the FLASH controller has free space, if so, executing step 106, otherwise, executing step 107

Step 106: in step 105, if it is determined that there is free space in the buffer, the data requested to be written is directly written to the buffer in the FLASH controller

Step 107: if there is no free space in the buffer, as determined in step 105, the data is then written directly to the FLASH FLASH page

Step 108: judging whether the request condition is other in the step 102, then judging whether the hot-written pages in the buffer are more than 2, if so, executing the step 109; otherwise, step 110 is performed.

Step 109: it is determined in step 108 that the hot-write pages are greater than 2 in the buffer, at which point two hot-write pages are selected and data allocation scheme 1 is performed to write hot-write data to the LSB and CSB and to write cold-write data to the MSB

Step 110: in step 108, it is determined that the hot-write page in the buffer is less than or equal to 2, and the request page is written into the FLASH memory page

Step 111, the data distribution mode of the I/O request is finished

The flowchart of fig. 2 is a flowchart of a data allocation method at the time of data migration, starting from step 101, and then:

record read as r, write as w, cold as c, and hot as h (e.g., record hot page as hw)

Step 102: if the page counter has hw ≥ 2& hr ≥ 1 at this time, enter a

loop including steps

102, 103, 104

Step 103: selecting two hot-write pages and one hot-read page in the request Buffer to execute a number 2 data allocation strategy, wherein the LSB and the CSB are allocated with hot-write data, and the MSB is allocated with hot-read data

Step 104: because some of the requests in the buffer are completed in 103, the page condition needs to be updated in the page counter, i.e., hw-2, hr-1

Step 105: judging whether hr is greater than 0, if yes, executing step 107, or step 109 or step 111

Step 106: if the condition that hr is not satisfied is judged in step 105, that is, hr is less than 0, the rest pages are written into the FLASH FLASH memory page

Step 107: if the condition is satisfied, i.e., hr >0, in step 105, it is determined whether 1<2 × hr ≦ cr is satisfied, if so, step 108 is performed, and if not, step 109 or step 111 is performed

Step 108: if 1<2 × hr ≦ cr is satisfied in step 107, then the data allocation scheme 3 is executed, i.e., two hot-write data are written to the LSB and CSB, respectively, and the hot-read data are written to the MSB, otherwise step 111 is executed

Step 109: if the condition of hr is satisfied in step 105, i.e. hr >0, it is determined whether cr <2 × hr <4cr is satisfied

Step 110: in step 108, if cr <2 × hr <4cr is satisfied in step 107, the data allocation scheme 3 is executed (2hr-cr/3) times, i.e., two hot write data are written to the LSB and CSB, respectively, and hot read data is written to the MSB; and (4cr-hr)/3 times data allocation scheme 4 writes two hot read data to the LSB and CSB and one cold read data to the MSB.

Step 111: if the hr satisfying condition is hr >0 in step 105, it is determined whether hr ≧ 2cr is satisfied

Step 112: in step 111, if hr ≧ 2cr is satisfied in step 107 to execute the data allocation scheme No. 3, two hot-write data are written to the LSB and CSB, respectively, and hot-read data are written to the MSB

Step 113: data allocation mode ending in data migration

Fig. 3 illustrates four cases of data allocation, allocation case 1: firstly, two thermal-writing data pages are respectively programmed into an LSB page and a CSB page with lower writing time delay in one sub-line, so that the writing performance is improved. Case 2 is allocated, i.e., two hot-write requests are written on the LSB and CSB to improve write performance and read performance. And if the number of the hot writes in the buffer is less than 2, storing the hot read data page into a buffer area of the flash controller. If the size of the buffer is not enough to store all the hot read pages, we select the allocation case 3 and the allocation case 4 to improve the read performance according to the proportion of the hot read data in the rest read data pages. The scheme of case 3 is assigned with the hot read data on the LSB and the cold read data on the CSB and MSB. Allocation case 4 is to place the data read hot on the LSB and CSB and the data read cold on the MSB.

FIG. 4 is a voltage state transition diagram of an invalid sensing encoding technique for merging repetitive voltages when data on the LSB or CSB is invalid to reduce the number of times the identification voltage is read in the CSB or MSB. As shown in FIG. 4, if the LSB and CSB bits are invalid, the voltage states P1, P2, and P5 may move to P5, while P0, P3, and P4 may move to P7. Similarly, if the LSB bit is invalid, P1, P2, P3, or P4 may move to P8, P7, P6, or P5, respectively. Since programming errors are greatly increased when the number of reprogramming layers is greater than 2 in a 3D TLC SSD, we set the maximum number of reprogramming layers to 2 to ensure correctness.

Finally, the above embodiments are only intended to illustrate the technical solutions of the present invention and not to limit the present invention, and although the present invention has been described in detail with reference to the preferred embodiments, it will be understood by those skilled in the art that modifications or equivalent substitutions may be made on the technical solutions of the present invention without departing from the spirit and scope of the technical solutions, and all of them should be covered by the claims of the present invention.

Claims

1. A data distribution and reprogramming optimization method for a 3D TLC flash memory is characterized by comprising the following steps: the method comprises the following steps:

2. The 3D TLC flash memory-oriented data distribution and reprogramming optimization method of claim 1, wherein: the step S1 includes: setting a controller of the SSD to store data through a request buffer area, and distinguishing cold and hot data through a hot filter; when the request queue enters the heat filter, firstly judging whether data is written for the first time, if so, recording the writing time of the data, and storing the data into a traditional programming area for traditional programming operation; if not, the data is subjected to cold and hot differentiation through a hot filter, and the differentiated hot data is saved in a request buffer area.

3. The 3D TLC flash memory oriented data distribution and reprogramming optimization method of claim 2, wherein: the step S1 is specifically to divide the data into read data and write data according to the access operation of the request data, calculate the two access time interval of the request data, if the time interval is less than one second, divide the data into hot read data or hot write data, otherwise, divide the data into cold read data or cold write data.

4. The 3D TLC flash memory-oriented data distribution and reprogramming optimization method of claim 1, wherein: in step S2, a plurality of special linked lists are maintained in the request buffer of the controller to store hot data with the same update time, all the data stored in the same linked list have the same hot degree, and will be updated at the same time point, and there is always a timeline in the linked lists, and every other time period, the timeline will be automatically advanced, and the data stored in the linked list will be migrated to the linked list corresponding to the current update time; setting a specified fixed time period as m, storing the hot data in the request buffer area into a linked list corresponding to the updating time of the hot data, judging whether the time m passes through the data linked list, and if so, migrating the data in the original data linked list into the linked list corresponding to the updating time m of the data.

5. The 3D TLC flash memory-oriented data distribution and reprogramming optimization method of claim 4, wherein: the step S2 specifically includes: the heat of the data represents the expected time for the data to be accessed next time, and the higher the level of the linked list is, the higher the heat is, the data is accessed more quickly; the step of establishing the hot link list comprises the following steps:

6. The 3D TLC flash memory-oriented data distribution and reprogramming optimization method of claim 1, wherein: the step S3 specifically includes: taking simultaneously updated hot data at the front end parts of two chain tables, sending a cold data request to a hot filter by a buffer space, writing frequently read cold data requested to the hot filter into a TLC flash memory unit together with hot write data in the chain tables, writing the two simultaneously updated hot data into first two bits LSBs and CSBs of the flash memory unit, writing the frequently read cold data into a last bit MSB of the flash memory unit, when the data are updated, invalidating the first two bits LSBs and CSBs of the flash memory unit, only leaving the most significant bit MSB, then applying a reprogramming method, merging original eight voltage states of the TLC, and merging overlapped parts into the final voltage state which only leaves two valid voltage states.

7. The 3D TLC flash memory-oriented data distribution and reprogramming optimization method of claim 6, wherein: in step S3, when there is a new data request, the allocation is performed according to a new data allocation optimization method, which includes the following steps:

8. The 3D TLC flash memory-oriented data distribution and reprogramming optimization method of claim 1, wherein: in step S4, when the data enters the request buffer, it is determined whether the buffer space is full, if the buffer space is full, it is determined whether there is data that can be removed at the front end of the linked list, if there is data that can be removed, it is determined whether the buffer space is full again, and if there is no data that can be removed, the data is written back to the flash memory together with other data in the cache; if the buffer space is not full, the operations of step S2 and step S3 are performed.

9. The 3D TLC flash memory oriented data distribution and reprogramming optimization method of claim 8, wherein: in step S4, the reprogramming method based on the number of layers is limited to include the steps of:

s42: reprogramming is carried out when LSB and CSB on the same word fail at the same time;