CN114280868A

CN114280868A - Display substrate, display panel and display device

Info

Publication number: CN114280868A
Application number: CN202210002773.8A
Authority: CN
Inventors: 李伟; 张小凤; 张昭; 秦文文; 陈延青; 李泽亮; 陈凯; 秦伟达; 李必奇
Original assignee: BOE Technology Group Co Ltd
Current assignee: BOE Technology Group Co Ltd
Priority date: 2022-01-04
Filing date: 2022-01-04
Publication date: 2022-04-05

Abstract

The embodiment of the disclosure provides a display substrate, a display panel and a display device. The display substrate comprises a first substrate, a thin film transistor structure layer, a first insulating layer, a color resistance layer and a pixel electrode layer, wherein the thin film transistor structure layer is sequentially arranged on one side of the first substrate, the first insulating layer is arranged on the color resistance layer, the light shielding layer is arranged on one side of the first substrate, which faces the thin film transistor structure layer, and comprises a plurality of columns of color resistance blocks arranged along a first direction, the colors of the color resistance blocks arranged on the same column are the same, the colors of two adjacent columns of color resistance blocks are different, the light shielding layer comprises a plurality of first light shielding strips, and the orthographic projections of the first light shielding strips on the first substrate are positioned between the orthographic projections of the two adjacent color resistance blocks on the first substrate. The technical scheme of the disclosure can be applied to the flexible display device, can avoid the color mixing caused by bending, can avoid the aperture opening ratio loss caused by bending, and improves the display effect and the aperture opening ratio of the display device.

Description

Display substrate, display panel and display device

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a display substrate, a display panel, and a display device.

Background

With the development of technology, curved surface displays are increasingly popular in the market, and are widely used in the fields of TVs, vehicle displays, and the like. However, after the liquid crystal display product is bent, the upper and lower substrates of the liquid crystal display product are relatively displaced, resulting in optical and image quality failures.

Disclosure of Invention

Embodiments of the present disclosure provide a display substrate, a display panel and a display device to solve or alleviate one or more technical problems in the prior art.

As a first aspect of embodiments of the present disclosure, embodiments of the present disclosure provide a display substrate including:

a first substrate;

the thin film transistor structure layer is positioned on one side of the first substrate and comprises a plurality of thin film transistors, each thin film transistor comprises a gate electrode, an active layer, a first pole and a second pole, and the first pole and the second pole are both connected with the active layer;

the first insulating layer is positioned on one side, away from the first substrate, of the thin film transistor structure layer, and is provided with a plurality of first through holes, and the orthographic projection of the first through holes on the first substrate is positioned in the orthographic projection range of the second pole on the first substrate;

the color resistance layer is positioned on one side, away from the first substrate, of the first insulating layer and comprises a plurality of rows of color resistance blocks arranged along the first direction, the color of the color resistance blocks positioned in the same row is the same, and the color of the color resistance blocks positioned in the two adjacent rows is different;

the shading layer is positioned on one side, facing the thin film transistor structure layer, of the first substrate and comprises a plurality of first shading strips, and the orthographic projections of the first shading strips on the first substrate are positioned between the orthographic projections of two adjacent color resistance blocks on the first substrate;

and the pixel electrode layer is positioned on one side of the color resistance layer, which is deviated from the first substrate, and comprises a plurality of pixel electrodes, each pixel electrode is connected with the second pole of the corresponding thin film transistor through the corresponding through hole, and the through hole comprises the corresponding first through hole.

In some possible implementation manners, a partition groove is arranged between two adjacent color resist blocks in the same column, and an orthogonal projection of the via hole on the first substrate is located within an orthogonal projection range of the partition groove on the first substrate.

In some possible implementations, a distance between an orthographic boundary of the via on the first substrate and an orthographic boundary of the partition trench on the first substrate ranges from 4 μm to 6 μm.

In some of the possible implementations of the present invention,

the shading layer is positioned between the first insulating layer and the color resistance layer, the shading layer is provided with a plurality of second through holes, orthographic projections of the second through holes on the first substrate are at least partially overlapped with orthographic projections of the first through holes on the first substrate, and the through holes further comprise corresponding second through holes; alternatively, the first and second electrodes may be,

the shading layer is positioned between the first substrate and the thin film transistor structure layer; alternatively, the first and second electrodes may be,

the shading layer is positioned on one side of the pixel electrode layer, which is far away from the first substrate.

In some possible implementation manners, each first light-shielding bar extends along the first direction, the thin film transistor structure layer further includes a plurality of first metal routing lines, each first metal routing line extends along the first direction, and an orthographic projection of the first metal routing line on the first substrate is located within an orthographic projection range of the corresponding first light-shielding bar on the first substrate.

In some possible implementations, an orthographic projection of the blocking groove on the first substrate is within a range of an orthographic projection of the corresponding first light-shielding bar on the first substrate.

In some possible implementation manners, the light-shielding layer further includes a plurality of second light-shielding bars, the second light-shielding bars are located between two adjacent columns of color-resisting blocks, the thin film transistor structure layer further includes a plurality of second metal wires, and an orthographic projection of each second metal wire on the first substrate is located within an orthographic projection range of the corresponding second light-shielding bar on the first substrate.

In some possible implementations, a distance between an orthographic projection boundary of the first light-shielding bar on the first substrate and an orthographic projection boundary of the corresponding first metal trace on the first substrate ranges from 0.8 μm to 1.2 μm, and a distance between an orthographic projection boundary of the second light-shielding bar on the first substrate and an orthographic projection boundary of the corresponding second metal trace on the first substrate ranges from 0.8 μm to 1.2 μm.

In some possible implementation manners, each first light-shielding strip extends along the second direction, the first light-shielding strips are located between two adjacent columns of color-resisting blocks, the thin film transistor structure layer further includes a plurality of second metal routing lines, each second metal routing line extends along the second direction, an orthographic projection of each second metal routing line on the first substrate is located in an orthographic projection range of the corresponding first light-shielding strip on the first substrate, and the second direction is a direction perpendicular to the first direction.

In some possible implementations, the display substrate further includes a plurality of main supporting pillars, the main supporting pillars are located on a side of the pixel electrode layer away from the first substrate, an orthographic projection of a bottom surface of each main supporting pillar, facing the side of the first substrate, on the first substrate is located within an orthographic projection range of the partition groove on the first substrate, and the orthographic projection of the bottom surface of each main supporting pillar on the first substrate does not intersect with an orthographic projection of the via hole on the first substrate.

In some possible implementation manners, the display substrate further includes a plurality of secondary support pillars, the secondary support pillars are located on a side of the pixel electrode layer away from the first substrate, an orthographic projection of a bottom surface of each secondary support pillar, facing the first substrate, on the first substrate is located within an orthographic projection range of the partition trench on the first substrate, and the orthographic projection of the bottom surface of each secondary support pillar on the first substrate does not intersect with an orthographic projection of the via hole on the first substrate.

In some possible implementations, the central dimension of the bottom surface of the primary support posts is greater than or equal to 14.5 μm and the central dimension of the bottom surface of the secondary support posts is greater than or equal to 14.5 μm.

As a second aspect of the embodiments of the present disclosure, embodiments of the present disclosure provide a display panel including a first substrate and a second substrate that are oppositely disposed, and a liquid crystal disposed between the first substrate and the second substrate, wherein the first substrate is the display substrate in any embodiment of the present disclosure.

As a third aspect of the embodiments of the present disclosure, an embodiment of the present disclosure provides a display panel, including a first substrate and a second substrate that are oppositely disposed, and a liquid crystal disposed between the first substrate and the second substrate, where the first substrate is a display substrate as in the above embodiment, the second substrate includes a second base and a plurality of second light-shielding bars located on a side of the second base facing the display substrate, each second light-shielding bar extends along a first direction, and an orthographic projection of a second pole of a thin film transistor in the display substrate on the first base is located within an orthographic projection range of the corresponding second light-shielding bar on the first base.

In some possible implementations, the display panel is a display panel that is bendable in a first direction.

As a fourth aspect of the embodiments of the present disclosure, embodiments of the present disclosure provide a display device including the display panel in any one of the embodiments of the present disclosure.

According to the technical scheme of the embodiment of the disclosure, the thin film transistor structure layer, the color resistance layer, the light shielding layer and the pixel electrode layer are arranged on the same substrate, even if the display substrate and the other substrate have the problem of inconsistent box, the color resistance block and the pixel region are not staggered, the color mixing and color crosstalk caused by inconsistent box can be avoided, and the display effect is improved.

The display panel in the embodiment of the disclosure can avoid the deviation of the light shielding layer caused by the bending of the display panel, thereby avoiding the loss of the aperture opening ratio and improving the aperture opening ratio of the display panel.

The display substrate of the embodiment can be applied to a bendable liquid crystal display panel, and the liquid crystal display panel adopting the display substrate of the embodiment can avoid color mixing caused by bending, avoid aperture opening ratio loss caused by bending and improve the display effect and aperture opening ratio of the display panel.

The foregoing summary is provided for the purpose of description only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features of the present disclosure will be readily apparent by reference to the drawings and following detailed description.

Drawings

In the drawings, like reference numerals refer to the same or similar parts or elements throughout the several views unless otherwise specified. The figures are not necessarily to scale. It is appreciated that these drawings depict only some embodiments in accordance with the disclosure and are not to be considered limiting of its scope.

FIG. 1a is a schematic view of a liquid crystal display panel;

FIG. 1b is a schematic diagram of the LCD panel shown in FIG. 1a in a bent state;

FIG. 2a is a schematic structural diagram of a display panel in the related art;

FIG. 2b is a schematic diagram illustrating a bending state of the display panel shown in FIG. 2 a;

FIG. 3 is a schematic top view of a display substrate according to an embodiment of the present disclosure;

FIG. 4 is a schematic view of the cross-sectional structure A-A of FIG. 3;

FIG. 5 is a schematic top view of a display substrate according to another embodiment of the present disclosure;

FIG. 6 is a schematic cross-sectional view B-B of FIG. 5;

FIG. 7 is a schematic cross-sectional view of a display substrate according to another embodiment of the present disclosure;

FIG. 8 is a schematic cross-sectional view of a display substrate according to another embodiment of the present disclosure;

FIG. 9 is a schematic view of a structure showing an arrangement of support pillars in a substrate according to an embodiment of the present disclosure;

FIG. 10 is a schematic structural diagram of a display panel according to an embodiment of the present disclosure;

fig. 11 is a schematic structural diagram of a display panel according to another embodiment of the disclosure.

Description of reference numerals:

10. a first substrate; 11. a first substrate; 13. a first insulating layer; 14. a color resist layer; 141. a color block; 142. isolating the groove; 15. a light-shielding layer; 151. a first shading strip; 152. a second shading strip; 16. a pixel electrode layer; 161. a pixel electrode; 17. a planarization layer; 18. a second insulating layer; 19. a common electrode layer; 20. A second substrate; 21. a second substrate; 22. a color film layer; 221. a color film; 23. a black matrix; 24. an outer cover; 30. a thin film transistor structure layer; 311. a first electrode of the thin film transistor; 312. a second electrode of the thin film transistor; 313. an active layer; 314. a gate electrode; 32. a buffer layer; 33. an interlayer insulating layer; 34. a gate insulating layer; 41. a first alignment layer; 42. a second alignment layer; 43. a shielding layer; 51. a first metal routing; 52. a second metal routing; 61. a main support column; 62. a secondary support post; 621. a first secondary support column; 622. A second secondary support column; 70. a via hole; 71. a first via hole; 72. a second via hole; 73. a third via hole; 74. And a fourth via.

Detailed Description

In the following, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments may be modified in various different ways, and different embodiments may be combined arbitrarily without departing from the spirit or scope of the disclosure. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.

Fig. 1a is a schematic structural diagram of a liquid crystal display panel, and fig. 1b is a schematic diagram of a bent state of the liquid crystal display panel shown in fig. 1 a. As shown in fig. 1a and 1b, the liquid crystal display panel includes a first substrate 10 and a second substrate 20 disposed opposite to each other, and liquid crystal (not shown) between the first substrate 10 and the second substrate 20. The first substrate 10 includes a first base 11, and a pixel electrode 161 disposed on the first base 11. The second substrate 20 includes a second substrate 21, and a color film layer 22 and a black matrix 23 disposed on the second substrate 21, where the color film layer 22 includes a plurality of color films 221, as shown in fig. 1a, colors of adjacent color films 221 are different. In a normal state (i.e., a flat state) of the lcd panel, as shown in fig. 1a, the color films 221 correspond to the pixel electrodes 161 one by one. When the lcd panel is bent, the first substrate 11 and the second substrate 21 may be displaced relatively, as shown in fig. 1b, so that the color films 221 and the pixel electrodes 161 are dislocated, and when the same pixel electrode 161 is turned on, the adjacent two color films 221 with different colors both transmit light, and color mixing occurs. For example, after the first pixel electrode 161a in fig. 1b is turned on, two adjacent color films 221a (green color resist blocks) and 221b (blue color resist blocks) transmit light, and color mixing occurs.

Fig. 2a is a schematic structural diagram of a display panel in the related art, and fig. 2b is a schematic diagram of the display panel shown in fig. 2a in a bent state. As shown in fig. 2b, the first substrate includes a first metal trace 51 and a second metal trace 52 that are disposed to intersect with each other, the first metal trace 51 and the second metal trace 52 intersect with each other to define a pixel region, and in fig. 2b, a width of the pixel region is a distance between two adjacent second metal traces 52. In contrast to the display panel shown in fig. 1a, in the display panel shown in fig. 2a and 2b, the color film layer 22 is disposed on the first substrate 10. Compared with the display panel shown in fig. 1a, the display panel shown in fig. 2a can effectively avoid the color cross problem of the display panel in a bent state. However, since the black matrix 23 is located on the second substrate 20, after the display panel is bent, the second base 21 of the second substrate 20 and the first base 11 of the first substrate 10 are relatively displaced, so that the black matrix 23 on the second substrate 20 is shifted to the pixel region in the horizontal direction, as shown in fig. 2b, resulting in a loss of aperture ratio of the display panel, and affecting the optical evaluation index such as transmittance of the display panel.

Fig. 3 is a schematic top view of a display substrate according to an embodiment of the disclosure, and fig. 4 is a schematic cross-sectional view of a-a in fig. 3. As shown in fig. 3 and 4, the display substrate includes a first base 11, a thin film transistor structure layer 30, a first insulating layer 13, a color resistance layer 14, a light shielding layer 15, and a pixel electrode layer 16.

The thin film transistor structure layer 30 is located on one side of the first substrate 11, the thin film transistor structure layer 30 includes a plurality of thin film transistors, the thin film transistors may include a gate electrode, an active layer, a first electrode 311 and a second electrode 312, and the first electrode 311 and the second electrode 312 are both connected to the active layer. One of the first and

second poles

311 and 312 may be a source electrode and the other may be a drain electrode.

The first insulating layer 13 may be located on a side of the thin film transistor structure layer 30 away from the first substrate 11, the first insulating layer 13 defines a plurality of first via holes 71, and an orthographic projection of the first via holes 71 on the first substrate 11 is located within an orthographic projection range of the second pole 312 on the first substrate 11. With such a structure, the second pole 312 can shield the first via hole 71, thereby preventing light leakage at the position of the first via hole 71.

The color resist layer 14 is located on a side of the first insulating layer 13 facing away from the first substrate 11, the color resist layer 14 may include a plurality of rows of color resist blocks 141 arranged along the first direction X, colors of the color resist blocks 141 located in a same row may be the same, and colors of the color resist blocks 141 in two adjacent rows may be different. For example, in the first direction X, the color blocks located in the same row may include a first color block 141a, a second color block 141b, and a third color block 141c, the first color block 141a may be red, the second color block 141b may be green, and the third color block 141c may be blue. It is understood that the color resist layer may also be called a color film layer, and the color resist block may also be called a color film.

For example, the color-resisting blocks in the same column may be one color-resisting strip, the color-resisting strip is divided into a plurality of color-resisting blocks in the same column, or the color-resisting blocks in the same column are a plurality of color-resisting blocks disconnected from each other.

The light-shielding layer 15 is located on a side of the first substrate 11 facing the thin film transistor structure layer 30, and the light-shielding layer 15 may include a plurality of first light-shielding bars 151, where orthographic projections of the first light-shielding bars 151 on the first substrate 11 are located between orthographic projections of two adjacent color resist blocks 141 on the first substrate 11. Therefore, the first light-shielding strip 151 can prevent color mixing between two adjacent color-resisting blocks 141, and improve the display effect. The light-shielding layer 15 may be referred to as a black matrix layer.

Here, the extending direction of the first light-shielding bars 151 is not limited, and exemplarily, the first light-shielding bars 151 may extend in a first direction X, or the first light-shielding bars 151 may extend in a second direction Y, which is a direction perpendicular to the first direction X.

The orthographic projection of the first light-shielding bars 151 on the first substrate 11 is located between the orthographic projections of two adjacent color-resisting blocks 141 on the first substrate 11, for example, the orthographic projection of the first light-shielding bars 151 on the first substrate 11 may be located between the orthographic projections of two adjacent columns of color-resisting blocks 141 on the first substrate 11, or the orthographic projection of the first light-shielding bars 151 on the first substrate 11 may be located between the orthographic projections of two adjacent rows of color-resisting blocks 141 on the first substrate 11. Here, the orthographic projection of the first light-shielding bar 151 on the first substrate 11 is located between the orthographic projections of the adjacent two color-resist blocks 141 on the first substrate 11, and it can be understood that there is an overlapping area between the orthographic projection of the first light-shielding bar 151 on the first substrate 11 and the orthographic projections of the adjacent two color-resist blocks 141 on the first substrate 11, as shown in fig. 3.

The pixel electrode layer 16 is located on a side of the color resist layer 14 away from the first substrate 11, the pixel electrode layer 16 includes a plurality of pixel electrodes 161, each pixel electrode 161 is connected to the second electrode 312 of the corresponding thin film transistor through a corresponding via hole 70, as shown in fig. 4, the via hole 70 includes a corresponding first via hole 71.

The conventional liquid crystal display panel comprises an array substrate and a color film substrate which are arranged in a box-to-box mode, a thin film transistor structure layer and a pixel electrode are both arranged on the array substrate, and a pixel area can be defined by mutually crossed grid lines and data lines in the thin film transistor structure layer. And the color film layer and the black matrix are arranged on the color film substrate. When the array substrate and the color film substrate are subjected to box alignment, the color films and the pixel regions are ensured to be in one-to-one correspondence, if the color film substrate and the array substrate are not in box alignment, the color films and the pixel regions are staggered, color mixing occurs, and the display effect is affected, so that the problem of box alignment inconsistency is avoided in the box alignment process.

According to the display substrate provided by the embodiment of the disclosure, the thin film transistor structure layer 30, the color resistance layer 14, the light shielding layer 15 and the pixel electrode layer 16 are arranged on the same substrate, when the display substrate is applied to a liquid crystal display panel, even if the display substrate and another substrate have the problem of inconsistent box alignment, the color resistance block and the pixel region are not staggered, the color mixing and cross color caused by inconsistent box alignment can be avoided, and the display effect is improved.

When the display substrate of the embodiment of the disclosure is applied to a bendable liquid crystal display panel, compared with the display panel shown in fig. 2a and 2b, the display panel to which the display substrate of the embodiment of the disclosure is applied can avoid the deviation of the light shielding layer caused by the bending of the display panel, thereby avoiding the loss of the aperture ratio and improving the aperture ratio of the display panel.

In one embodiment, as shown in fig. 4, the thin film transistor structure layer 30 may include a Buffer layer (Buffer)32, an active layer 313, a gate insulating layer (GI)33, a gate electrode 314, an interlayer Insulating Layer (ILD) 34, a first electrode 311, and a second electrode 312. The thin film transistor in the thin film transistor structure layer 30 shown in fig. 4 is a top gate type thin film transistor, and it is understood that in other embodiments, the thin film transistor may be a bottom gate type thin film transistor. Here, the type of the thin film transistor is not specifically set as long as the performance of the thin film transistor can be achieved.

In one embodiment, as shown in fig. 3 and 4, a blocking groove 142 is disposed between two adjacent color resist blocks 141 in the same column, and an orthographic projection of the via hole 70 on the first substrate 11 is located within an orthographic projection range of the blocking groove 142 on the first substrate 11. With such a structure, the color resist block 141 can completely avoid the via hole 70, and the material in the process of forming the color resist layer is prevented from remaining in the first via hole 71, so that the pixel electrode 161 is ensured to be in good contact with the second electrode 312 of the thin film transistor through the via hole 70, and stable signal transmission is ensured. In addition, by arranging the partition groove 142, the color resistance blocks of the same color can be completely isolated, so that the mutual influence is avoided, and the display effect is improved. It can be understood that the pixel electrode 161 needs to be connected to the second electrode 312 of the thin film transistor through a via hole penetrating through each film layer, and the film thickness of the region of the blocking trench 142 can be reduced by providing the blocking trench 142, so that when the via hole 70 is formed in the region of the blocking trench 142, the thickness of the film layer to be etched can be reduced, and the difficulty in forming the via hole can be reduced.

In one embodiment, as shown in fig. 3, a distance between an orthographic projection boundary of the via 70 on the first substrate 11 and an orthographic projection boundary of the partition trench 142 on the first substrate 11 ranges from 4 μm to 6 μm (inclusive). Accordingly, the distance between the color-resist block 141 and the first via hole 71 is far enough to completely prevent the material from remaining in the first via hole 71 during the color-resist layer formation process. Illustratively, the distance between the orthographic projection boundary of the via 70 on the first substrate 11 and the orthographic projection boundary of the blocking trench 142 on the first substrate 11 may be any value from 4 μm to 6 μm, and for example, may be any value from 4 μm, 4.5 μm, 5 μm, 5.5 μm, and 6 μm.

In one embodiment, as shown in fig. 4, the light shielding layer 15 may be located between the first insulating layer 13 and the color resist layer 14.

In one embodiment, as shown in fig. 4, the display substrate may further include a planarization layer 17, and the planarization layer 17 is located between the color resist layer 14 and the pixel electrode layer 16. Illustratively, the light-shielding layer 15 may be located between the color resist layer 14 and the planarization layer 17.

In this manner, the light-shielding layer 15 and the color resist layer 14 are adjacent layers, and the light-shielding layer 15 and the color resist layer 14 are located at a short distance from each other, so that the light-shielding effect of the light-shielding layer 15 can be further improved, and the color mixture phenomenon between adjacent color resist blocks can be further prevented.

As shown in fig. 4, the light shielding layer 15 has a plurality of second vias 72, and an orthographic projection of the second vias 72 on the first substrate 11 at least partially overlaps an orthographic projection of the first vias 71 on the first substrate 11, so that the second vias 72 communicate with the first vias 71, and the vias 70 include the second vias 72 and the first vias 71 that communicate with each other. With such a structure, the second via hole 72 and the first via hole 71 can form a trepan boring, and when the pixel electrode 161 is formed, the pixel electrode 161 can be directly connected with the second pole 312 of the thin film transistor vertically and downwards, so that the length of a connecting wire between the pixel electrode 161 and the second pole 312 is shortened, and the signal transmission speed can be improved.

In one embodiment, as shown in fig. 4, the orthographic projection of the second via 72 on the first substrate 11 includes the orthographic projection of the first via 71 on the first substrate 11. An orthographic projection of the second via hole 72 on the first substrate 11 is located within an orthographic projection range of the blocking groove 142 on the first substrate 11.

In one embodiment, as shown in fig. 4, the planarization layer 17 is opened with a third via 73, and an orthographic projection of the third via 73 on the first substrate 11 at least partially coincides with an orthographic projection of the second via 72 on the first substrate 11. Thus, the third via 73, the second via 72, and the first via 71 may form a communicating trepan.

In one embodiment, as shown in fig. 4, the display substrate may further include a second insulating layer 18, the second insulating layer 18 is located between the planarization layer 17 and the pixel electrode layer 161, and the second insulating layer 18 defines a fourth via 74. An orthographic projection of the fourth via 74 on the first substrate 11 at least partially coincides with an orthographic projection of the third via 73 on the first substrate 11. Therefore, the fourth via hole 74, the third via hole 73, the second via hole 72 and the first via hole 71 can form a communicated trepan boring, and the pixel electrode 161 is connected with the second pole 312 of the thin film transistor through the fourth via hole 74, the third via hole 73, the second via hole 72 and the first via hole 71, so that the length of a connecting line between the pixel electrode 161 and the second pole 312 is further shortened, the signal transmission speed is improved, and the display effect is improved.

Illustratively, the orthographic projection of the fourth via 74 on the first substrate 11 may include the orthographic projection of the third via 73 on the first substrate 11, the orthographic projection of the third via 73 on the first substrate 11 may include the orthographic projection of the second via 72 on the first substrate 11, the orthographic projection of the second via 72 on the first substrate 11 may include the orthographic projection of the first via 71 on the first substrate 11, and the via 70 includes the fourth via 74, the third via 73, the second via 72, and the first via 71 which are sequentially nested.

In one embodiment, as shown in fig. 4, the display substrate may further include a common electrode layer 19, and the common electrode layer 19 may be located between the second insulating layer 18 and the planarization layer 17. The common electrode layer 19 and the pixel electrode layer 16 may form a horizontal electric field, and when the display substrate is applied to a liquid crystal display panel, the horizontal electric field formed by the common electrode layer 19 and the pixel electrode layer 16 may be used to drive the liquid crystal to rotate.

In one embodiment, as shown in fig. 4, the display substrate may further include a first alignment layer 41, and the first alignment layer 41 may be located on a side of the pixel electrode layer 16 facing away from the first substrate 11. The material of the first alignment layer 41 may be Polyimide (PI).

In one embodiment, as shown in fig. 4, the display substrate may further include a shielding layer 43, and the shielding layer 43 may be located between the first base 11 and the thin film transistor structure layer 30. The shielding layer is used for shielding the active layer of the thin film transistor, and the influence of backlight on the active layer to the performance of the thin film transistor is avoided.

In one embodiment, as shown in fig. 3, the plurality of first light-shielding bars 151 are parallel to each other, and each of the first light-shielding bars 151 extends in the first direction X. The thin film transistor structure layer 30 may further include a plurality of first metal traces 51, each of the first metal traces 51 extends along the first direction, and an orthographic projection of the first metal trace 51 on the first substrate 11 is located within an orthographic projection range of the corresponding first light-shielding bar 151 on the first substrate 11. With such a structure, the first light-shielding bar 151 can shield the area where the first metal wire 51 is located, thereby preventing side light leakage from occurring at the position of the first metal wire 51.

Illustratively, the distance between the orthographic projection boundary of the first light-shielding bar 151 on the first substrate 11 and the orthographic projection boundary of the corresponding first metal routing 51 on the first substrate 11 ranges from 0.8 μm to 1.2 μm (inclusive). In this way, the first light-shielding bar 151 can completely shield the lateral light leakage of the first metal trace 51. The distance between the orthographic projection boundary of the first light-shielding bar 151 on the first substrate 11 and the orthographic projection boundary of the corresponding first metal routing 51 on the first substrate 11 may be any value from 0.8 μm to 1.2 μm, for example, one value from 0.8 μm, 1.0 μm, and 1.2 μm.

In one embodiment, as shown in fig. 3, an orthographic projection of the blocking groove 142 on the first substrate 11 is located within an orthographic projection range of the corresponding first light-shielding bar 151 on the first substrate 11. Therefore, the first light-shielding bars 151 can shield the region where the blocking grooves 141 are located, light leakage at the positions of the blocking grooves 141 is avoided, a display effect is provided, and the contrast of the display device is improved.

In one embodiment, as shown in fig. 3, an orthographic projection of the blocking groove 141 on the first substrate 11 at least partially coincides with an orthographic projection of the corresponding first metal trace 51 on the first substrate. It is understood that the material of the first metal trace 51 is usually metal, and the arrangement of the first metal trace 51 may reduce the aperture ratio of the display device. By arranging that the orthographic projection of the blocking groove 141 on the first substrate 11 is at least partially overlapped with the orthographic projection of the corresponding first metal wire 51 on the first substrate, the aperture ratio loss can be reduced, and the aperture ratio of the display device can be increased. Exemplarily, an orthographic projection of the blocking groove 141 on the first substrate 11 may be located within an orthographic projection range of the corresponding first metal trace 51 on the first substrate, as shown in fig. 3.

In one embodiment, the first metal trace 51 may be a gate line, and the first metal trace 51 may be located at the same layer as a gate electrode of the thin film transistor.

In one embodiment, as shown in fig. 3, the light-shielding layer 15 may further include a plurality of second light-shielding bars 152, the plurality of second light-shielding bars 152 are parallel to each other, and the second light-shielding bars 152 all extend along the second direction Y. The second light-shielding bar 152 is located between two adjacent columns of color-resist blocks 141. The thin film transistor structure layer may further include a plurality of second metal traces 52, and an orthographic projection of each second metal trace 52 on the first substrate 11 may be located within an orthographic projection range of the corresponding second light-shielding bar 152 on the first substrate 11. The second light-shielding strip 152 can shield light, so as to prevent color mixing between color-blocking blocks with different colors. The orthographic projection of each second metal wire 52 on the first substrate 11 is set to be located in the orthographic projection range of the corresponding second light-shielding bar 152 on the first substrate 11, so that the influence of the second metal wire 52 and the second light-shielding bar 152 on the aperture ratio can be reduced, the loss of the aperture ratio is reduced, and the aperture ratio of the display device is improved.

Illustratively, the distance between the orthographic projection boundary of the second light-shielding bar 152 on the first substrate 11 and the orthographic projection boundary of the corresponding second metal routing 52 on the first substrate 11 ranges from 0.8 μm to 1.2 μm (inclusive). In this way, the second light-shielding bar 152 can completely shield the lateral light leakage of the second metal trace 52. The distance between the orthographic projection boundary of the second light-shielding bar 152 on the first substrate 11 and the orthographic projection boundary of the corresponding second metal routing 52 on the first substrate 11 can be any value from 0.8 μm to 1.2 μm, for example, one value from 0.8 μm, 1.0 μm and 1.2 μm.

In one embodiment, the second metal trace 52 may be a data line, and the second metal trace 52 may be located at the same layer as a source electrode or a drain electrode of the thin film transistor.

It should be noted that, in the above, the first metal trace 51 may be a gate line, and the second metal trace 52 may be a data line. In other embodiments, the first metal trace 51 may be a data line, and the second metal trace 52 may be a gate line. It is understood that the first metal trace and the second metal trace may also be other metal lines for transmitting signals.

It should be noted that the second light-shielding bar 152 is located between two adjacent columns of color-resisting blocks 141, it is understood that an orthographic projection of the second light-shielding bar 152 on the first substrate 11 is located between two adjacent columns (for example, a first column and a second column) of color-resisting blocks on the first substrate 11, that is, an orthographic projection of the second light-shielding bar 152 on the first substrate 11 and an orthographic projection of the first column of color-resisting blocks on the first substrate 11 may not intersect, and an orthographic projection of the second light-shielding bar 152 on the first substrate 11 and an orthographic projection of the second column of color-resisting blocks on the first substrate 11 also do not intersect; alternatively, the orthographic projection of the second light shielding bar 152 on the first substrate 11 may intersect the orthographic projection of the first column of color-resist blocks on the first substrate, and does not intersect the orthographic projection of the second column of color-resist blocks on the first substrate; alternatively, the orthographic projection of the second light-shielding bar 152 on the first substrate 11 intersects the orthographic projection of the first column of color-resisting blocks on the first substrate 11, and the orthographic projection of the second light-shielding bar 152 on the first substrate 11 also intersects the orthographic projection of the second column of color-resisting blocks on the first substrate 11.

Fig. 5 is a schematic top view of a display substrate according to another embodiment of the disclosure, and fig. 6 is a schematic cross-sectional view B-B of fig. 5. In one embodiment, as shown in fig. 5 and 6, the plurality of first light-shielding bars 151 are parallel to each other, each of the first light-shielding bars 151 extends along the second direction Y, and the first light-shielding bars 151 are located between two adjacent columns of the color resist blocks 141. The thin film transistor structure layer further includes a plurality of second metal traces 52, each second metal trace 52 extends along a second direction Y, an orthographic projection of each second metal trace 52 on the first substrate 11 is located within an orthographic projection range of the corresponding first light-shielding bar 151 on the first substrate 11, and the second direction Y is a direction perpendicular to the first direction X.

The first light-shielding strip 151 is arranged between two adjacent columns of color blocking blocks 141, and the colors of the two adjacent columns of color blocking blocks 141 are different, so that the first light-shielding strip 151 can prevent color mixing or color cross between the color blocking blocks with different colors, and the display effect is improved. When the display substrate is applied to the flexible display device, the bending of the display substrate does not cause the first light-shielding bars 151 to shift relative to the color-blocking blocks, thereby avoiding color mixing caused by the bending, and simultaneously, does not cause the first light-shielding bars 151 to shift relative to the pixel area, thereby avoiding aperture ratio loss caused by the bending, and increasing the aperture ratio of the display device. In addition, the via hole 70 does not need to penetrate through the light shielding layer any more, so that the depth of the via hole 70 is further reduced, and the formation of the via hole is facilitated. In the present embodiment, the via holes 70 include a first via hole 71, a third via hole 73, and a fourth via hole 74 which are sleeved, as shown in fig. 6.

The orthographic projection of each second metal wire 52 on the first substrate 11 is set to be located in the range of the orthographic projection of the corresponding first light-shielding bar 151 on the first substrate 11, so that the aperture ratio loss can be reduced to the greatest extent, and the aperture ratio of the display device is increased.

Fig. 7 is a schematic cross-sectional structure diagram of a display substrate according to another embodiment of the disclosure. In one embodiment, as shown in fig. 7, the light shielding layer 15 may be located between the first substrate 11 and the thin film transistor structure layer 30. With this structure, the connection line between the pixel electrode 161 and the second electrode 312 of the thin film transistor no longer needs to pass through the light-shielding layer 15. For example, the material of the light shielding layer 15 may be light shielding resin or opaque metal.

Fig. 8 is a schematic cross-sectional structure view of a display substrate according to another embodiment of the present disclosure. In one embodiment, as shown in fig. 8, the light shielding layer 15 may be located on a side of the pixel electrode layer 16 facing away from the first substrate 11, and for example, the light shielding layer 15 may be located between the pixel electrode layer 16 and the first alignment layer 41. With this structure, the connection line between the pixel electrode 161 and the second electrode 312 of the thin film transistor no longer needs to pass through the light-shielding layer 15. For example, the material of the light-shielding layer 15 may be light-shielding resin.

The light-shielding layer 15 may be disposed on any one of the sides of the first substrate 11 facing the thin film transistor structure layer, and as long as the light-shielding layer 15 and the color resist layer 14 are both disposed on the display substrate, the technical effects of preventing color mixing and reducing loss of aperture ratio can be achieved.

Fig. 9 is a schematic structural diagram illustrating an arrangement of support pillars in a substrate according to an embodiment of the disclosure. The boundaries of the partition trenches, vias 70, and primary and secondary support posts 61, 62 are shown in fig. 9. In one embodiment, as shown in fig. 3, 4 and 9, the display substrate may further include a plurality of main support pillars 61, the main support pillars 61 are located on a side of the pixel electrode layer 16 facing away from the first substrate 11, and an orthographic projection of bottom surfaces of the main support pillars 61 facing the side of the first substrate 11 on the first substrate 11 is located within an orthographic projection range of the partition grooves 142 on the first substrate 11. It should be noted that, on the surface of the display substrate, the area where the blocking groove 142 is located is recessed relative to other areas, the orthographic projection of the bottom surface of the main support post 61 on the first base 11 is set to be located within the orthographic projection range of the blocking groove 142 on the first base 11, and the main support post 61 can be set in the recessed area corresponding to the blocking groove 142, so that, during the bending process of the display device, the main support post 61 can be prevented from sliding due to bending, and the main support post 61 can be stabilized. In addition, the main support post 61 can be prevented from influencing the aperture ratio of the display device in such an arrangement.

In one embodiment, the orthographic projection of the bottom surface of the main support post 61 on the first substrate 11 does not intersect the orthographic projection of the via 70 on the first substrate 11. Therefore, the main support column 61 can avoid the through hole 70, and the main support column 61 is prevented from sliding into the position of the through hole 70 in the bending process of the display device, so that the problem of uneven box thickness caused by the sliding is avoided.

In one embodiment, the central dimension of the bottom surface of the main support post 61 is greater than or equal to 14.5 μm. Such an arrangement can ensure adhesion between the main support post 61 and the second insulating layer 18, and prevent the main support post 61 from falling off. It should be noted that the center of the bottom surface of the main support column 61 is the dimension passing through the center of the bottom surface on the bottom surface of the main support column, for example, when the bottom surface of the main support column 61 is circular, the center of the bottom surface of the main support column 61 is the diameter of the bottom surface of the main support column 61; when the bottom surface of the main support column 61 is a regular polygon, the center dimension of the bottom surface of the main support column 61 is the diameter of the circumscribed circle of the bottom surface of the main support column 61.

In one embodiment, as shown in fig. 3, the display substrate further includes a plurality of sub-supporting pillars 62, the sub-supporting pillars 62 are located on a side of the pixel electrode layer 16 facing away from the first substrate 11, and an orthographic projection of a bottom surface of the sub-supporting pillars 62 facing the first substrate 11 on the first substrate 11 is located within an orthographic projection range of the partition trench 142 on the first substrate 11. By such an arrangement, the auxiliary supporting columns 62 can be prevented from sliding due to bending in the bending process of the display device, and the auxiliary supporting columns 62 can be stabilized. In addition, the arrangement mode can avoid the influence of the auxiliary supporting columns 62 on the aperture ratio of the display device.

The orthographic projection of the bottom surfaces of the secondary support posts 62 on the first substrate 11 does not intersect the orthographic projection of the via holes 70 on the first substrate 11. Therefore, the auxiliary supporting columns 62 can avoid the through holes 70, the auxiliary supporting columns 62 are prevented from sliding into the positions of the through holes 70 in the bending process of the display device, and the problem of uneven box thickness caused by the sliding is avoided.

Illustratively, the height of the secondary support posts 62 may be less than the height of the primary support posts 61. The "height" here is the dimension in the direction perpendicular to the first substrate.

In one embodiment, the center dimension of the bottom surface of the secondary support posts 62 is greater than or equal to 14.5 μm. By such an arrangement, adhesion between the auxiliary supporting posts 62 and the second insulating layer 18 can be ensured, and the auxiliary supporting posts 62 are prevented from falling off. It should be noted that the center dimension of the bottom surface of the secondary support column 62 is the dimension passing through the center of the bottom surface of the secondary support column 62, for example, when the bottom surface of the secondary support column 62 is circular, the center dimension of the bottom surface of the secondary support column 62 is the diameter of the bottom surface of the secondary support column 62; when the bottom surface of the secondary support post 62 is a regular polygon, the center dimension of the bottom surface of the secondary support post 62 is the diameter of a circumscribed circle of the bottom surface of the secondary support post 62.

For an integrated touch display device, such as a TDDI display product, the spacing between adjacent vias 70 is small, and the sub-support posts 62 may be disposed to include a first sub-support post 621 and a second sub-support post 622.

The cross-sectional areas of the main supporting column 61 and the auxiliary supporting column 62 may gradually increase or gradually decrease in a direction away from the first substrate 11, or may remain unchanged, that is, the main supporting column 61 and the auxiliary supporting column 62 may be an inverted cylindrical table, a right cylindrical table or a cylinder, which is not particularly limited herein.

The following briefly describes a process for manufacturing a display substrate according to an embodiment of the present disclosure with reference to fig. 3 and 4.

A barrier layer 43 and a thin film transistor structure layer 30 are sequentially formed on the first substrate 11.

A first insulating layer 13 is formed on a side of the thin film transistor structure layer 30 away from the first substrate 11, the first insulating layer 13 is opened with a first via hole 71, and the second electrode 312 of the thin film transistor is exposed through the first via hole 71.

The light-shielding layer 15 is formed on a side of the first insulating layer 13 away from the first substrate 11, and the light-shielding layer 15 may include a plurality of first light-shielding bars 151 and a plurality of second light-shielding bars 152, where each first light-shielding bar 151 extends along the first direction X and each second light-shielding bar 152 extends along the second direction Y. The orthographic projection of each first metal wire 51 on the first substrate 11 is located within the range of the orthographic projection of the corresponding first light-shielding bar 151 on the first substrate 11, and the orthographic projection of each second metal wire 152 on the first substrate 11 is located within the range of the orthographic projection of the corresponding second light-shielding bar 152 on the first substrate 11. The light shielding layer 15 has a second via hole 72, and an orthographic projection of the second via hole 72 on the first substrate 11 includes an orthographic projection of the first via hole 71 on the first substrate 11.

The color resist layer 14 is formed on a side of the light shielding layer 15 away from the first substrate 11, the color resist layer 14 may include a plurality of rows of color resist blocks 141 arranged along the first direction X, the color of the color resist blocks 141 in the same row may be the same, and the color of the color resist blocks 141 in two adjacent rows may be different. A blocking groove 142 is formed between two adjacent color blocking blocks 141 in the same column.

A planarization layer 17 is formed on the side of the color resist layer 14 facing away from the first substrate 11.

A common electrode layer 19 is formed on the side of the planarization layer 17 facing away from the first substrate 11.

A second insulating layer 18 is formed on the side of the common electrode layer 19 facing away from the first substrate 11, and the second insulating layer 18 and the planarization layer 17 are simultaneously patterned to form a third via 73 and a fourth via 74. Thus, a mask can be saved, and the cost can be reduced.

A pixel electrode layer 16 is formed on a side of the second insulating layer 18 facing away from the first substrate 11, the pixel electrode layer 16 includes a plurality of pixel electrodes 161, and each pixel electrode 161 is connected to the second electrode 312 of the thin film transistor through the fourth via 74, the third via 73, the second via 72, and the first via 71.

A main support post 61 and a sub support post 62 are formed on a side of the pixel electrode layer 16 facing away from the first substrate 11.

In an exemplary embodiment, the first and second insulating layers may employ any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multi-layer, or a composite layer. The gate electrode, the source electrode, the drain electrode, and the metal wire may be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or an alloy material of the above metals, such as aluminum neodymium (AlNd) or molybdenum niobium (MoNb), and may have a single-layer structure or a multi-layer composite structure, such as Ti/Al/Ti, and the like. The pixel defining layer may be made of polyimide, acryl, polyethylene terephthalate, or the like. The active layer may be made of various materials such as amorphous indium gallium zinc Oxide (a-IGZO), zinc oxynitride (ZnON), Indium Zinc Tin Oxide (IZTO), amorphous silicon (a-Si), polysilicon (p-Si), hexathiophene, polythiophene, etc., that is, the present disclosure is applicable to transistors manufactured based on Oxide technology, silicon technology, and organic technology. The light-shielding layer may be made of a material having light-shielding properties, such as a black resin. The common electrode layer and the pixel electrode layer may use a transparent conductive material, such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO).

Fig. 10 is a schematic structural diagram of a display panel according to an embodiment of the disclosure. In one embodiment, as shown in fig. 10, the display panel may include a first substrate 10 and a second substrate 20 disposed opposite to each other, and liquid crystal disposed between the first substrate 10 and the second substrate 20. The first substrate 10 is a display substrate in any of the above embodiments of the present disclosure.

The second substrate 20 includes a second base 21, an overcoat layer (OC)24 disposed on a side of the second base 21 facing the first substrate, and a second alignment layer 42 disposed on a side of the overcoat layer 24 facing the first substrate. The overcoat layer 24 may be a flat layer to ensure flatness of the second substrate.

For example, alignment marks may be formed on the second substrate 20 to facilitate alignment between the second substrate 20 and the display substrate.

Fig. 11 is a schematic structural diagram of a display panel according to another embodiment of the disclosure. In one embodiment, as shown in fig. 11, the display panel includes a first substrate 10 and a second substrate 20 disposed opposite to each other, and a liquid crystal disposed between the first substrate 10 and the second substrate 20, and the first substrate 10 is the display substrate shown in fig. 6. The second substrate 20 includes a second base 21 and a plurality of second light-shielding bars 152 located on a side of the second base 21 facing the display substrate, each second light-shielding bar 152 extends along the first direction, and an orthographic projection of the second pole 312 of the thin film transistor in the display substrate on the first base 11 of the display substrate is located within an orthographic projection range of the corresponding second light-shielding bar 152 on the first base 11.

In this embodiment, in the display substrate, the light-shielding layer is not present at the second electrode 312 of the thin film transistor, but the second electrode 312 is made of a metal material and has a high reflectance. By arranging the second light-shielding bars 152 on the second substrate 20, the second light-shielding bars 152 can shield the second electrodes 312, so that the overall reflectivity of the display panel is reduced, the display effect is improved, and the contrast of the display panel is improved.

Exemplarily, an orthographic projection of the second pole of the thin film transistor on the first substrate is located within a range of an orthographic projection of the second light-shielding bar 152 on the first substrate. Therefore, the second light-shielding bar 152 can completely shield the second pole 312 of the tft, and prevent the second pole 312 from reflecting external light.

In one embodiment, the thin film transistor structure layer of the display substrate further includes a plurality of first metal traces, each of the first metal traces extends along the first direction, and an orthogonal projection of the first metal trace on the first substrate of the display substrate is located within an orthogonal projection range of the corresponding second light-shielding bar 152 on the first substrate of the display substrate. In such a configuration, the second light-shielding bar 152 can shield the first metal trace, thereby preventing the first metal trace from side light leakage.

In one embodiment, the display panel shown in fig. 10 and 11 may be a bendable display panel, and the display panel may be bendable in the first direction. According to the display panel, the color resistance layer and the light shielding layer are arranged on the display substrate, and the color resistance block and the light shielding layer cannot deviate in a bending state, so that color mixing is avoided, and aperture opening ratio loss is avoided.

Based on the inventive concept of the foregoing embodiments, the embodiments of the present disclosure also provide a display device including the display panel employing the foregoing embodiments. The display device may be: any product or component with a display function, such as electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, a wearable display device, and the like.

In the description of the present specification, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present disclosure and to simplify the description, but are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting of the present disclosure.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present disclosure, "a plurality" means two or more unless specifically limited otherwise.

In the present disclosure, unless otherwise expressly stated or limited, the terms "mounted," "connected," "secured," and the like are to be construed broadly and can, for example, be fixedly connected, detachably connected, or integral; the connection can be mechanical connection, electrical connection or communication; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present disclosure can be understood by those of ordinary skill in the art as appropriate.

In the present disclosure, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise the first and second features being in direct contact, or may comprise the first and second features being in contact, not directly, but via another feature in between. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly above and obliquely above the second feature, or simply meaning that the first feature is at a lesser level than the second feature.

The above disclosure provides many different embodiments or examples for implementing different features of the disclosure. The components and arrangements of specific examples are described above to simplify the present disclosure. Of course, they are merely examples and are not intended to limit the present disclosure. Moreover, the present disclosure may repeat reference numerals and/or reference letters in the various examples, which have been repeated for purposes of simplicity and clarity and do not in themselves dictate a relationship between the various embodiments and/or arrangements discussed.

While the present disclosure has been described with reference to specific embodiments, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A display substrate, comprising:

a first substrate;

the shading layer is positioned on one side, facing the thin film transistor structure layer, of the first substrate and comprises a plurality of first shading strips, and orthographic projections of the first shading strips on the first substrate are positioned between orthographic projections of two adjacent color resistance blocks on the first substrate;

and the pixel electrode layer is positioned on one side of the color resistance layer, which is far away from the first substrate, and comprises a plurality of pixel electrodes, each pixel electrode is connected with the corresponding second electrode of the thin film transistor through a corresponding through hole, and the through hole comprises a corresponding first through hole.

2. The display substrate according to claim 1, wherein a blocking groove is disposed between two adjacent color resist blocks in the same column, and an orthographic projection of the via hole on the first substrate is within an orthographic projection range of the blocking groove on the first substrate.

3. The display substrate according to claim 2, wherein a distance between an orthographic projection boundary of the via hole on the first base and an orthographic projection boundary of the partition trench on the first base ranges from 4 μm to 6 μm.

4. The display substrate of claim 1,

the light shielding layer is located between the first insulating layer and the color resistance layer, the light shielding layer is provided with a plurality of second through holes, orthographic projections of the second through holes on the first substrate are at least partially overlapped with orthographic projections of the first through holes on the first substrate, and the through holes further comprise corresponding second through holes; alternatively, the first and second electrodes may be,

the light shielding layer is positioned between the first substrate and the thin film transistor structure layer; alternatively, the first and second electrodes may be,

the light shielding layer is located on one side, away from the first substrate, of the pixel electrode layer.

5. The display substrate according to claim 2 or 3, wherein each of the first light-shielding bars extends along the first direction, the thin film transistor structure layer further includes a plurality of first metal traces, each of the first metal traces extends along the first direction, and an orthogonal projection of the first metal trace on the first substrate is located within an orthogonal projection range of the corresponding first light-shielding bar on the first substrate.

6. The display substrate according to claim 5, wherein an orthographic projection of the partition groove on the first base is within a range of an orthographic projection of the corresponding first light-shielding bar on the first base.

7. The display substrate according to claim 5, wherein the light-shielding layer further includes a plurality of second light-shielding bars, the second light-shielding bars are located between two adjacent columns of color-resisting blocks, the thin film transistor structure layer further includes a plurality of second metal traces, and an orthographic projection of each of the second metal traces on the first substrate is located within an orthographic projection range of the corresponding second light-shielding bar on the first substrate.

8. The display substrate according to claim 7, wherein a distance between an orthographic projection boundary of the first light-shielding bar on the first substrate and an orthographic projection boundary of the corresponding first metal trace on the first substrate is in a range from 0.8 μm to 1.2 μm, and a distance between an orthographic projection boundary of the second light-shielding bar on the first substrate and an orthographic projection boundary of the corresponding second metal trace on the first substrate is in a range from 0.8 μm to 1.2 μm.

9. The display substrate according to any one of claims 1 to 4, wherein each of the first light-shielding bars extends along a second direction, the first light-shielding bar is located between two adjacent columns of color-resistant blocks, the thin film transistor structure layer further includes a plurality of second metal traces, each of the second metal traces extends along the second direction, an orthographic projection of each of the second metal traces on the first substrate is located within an orthographic projection range of the corresponding first light-shielding bar on the first substrate, and the second direction is a direction perpendicular to the first direction.

10. The display substrate according to claim 2, wherein the display substrate further comprises a plurality of main support pillars, the main support pillars are located on a side of the pixel electrode layer facing away from the first substrate, an orthographic projection of a bottom surface of each main support pillar facing the first substrate on the first substrate is located within an orthographic projection range of the partition trench on the first substrate, and the orthographic projection of the bottom surface of each main support pillar on the first substrate does not intersect with the orthographic projection of the via hole on the first substrate.

11. The display substrate according to claim 10, further comprising a plurality of secondary support pillars located on a side of the pixel electrode layer facing away from the first substrate, wherein an orthographic projection of a bottom surface of the secondary support pillar facing the first substrate on the first substrate is within an orthographic projection range of the partition trench on the first substrate, and the orthographic projection of the bottom surface of the secondary support pillar on the first substrate does not intersect with an orthographic projection of the via hole on the first substrate.

12. The display substrate of claim 11, wherein the central dimension of the bottom surface of the primary support posts is greater than or equal to 14.5 μm, and the central dimension of the bottom surface of the secondary support posts is greater than or equal to 14.5 μm.

13. A display panel comprising a first substrate and a second substrate which are disposed opposite to each other, and a liquid crystal disposed between the first substrate and the second substrate, wherein the first substrate is the display substrate according to any one of claims 1 to 12.

14. A display panel, comprising a first substrate and a second substrate disposed opposite to each other, and a liquid crystal disposed between the first substrate and the second substrate, wherein the first substrate is the display substrate according to claim 9, the second substrate includes a second base and a plurality of second light-shielding bars located on a side of the second base facing the display substrate, each of the second light-shielding bars extends along a first direction, and an orthographic projection of a second pole of a thin film transistor in the display substrate on the first base of the display substrate is located within an orthographic projection range of the corresponding second light-shielding bar on the first base.

15. The display panel according to claim 13 or 14, wherein the display panel is a display panel bendable in a first direction.

16. A display device characterized by comprising the display panel according to any one of claims 13 to 15.