CN114267561A

CN114267561A - Delay circuit design method and delay circuit structure of microwave integrated circuit

Info

Publication number: CN114267561A
Application number: CN202111343048.9A
Authority: CN
Inventors: 杨光; 王安劳; 卢子焱; 刘云刚; 蒋冬冬; 张继帆; 韩思扬; 王胜源; 赵伟
Original assignee: CETC 29 Research Institute
Current assignee: CETC 29 Research Institute
Priority date: 2021-11-12
Filing date: 2021-11-12
Publication date: 2022-04-01
Anticipated expiration: 2041-11-12
Also published as: CN114267561B

Abstract

The invention discloses a design method of a delay circuit of a microwave integrated circuit and a delay circuit structure, belonging to the field of microwave integrated circuits, wherein the delay circuit structure comprises a spiral inductor, a capacitor tapped in the middle of the spiral inductor and a grounding through hole; the time delay unit is used for providing reactive loading, and when the unit is periodically loaded, a slow wave structure can be formed, so that a time delay function is realized. In the arrangement method of the delay units, the current directions of the parallel microstrip transmission lines between the adjacent units are the same, the mutual inductance between the adjacent units increases the total inductance, and larger delay amount can be obtained by the same size. Meanwhile, compared with the traditional structure, the delay unit has the same selected inductance and capacitance, so that the direct-current resistance of the inductor is the same. The delay circuit structure realized by the invention has higher quality factor, can obtain lower loss, overcomes the prejudice of the prior art, improves the delay amount of unit area, and has smaller size compared with the traditional delayer.

Description

Delay circuit design method and delay circuit structure of microwave integrated circuit

Technical Field

The present invention relates to the field of microwave integrated circuit technology, and more particularly, to a delay circuit design method and a delay circuit structure of a microwave integrated circuit.

Background

The microwave delayer is a commonly used microwave passive two-port device and has wide application in many fields, such as satellite communication, radar systems, phased array antenna arrays and the like. The main function is to make the electromagnetic wave transmit time delay between two ports for a constant time and compensate the phase difference caused by different frequencies. At present, a numerical control delayer chip designed in a mode of forming a slow wave transmission line by adopting a microwave integrated circuit process is widely applied to a modern broadband radar system.

A conventional delay chip adopts a method of arranging a plurality of delay units in parallel, as shown in fig. 1. The method of periodically loading the multi-delay unit is adopted. The single delay unit comprises a spiral inductor, a capacitor and a grounding through hole, and the equivalent circuit diagram of the structure is shown in figure 2. The problems with this structure are: between adjacent units, the current directions on the parallel microstrip transmission lines are opposite, so that the total inductance is reduced, and the delay amount obtained in unit area is reduced in order to reduce the influence of mutual inductance.

The design direction of the conventional delay circuit structure is to realize structural symmetry, so that a circuit layout can be easily designed into a rectangle, and the whole circuit layout is convenient. However, with the structure of the present invention, the circuit cannot be designed into a regular rectangle, and circuit designers need to take more consideration and optimization into the circuit layout.

Disclosure of Invention

The invention aims to overcome the defects of the prior art and provides a design method of a delay circuit of a microwave integrated circuit and a delay circuit structure, which improve the delay amount of a unit area and have smaller loss and smaller size compared with the traditional delayer.

The purpose of the invention is realized by the following scheme:

a design method of a delay circuit of a microwave integrated circuit comprises the following steps: the mutual inductance between adjacent delay units is utilized to increase the total inductance, so that the same size can obtain larger delay amount.

Further, the increasing the total inductance by using the mutual inductance between the adjacent delay units comprises the sub-steps of: the arrangement design among the delay units: the current directions on the parallel microstrip transmission lines between the adjacent delay units are the same.

Further, the delay unit is designed with a spiral inductor, a capacitor tapped in the middle of the spiral inductor, and a ground via.

Furthermore, the function of the delay unit is to provide a reactance loading, and when the delay unit is loaded periodically, a slow wave structure can be formed, so that a delay function is realized.

Further, the number of the delay units is designed to be plural.

A delay circuit structure obtained according to any one of the design methods comprises a delay unit structure, and the current directions on parallel microstrip transmission lines between adjacent delay units are the same.

Further, the delay unit structure comprises a spiral inductor, a capacitor tapped in the middle of the spiral inductor and a ground through hole.

Further, the number of the delay units is designed to be 10 or more than 10.

The invention has the beneficial effects that:

the invention overcomes the prejudice of the prior art, does not adopt the traditional design direction, adopts an asymmetric structure, ensures that the circuit can not be designed into a regular rectangle, and improves the delay amount of unit area. Compared with the traditional delayer, the delayer has smaller loss and smaller size.

In the embodiment, 10 identical delay circuit units are used for periodic loading, and the simulation performance of the traditional delay circuit structure is compared with that of the delay circuit structure of the invention as follows:

delay amount: in the frequency range of 0.2 GHz-6 GHz, the delay quantity of the circuit of the delay structure is 318.5 +/-3.5 ps; the traditional structure has the retardation of 304.5 +/-6.5 ps; the delay circuit structure of the invention uses the same delay unit, improves the delay amount by more than 5 percent compared with the traditional structure, and has higher delay precision.

Loss: in the frequency range of 0.2 GHz-6 GHz, the loss of the time delay circuit structure is superior to that of the traditional structure, and the average loss of the time delay circuit structure is about 0.2dB less than that of the traditional structure.

Therefore, compared with the prior art, the method overcomes the technical bias and makes remarkable technical progress.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

FIG. 1 is a conventional delay circuit structure;

FIG. 2 is an equivalent circuit of a delay cell;

FIG. 3 shows a delay circuit structure (10 delay units) according to the present invention;

FIG. 4 is a conventional delay circuit structure (10 cells);

FIG. 5 is a comparison of delay amount performance;

fig. 6 is a comparison of loss performance.

Detailed Description

All features disclosed in all embodiments in this specification, or all methods or process steps implicitly disclosed, may be combined and/or expanded, or substituted, in any way, except for mutually exclusive features and/or steps.

In an alternative embodiment, it should be noted that the increasing of the total inductance by using the mutual inductance between the adjacent delay units includes the sub-steps of: the arrangement design among the delay units: the current directions on the parallel microstrip transmission lines between the adjacent delay units are the same.

In an alternative embodiment, it should be noted that the delay unit is designed with a spiral inductor, a capacitor tapped at the center of the spiral inductor, and a ground via.

In an alternative embodiment, it should be noted that the delay unit functions to provide a reactive loading, and when the delay unit is periodically loaded, a slow-wave structure can be formed to implement the delay function.

In an alternative embodiment, it should be noted that the number of the delay units is designed to be multiple.

In an alternative embodiment, it should be noted that the delay unit structure includes a spiral inductor, a capacitor tapped at the center of the spiral inductor, and a ground via.

In an alternative embodiment, it should be noted that the number of the delay units is 10.

The invention aims to provide a novel delay circuit structure, which improves the delay amount of unit area. Compared with the traditional delayer, the delayer has smaller loss and smaller size. To achieve the above object, the present embodiment includes delay units, and an arrangement method of the delay units, wherein:

in a specific application, the delay unit may be a conventional circuit structure, and includes a spiral inductor, a capacitor tapped at the center of the spiral inductor, and a ground via. The time delay unit is used for providing reactive loading, and when the unit is periodically loaded, a slow wave structure can be formed, so that a time delay function is realized.

The arrangement method between the delay units is the main innovation of the embodiment, namely the arrangement method used in the embodiment is shown in fig. 3, it can be seen that the current directions on the parallel microstrip transmission lines between the adjacent units are the same, the mutual inductance between the adjacent units increases the total inductance, and larger delay amount can be obtained with the same size. Meanwhile, compared with the traditional structure that the selected inductance and capacitance of the delay unit are the same, the direct-current resistance of the inductor is the same, and the circuit has higher quality factors and can obtain lower loss.

In a specific application, 10 identical delay circuit units can be used for periodic loading, and the simulation performance of the conventional structure (fig. 4) is compared with that of the structure (fig. 3) of the present invention as follows:

amount of delay (see fig. 5): in the frequency range of 0.2 GHz-6 GHz, the delay quantity of the circuit with the delay circuit structure is 318.5 +/-3.5 ps; the traditional structure has the retardation of 304.5 +/-6.5 ps; the structure of the invention uses the same delay unit, the delay amount is improved by more than 5 percent compared with the traditional structure, and the delay precision is higher.

Loss (see fig. 6): in the frequency range of 0.2 GHz-6 GHz, the circuit loss of the time delay circuit structure is superior to that of the traditional structure, and the average loss of the time delay circuit structure is about 0.2dB less than that of the traditional structure.

Claims

1. A method for designing a delay circuit of a microwave integrated circuit is characterized by comprising the following steps: the mutual inductance between adjacent delay units is utilized to increase the total inductance, so that the same size can obtain larger delay amount.

2. The method of claim 1, wherein the step of increasing the total inductance by mutual inductance between adjacent delay cells comprises the sub-steps of: the arrangement design among the delay units: the current directions on the parallel microstrip transmission lines between the adjacent delay units are the same.

3. The method of claim 1 or 2, wherein the delay unit is designed with a spiral inductor, a capacitor tapped at the center of the spiral inductor, and a ground via.

4. The method of claim 1, wherein the delay unit is configured to provide a reactive loading, and the delay unit is configured to form a slow-wave structure to implement the delay function when periodically loaded.

5. The method of claim 1, wherein the number of the delay units is plural.

6. A delay circuit structure obtained by the design method according to any one of claims 1 to 5, comprising a delay unit structure, wherein the current directions on the parallel microstrip transmission lines between adjacent delay units are the same.

7. The method of claim 6, wherein the delay cell structure comprises a spiral inductor, a capacitor tapped at the center of the spiral inductor, and a ground via.

8. The method of claim 6, wherein the number of the delay cells is 10 or more than 10.